2 class R600Reg <string name, bits<16> encoding> : Register<name> {
3 let Namespace = "AMDGPU";
4 let HWEncoding = encoding;
7 class R600RegWithChan <string name, bits<9> sel, string chan> :
10 field bits<2> chan_encoding = !if(!eq(chan, "X"), 0,
11 !if(!eq(chan, "Y"), 1,
12 !if(!eq(chan, "Z"), 2,
13 !if(!eq(chan, "W"), 3, 0))));
14 let HWEncoding{8-0} = sel;
15 let HWEncoding{10-9} = chan_encoding;
16 let Namespace = "AMDGPU";
19 class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> :
20 RegisterWithSubRegs<n, subregs> {
21 let Namespace = "AMDGPU";
22 let SubRegIndices = [sub0, sub1, sub2, sub3];
23 let HWEncoding = encoding;
26 foreach Index = 0-127 in {
27 foreach Chan = [ "X", "Y", "Z", "W" ] in {
28 // 32-bit Temporary Registers
29 def T#Index#_#Chan : R600RegWithChan <"T"#Index#"."#Chan, Index, Chan>;
31 // Indirect addressing offset registers
32 def Addr#Index#_#Chan : R600RegWithChan <"T("#Index#" + AR.x)."#Chan,
34 def TRegMem#Index#_#Chan : R600RegWithChan <"T"#Index#"."#Chan, Index,
37 // 128-bit Temporary Registers
38 def T#Index#_XYZW : R600Reg_128 <"T"#Index#"",
39 [!cast<Register>("T"#Index#"_X"),
40 !cast<Register>("T"#Index#"_Y"),
41 !cast<Register>("T"#Index#"_Z"),
42 !cast<Register>("T"#Index#"_W")],
47 foreach Index = 159-128 in {
48 foreach Chan = [ "X", "Y", "Z", "W" ] in {
49 // 32-bit Temporary Registers
50 def KC0_#Index#_#Chan : R600RegWithChan <"KC0["#Index#"-128]."#Chan, Index, Chan>;
52 // 128-bit Temporary Registers
53 def KC0_#Index#_XYZW : R600Reg_128 <"KC0["#Index#"-128].XYZW",
54 [!cast<Register>("KC0_"#Index#"_X"),
55 !cast<Register>("KC0_"#Index#"_Y"),
56 !cast<Register>("KC0_"#Index#"_Z"),
57 !cast<Register>("KC0_"#Index#"_W")],
62 foreach Index = 191-160 in {
63 foreach Chan = [ "X", "Y", "Z", "W" ] in {
64 // 32-bit Temporary Registers
65 def KC1_#Index#_#Chan : R600RegWithChan <"KC1["#Index#"-160]."#Chan, Index, Chan>;
67 // 128-bit Temporary Registers
68 def KC1_#Index#_XYZW : R600Reg_128 <"KC1["#Index#"-160].XYZW",
69 [!cast<Register>("KC1_"#Index#"_X"),
70 !cast<Register>("KC1_"#Index#"_Y"),
71 !cast<Register>("KC1_"#Index#"_Z"),
72 !cast<Register>("KC1_"#Index#"_W")],
77 // Array Base Register holding input in FS
78 foreach Index = 448-480 in {
79 def ArrayBase#Index : R600Reg<"ARRAY_BASE", Index>;
85 def ZERO : R600Reg<"0.0", 248>;
86 def ONE : R600Reg<"1.0", 249>;
87 def NEG_ONE : R600Reg<"-1.0", 249>;
88 def ONE_INT : R600Reg<"1", 250>;
89 def HALF : R600Reg<"0.5", 252>;
90 def NEG_HALF : R600Reg<"-0.5", 252>;
91 def ALU_LITERAL_X : R600RegWithChan<"literal.x", 253, "X">;
92 def ALU_LITERAL_Y : R600RegWithChan<"literal.y", 253, "Y">;
93 def ALU_LITERAL_Z : R600RegWithChan<"literal.z", 253, "Z">;
94 def ALU_LITERAL_W : R600RegWithChan<"literal.w", 253, "W">;
95 def PV_X : R600RegWithChan<"PV.X", 254, "X">;
96 def PV_Y : R600RegWithChan<"PV.Y", 254, "Y">;
97 def PV_Z : R600RegWithChan<"PV.Z", 254, "Z">;
98 def PV_W : R600RegWithChan<"PV.W", 254, "W">;
99 def PREDICATE_BIT : R600Reg<"PredicateBit", 0>;
100 def PRED_SEL_OFF: R600Reg<"Pred_sel_off", 0>;
101 def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 2>;
102 def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>;
103 def AR_X : R600Reg<"AR.x", 0>;
104 def OQAP : R600Reg<"OQAP", 221>;
106 def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
107 (add (sequence "ArrayBase%u", 448, 480))>;
108 // special registers for ALU src operands
109 // const buffer reference, SRCx_SEL contains index
110 def ALU_CONST : R600Reg<"CBuf", 0>;
111 // interpolation param reference, SRCx_SEL contains index
112 def ALU_PARAM : R600Reg<"Param", 0>;
114 let isAllocatable = 0 in {
116 // XXX: Only use the X channel, until we support wider stack widths
117 def R600_Addr : RegisterClass <"AMDGPU", [i32], 127, (add (sequence "Addr%u_X", 0, 127))>;
119 } // End isAllocatable = 0
121 def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32,
122 (add (sequence "KC0_%u_X", 128, 159))>;
124 def R600_KC0_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
125 (add (sequence "KC0_%u_Y", 128, 159))>;
127 def R600_KC0_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
128 (add (sequence "KC0_%u_Z", 128, 159))>;
130 def R600_KC0_W : RegisterClass <"AMDGPU", [f32, i32], 32,
131 (add (sequence "KC0_%u_W", 128, 159))>;
133 def R600_KC0 : RegisterClass <"AMDGPU", [f32, i32], 32,
134 (interleave R600_KC0_X, R600_KC0_Y,
135 R600_KC0_Z, R600_KC0_W)>;
137 def R600_KC1_X : RegisterClass <"AMDGPU", [f32, i32], 32,
138 (add (sequence "KC1_%u_X", 160, 191))>;
140 def R600_KC1_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
141 (add (sequence "KC1_%u_Y", 160, 191))>;
143 def R600_KC1_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
144 (add (sequence "KC1_%u_Z", 160, 191))>;
146 def R600_KC1_W : RegisterClass <"AMDGPU", [f32, i32], 32,
147 (add (sequence "KC1_%u_W", 160, 191))>;
149 def R600_KC1 : RegisterClass <"AMDGPU", [f32, i32], 32,
150 (interleave R600_KC1_X, R600_KC1_Y,
151 R600_KC1_Z, R600_KC1_W)>;
153 def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32,
154 (add (sequence "T%u_X", 0, 127), AR_X)>;
156 def R600_TReg32_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
157 (add (sequence "T%u_Y", 0, 127))>;
159 def R600_TReg32_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
160 (add (sequence "T%u_Z", 0, 127))>;
162 def R600_TReg32_W : RegisterClass <"AMDGPU", [f32, i32], 32,
163 (add (sequence "T%u_W", 0, 127))>;
165 def R600_TReg32 : RegisterClass <"AMDGPU", [f32, i32], 32,
166 (interleave R600_TReg32_X, R600_TReg32_Y,
167 R600_TReg32_Z, R600_TReg32_W)>;
169 def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
173 ZERO, HALF, ONE, ONE_INT, PV_X, ALU_LITERAL_X, NEG_ONE, NEG_HALF,
174 ALU_CONST, ALU_PARAM, OQAP
177 def R600_Predicate : RegisterClass <"AMDGPU", [i32], 32, (add
178 PRED_SEL_OFF, PRED_SEL_ZERO, PRED_SEL_ONE)>;
180 def R600_Predicate_Bit: RegisterClass <"AMDGPU", [i32], 32, (add
183 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128,
184 (add (sequence "T%u_XYZW", 0, 127))> {
188 //===----------------------------------------------------------------------===//
189 // Register classes for indirect addressing
190 //===----------------------------------------------------------------------===//
192 // Super register for all the Indirect Registers. This register class is used
193 // by the REG_SEQUENCE instruction to specify the registers to use for direct
194 // reads / writes which may be written / read by an indirect address.
195 class IndirectSuper<string n, list<Register> subregs> :
196 RegisterWithSubRegs<n, subregs> {
197 let Namespace = "AMDGPU";
199 [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
200 sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15];
203 def IndirectSuperReg : IndirectSuper<"Indirect",
204 [TRegMem0_X, TRegMem1_X, TRegMem2_X, TRegMem3_X, TRegMem4_X, TRegMem5_X,
205 TRegMem6_X, TRegMem7_X, TRegMem8_X, TRegMem9_X, TRegMem10_X, TRegMem11_X,
206 TRegMem12_X, TRegMem13_X, TRegMem14_X, TRegMem15_X]
209 def IndirectReg : RegisterClass<"AMDGPU", [f32, i32], 32, (add IndirectSuperReg)>;
211 // This register class defines the registers that are the storage units for
212 // the "Indirect Addressing" pseudo memory space.
213 // XXX: Only use the X channel, until we support wider stack widths
214 def TRegMem : RegisterClass<"AMDGPU", [f32, i32], 32,
215 (add (sequence "TRegMem%u_X", 0, 16))