1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // R600 Tablegen instruction definitions
12 //===----------------------------------------------------------------------===//
14 include "R600Intrinsics.td"
16 class InstR600 <dag outs, dag ins, string asm, list<dag> pattern,
18 : AMDGPUInst <outs, ins, asm, pattern> {
24 bits<2> FlagOperandIdx = 0;
27 bit HasNativeOperands = 0;
29 let Namespace = "AMDGPU";
30 let OutOperandList = outs;
31 let InOperandList = ins;
33 let Pattern = pattern;
36 let TSFlags{4} = Trig;
39 // Vector instructions are instructions that must fill all slots in an
41 let TSFlags{6} = isVector;
42 let TSFlags{8-7} = FlagOperandIdx;
43 let TSFlags{9} = HasNativeOperands;
44 let TSFlags{10} = Op1;
45 let TSFlags{11} = Op2;
48 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
49 InstR600 <outs, ins, asm, pattern, NullALU> {
51 let Namespace = "AMDGPU";
54 def MEMxi : Operand<iPTR> {
55 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
56 let PrintMethod = "printMemOperand";
59 def MEMrr : Operand<iPTR> {
60 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
63 // Operands for non-registers
65 class InstFlag<string PM = "printOperand", int Default = 0>
66 : OperandWithDefaultOps <i32, (ops (i32 Default))> {
70 // src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers
71 def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> {
72 let PrintMethod = "printSel";
75 def LITERAL : InstFlag<"printLiteral">;
77 def WRITE : InstFlag <"printWrite", 1>;
78 def OMOD : InstFlag <"printOMOD">;
79 def REL : InstFlag <"printRel">;
80 def CLAMP : InstFlag <"printClamp">;
81 def NEG : InstFlag <"printNeg">;
82 def ABS : InstFlag <"printAbs">;
83 def UEM : InstFlag <"printUpdateExecMask">;
84 def UP : InstFlag <"printUpdatePred">;
86 // XXX: The r600g finalizer in Mesa expects last to be one in most cases.
87 // Once we start using the packetizer in this backend we should have this
89 def LAST : InstFlag<"printLast", 1>;
91 def FRAMEri : Operand<iPTR> {
92 let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index);
95 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
96 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
97 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
98 def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>;
99 def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>;
100 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
102 class R600ALU_Word0 {
103 field bits<32> Word0;
111 bits<3> index_mode = 0;
115 bits<9> src0_sel = src0{8-0};
116 bits<2> src0_chan = src0{10-9};
117 bits<9> src1_sel = src1{8-0};
118 bits<2> src1_chan = src1{10-9};
120 let Word0{8-0} = src0_sel;
121 let Word0{9} = src0_rel;
122 let Word0{11-10} = src0_chan;
123 let Word0{12} = src0_neg;
124 let Word0{21-13} = src1_sel;
125 let Word0{22} = src1_rel;
126 let Word0{24-23} = src1_chan;
127 let Word0{25} = src1_neg;
128 let Word0{28-26} = index_mode;
129 let Word0{30-29} = pred_sel;
130 let Word0{31} = last;
133 class R600ALU_Word1 {
134 field bits<32> Word1;
137 bits<3> bank_swizzle = 0;
141 bits<7> dst_sel = dst{6-0};
142 bits<2> dst_chan = dst{10-9};
144 let Word1{20-18} = bank_swizzle;
145 let Word1{27-21} = dst_sel;
146 let Word1{28} = dst_rel;
147 let Word1{30-29} = dst_chan;
148 let Word1{31} = clamp;
151 class R600ALU_Word1_OP2 <bits<11> alu_inst> : R600ALU_Word1{
155 bits<1> update_exec_mask;
160 let Word1{0} = src0_abs;
161 let Word1{1} = src1_abs;
162 let Word1{2} = update_exec_mask;
163 let Word1{3} = update_pred;
164 let Word1{4} = write;
165 let Word1{6-5} = omod;
166 let Word1{17-7} = alu_inst;
169 class R600ALU_Word1_OP3 <bits<5> alu_inst> : R600ALU_Word1{
175 bits<9> src2_sel = src2{8-0};
176 bits<2> src2_chan = src2{10-9};
178 let Word1{8-0} = src2_sel;
179 let Word1{9} = src2_rel;
180 let Word1{11-10} = src2_chan;
181 let Word1{12} = src2_neg;
182 let Word1{17-13} = alu_inst;
186 field bits<32> Word0;
190 bits<1> FETCH_WHOLE_QUAD;
194 bits<6> MEGA_FETCH_COUNT;
196 let Word0{4-0} = VC_INST;
197 let Word0{6-5} = FETCH_TYPE;
198 let Word0{7} = FETCH_WHOLE_QUAD;
199 let Word0{15-8} = BUFFER_ID;
200 let Word0{22-16} = SRC_GPR;
201 let Word0{23} = SRC_REL;
202 let Word0{25-24} = SRC_SEL_X;
203 let Word0{31-26} = MEGA_FETCH_COUNT;
206 class VTX_WORD1_GPR {
207 field bits<32> Word1;
214 bits<1> USE_CONST_FIELDS;
216 bits<2> NUM_FORMAT_ALL;
217 bits<1> FORMAT_COMP_ALL;
218 bits<1> SRF_MODE_ALL;
220 let Word1{6-0} = DST_GPR;
221 let Word1{7} = DST_REL;
222 let Word1{8} = 0; // Reserved
223 let Word1{11-9} = DST_SEL_X;
224 let Word1{14-12} = DST_SEL_Y;
225 let Word1{17-15} = DST_SEL_Z;
226 let Word1{20-18} = DST_SEL_W;
227 let Word1{21} = USE_CONST_FIELDS;
228 let Word1{27-22} = DATA_FORMAT;
229 let Word1{29-28} = NUM_FORMAT_ALL;
230 let Word1{30} = FORMAT_COMP_ALL;
231 let Word1{31} = SRF_MODE_ALL;
235 field bits<32> Word0;
239 bits<1> FETCH_WHOLE_QUAD;
244 bits<2> RESOURCE_INDEX_MODE;
245 bits<2> SAMPLER_INDEX_MODE;
247 let Word0{4-0} = TEX_INST;
248 let Word0{6-5} = INST_MOD;
249 let Word0{7} = FETCH_WHOLE_QUAD;
250 let Word0{15-8} = RESOURCE_ID;
251 let Word0{22-16} = SRC_GPR;
252 let Word0{23} = SRC_REL;
253 let Word0{24} = ALT_CONST;
254 let Word0{26-25} = RESOURCE_INDEX_MODE;
255 let Word0{28-27} = SAMPLER_INDEX_MODE;
259 field bits<32> Word1;
268 bits<1> COORD_TYPE_X;
269 bits<1> COORD_TYPE_Y;
270 bits<1> COORD_TYPE_Z;
271 bits<1> COORD_TYPE_W;
273 let Word1{6-0} = DST_GPR;
274 let Word1{7} = DST_REL;
275 let Word1{11-9} = DST_SEL_X;
276 let Word1{14-12} = DST_SEL_Y;
277 let Word1{17-15} = DST_SEL_Z;
278 let Word1{20-18} = DST_SEL_W;
279 let Word1{27-21} = LOD_BIAS;
280 let Word1{28} = COORD_TYPE_X;
281 let Word1{29} = COORD_TYPE_Y;
282 let Word1{30} = COORD_TYPE_Z;
283 let Word1{31} = COORD_TYPE_W;
287 field bits<32> Word2;
298 let Word2{4-0} = OFFSET_X;
299 let Word2{9-5} = OFFSET_Y;
300 let Word2{14-10} = OFFSET_Z;
301 let Word2{19-15} = SAMPLER_ID;
302 let Word2{22-20} = SRC_SEL_X;
303 let Word2{25-23} = SRC_SEL_Y;
304 let Word2{28-26} = SRC_SEL_Z;
305 let Word2{31-29} = SRC_SEL_W;
309 XXX: R600 subtarget uses a slightly different encoding than the other
310 subtargets. We currently handle this in R600MCCodeEmitter, but we may
311 want to use these instruction classes in the future.
313 class R600ALU_Word1_OP2_r600 : R600ALU_Word1_OP2 {
318 let Inst{37} = fog_merge;
319 let Inst{39-38} = omod;
320 let Inst{49-40} = alu_inst;
323 class R600ALU_Word1_OP2_r700 : R600ALU_Word1_OP2 {
327 let Inst{38-37} = omod;
328 let Inst{49-39} = alu_inst;
332 def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),
336 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
338 // Class for instructions with only one source register.
339 // If you add new ins to this instruction, make sure they are listed before
340 // $literal, because the backend currently assumes that the last operand is
341 // a literal. Also be sure to update the enum R600Op1OperandIndex::ROI in
342 // R600Defines.h, R600InstrInfo::buildDefaultInstruction(),
343 // and R600InstrInfo::getOperandIdx().
344 class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
345 InstrItinClass itin = AnyALU> :
346 InstR600 <(outs R600_Reg32:$dst),
347 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
348 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
349 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
350 !strconcat(" ", opName,
351 "$clamp $dst$write$dst_rel$omod, "
352 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
353 "$literal $pred_sel$last"),
357 R600ALU_Word1_OP2 <inst> {
363 let update_exec_mask = 0;
365 let HasNativeOperands = 1;
367 let DisableEncoding = "$literal";
369 let Inst{31-0} = Word0;
370 let Inst{63-32} = Word1;
373 class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
374 InstrItinClass itin = AnyALU> :
375 R600_1OP <inst, opName,
376 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))]
379 // If you add our change the operands for R600_2OP instructions, you must
380 // also update the R600Op2OperandIndex::ROI enum in R600Defines.h,
381 // R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx().
382 class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
383 InstrItinClass itin = AnyALU> :
384 InstR600 <(outs R600_Reg32:$dst),
385 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,
386 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
387 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
388 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
389 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
390 !strconcat(" ", opName,
391 "$clamp $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
392 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
393 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
394 "$literal $pred_sel$last"),
398 R600ALU_Word1_OP2 <inst> {
400 let HasNativeOperands = 1;
402 let DisableEncoding = "$literal";
404 let Inst{31-0} = Word0;
405 let Inst{63-32} = Word1;
408 class R600_2OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
409 InstrItinClass itim = AnyALU> :
410 R600_2OP <inst, opName,
411 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
415 // If you add our change the operands for R600_3OP instructions, you must
416 // also update the R600Op3OperandIndex::ROI enum in R600Defines.h,
417 // R600InstrInfo::buildDefaultInstruction(), and
418 // R600InstrInfo::getOperandIdx().
419 class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
420 InstrItinClass itin = AnyALU> :
421 InstR600 <(outs R600_Reg32:$dst),
422 (ins REL:$dst_rel, CLAMP:$clamp,
423 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
424 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
425 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel,
426 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
427 !strconcat(" ", opName, "$clamp $dst$dst_rel, "
428 "$src0_neg$src0$src0_rel, "
429 "$src1_neg$src1$src1_rel, "
430 "$src2_neg$src2$src2_rel, "
431 "$literal $pred_sel$last"),
435 R600ALU_Word1_OP3<inst>{
437 let HasNativeOperands = 1;
438 let DisableEncoding = "$literal";
441 let Inst{31-0} = Word0;
442 let Inst{63-32} = Word1;
445 class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern,
446 InstrItinClass itin = VecALU> :
447 InstR600 <(outs R600_Reg32:$dst),
453 class R600_TEX <bits<11> inst, string opName, list<dag> pattern,
454 InstrItinClass itin = AnyALU> :
455 InstR600 <(outs R600_Reg128:$DST_GPR),
456 (ins R600_Reg128:$SRC_GPR, i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID, i32imm:$textureTarget),
457 !strconcat(opName, "$DST_GPR, $SRC_GPR, $RESOURCE_ID, $SAMPLER_ID, $textureTarget"),
459 itin>, TEX_WORD0, TEX_WORD1, TEX_WORD2 {
460 let Inst{31-0} = Word0;
461 let Inst{63-32} = Word1;
463 let TEX_INST = inst{4-0};
473 let FETCH_WHOLE_QUAD = 0;
475 let SAMPLER_INDEX_MODE = 0;
477 let COORD_TYPE_X = 0;
478 let COORD_TYPE_Y = 0;
479 let COORD_TYPE_Z = 0;
480 let COORD_TYPE_W = 0;
483 } // End mayLoad = 1, mayStore = 0, hasSideEffects = 0
485 def TEX_SHADOW : PatLeaf<
487 [{uint32_t TType = (uint32_t)N->getZExtValue();
488 return (TType >= 6 && TType <= 8) || (TType >= 11 && TType <= 13);
492 def TEX_RECT : PatLeaf<
494 [{uint32_t TType = (uint32_t)N->getZExtValue();
499 def TEX_ARRAY : PatLeaf<
501 [{uint32_t TType = (uint32_t)N->getZExtValue();
502 return TType == 9 || TType == 10 || TType == 15 || TType == 16;
506 def TEX_SHADOW_ARRAY : PatLeaf<
508 [{uint32_t TType = (uint32_t)N->getZExtValue();
509 return TType == 11 || TType == 12 || TType == 17;
513 class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
514 dag ins, string asm, list<dag> pattern> :
515 InstR600ISA <outs, ins, asm, pattern> {
532 // CF_ALLOC_EXPORT_WORD0_RAT
533 let Inst{3-0} = rat_id;
534 let Inst{9-4} = rat_inst;
535 let Inst{10} = 0; // Reserved
536 let Inst{12-11} = RIM;
537 let Inst{14-13} = TYPE;
538 let Inst{21-15} = RW_GPR;
539 let Inst{22} = RW_REL;
540 let Inst{29-23} = INDEX_GPR;
541 let Inst{31-30} = ELEM_SIZE;
543 // CF_ALLOC_EXPORT_WORD1_BUF
544 let Inst{43-32} = ARRAY_SIZE;
545 let Inst{47-44} = COMP_MASK;
546 let Inst{51-48} = BURST_COUNT;
549 let Inst{61-54} = cf_inst;
551 let Inst{63} = BARRIER;
554 class LoadParamFrag <PatFrag load_type> : PatFrag <
555 (ops node:$ptr), (load_type node:$ptr),
556 [{ return isParamLoad(dyn_cast<LoadSDNode>(N)); }]
559 def load_param : LoadParamFrag<load>;
560 def load_param_zexti8 : LoadParamFrag<zextloadi8>;
561 def load_param_zexti16 : LoadParamFrag<zextloadi16>;
563 def isR600 : Predicate<"Subtarget.device()"
564 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX">;
565 def isR700 : Predicate<"Subtarget.device()"
566 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX &&"
567 "Subtarget.device()->getDeviceFlag()"
568 ">= OCL_DEVICE_RV710">;
569 def isEG : Predicate<
570 "Subtarget.device()->getGeneration() >= AMDGPUDeviceInfo::HD5XXX && "
571 "Subtarget.device()->getGeneration() < AMDGPUDeviceInfo::HD7XXX && "
572 "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">;
574 def isCayman : Predicate<"Subtarget.device()"
575 "->getDeviceFlag() == OCL_DEVICE_CAYMAN">;
576 def isEGorCayman : Predicate<"Subtarget.device()"
577 "->getGeneration() == AMDGPUDeviceInfo::HD5XXX"
578 "|| Subtarget.device()->getGeneration() =="
579 "AMDGPUDeviceInfo::HD6XXX">;
581 def isR600toCayman : Predicate<
582 "Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX">;
584 //===----------------------------------------------------------------------===//
586 //===----------------------------------------------------------------------===//
588 def INTERP_PAIR_XY : AMDGPUShaderInst <
589 (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1),
590 (ins i32imm:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
591 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
594 def INTERP_PAIR_ZW : AMDGPUShaderInst <
595 (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1),
596 (ins i32imm:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
597 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1",
600 def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS",
601 SDTypeProfile<1, -1, [SDTCisInt<0>, SDTCisPtrTy<1>]>,
605 //===----------------------------------------------------------------------===//
606 // Interpolation Instructions
607 //===----------------------------------------------------------------------===//
609 def INTERP_VEC_LOAD : AMDGPUShaderInst <
610 (outs R600_Reg128:$dst),
612 "INTERP_LOAD $src0 : $dst",
615 def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> {
616 let bank_swizzle = 5;
619 def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> {
620 let bank_swizzle = 5;
623 def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>;
625 //===----------------------------------------------------------------------===//
626 // Export Instructions
627 //===----------------------------------------------------------------------===//
629 def ExportType : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
631 def EXPORT: SDNode<"AMDGPUISD::EXPORT", ExportType,
632 [SDNPHasChain, SDNPSideEffect]>;
635 field bits<32> Word0;
642 let Word0{12-0} = arraybase;
643 let Word0{14-13} = type;
644 let Word0{21-15} = gpr;
645 let Word0{22} = 0; // RW_REL
646 let Word0{29-23} = 0; // INDEX_GPR
647 let Word0{31-30} = elem_size;
650 class ExportSwzWord1 {
651 field bits<32> Word1;
660 let Word1{2-0} = sw_x;
661 let Word1{5-3} = sw_y;
662 let Word1{8-6} = sw_z;
663 let Word1{11-9} = sw_w;
666 class ExportBufWord1 {
667 field bits<32> Word1;
674 let Word1{11-0} = arraySize;
675 let Word1{15-12} = compMask;
678 multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
679 def : Pat<(int_R600_store_pixel_depth R600_Reg32:$reg),
681 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
682 0, 61, 0, 7, 7, 7, cf_inst, 0)
685 def : Pat<(int_R600_store_pixel_stencil R600_Reg32:$reg),
687 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
688 0, 61, 7, 0, 7, 7, cf_inst, 0)
691 def : Pat<(int_R600_store_dummy (i32 imm:$type)),
693 (v4f32 (IMPLICIT_DEF)), imm:$type, 0, 7, 7, 7, 7, cf_inst, 0)
696 def : Pat<(int_R600_store_dummy 1),
698 (v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0)
701 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
702 (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)),
703 (ExportInst R600_Reg128:$src, imm:$type, imm:$base,
704 imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0)
709 multiclass SteamOutputExportPattern<Instruction ExportInst,
710 bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> {
712 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
713 (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)),
714 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
715 4095, imm:$mask, buf0inst, 0)>;
717 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
718 (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)),
719 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
720 4095, imm:$mask, buf1inst, 0)>;
722 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
723 (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)),
724 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
725 4095, imm:$mask, buf2inst, 0)>;
727 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
728 (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)),
729 (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
730 4095, imm:$mask, buf3inst, 0)>;
733 // Export Instructions should not be duplicated by TailDuplication pass
734 // (which assumes that duplicable instruction are affected by exec mask)
735 let usesCustomInserter = 1, isNotDuplicable = 1 in {
737 class ExportSwzInst : InstR600ISA<(
739 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
740 i32imm:$sw_x, i32imm:$sw_y, i32imm:$sw_z, i32imm:$sw_w, i32imm:$inst,
742 !strconcat("EXPORT", " $gpr"),
743 []>, ExportWord0, ExportSwzWord1 {
745 let Inst{31-0} = Word0;
746 let Inst{63-32} = Word1;
749 } // End usesCustomInserter = 1
751 class ExportBufInst : InstR600ISA<(
753 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
754 i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop),
755 !strconcat("EXPORT", " $gpr"),
756 []>, ExportWord0, ExportBufWord1 {
758 let Inst{31-0} = Word0;
759 let Inst{63-32} = Word1;
762 //===----------------------------------------------------------------------===//
763 // Control Flow Instructions
764 //===----------------------------------------------------------------------===//
767 field bits<32> Word0;
770 bits<4> KCACHE_BANK0;
771 bits<4> KCACHE_BANK1;
772 bits<2> KCACHE_MODE0;
774 let Word0{21-0} = ADDR;
775 let Word0{25-22} = KCACHE_BANK0;
776 let Word0{29-26} = KCACHE_BANK1;
777 let Word0{31-30} = KCACHE_MODE0;
781 field bits<32> Word1;
783 bits<2> KCACHE_MODE1;
784 bits<8> KCACHE_ADDR0;
785 bits<8> KCACHE_ADDR1;
789 bits<1> WHOLE_QUAD_MODE;
792 let Word1{1-0} = KCACHE_MODE1;
793 let Word1{9-2} = KCACHE_ADDR0;
794 let Word1{17-10} = KCACHE_ADDR1;
795 let Word1{24-18} = COUNT;
796 let Word1{25} = ALT_CONST;
797 let Word1{29-26} = CF_INST;
798 let Word1{30} = WHOLE_QUAD_MODE;
799 let Word1{31} = BARRIER;
802 class ALU_CLAUSE<bits<4> inst, string OpName> : AMDGPUInst <(outs),
803 (ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1, i32imm:$KCACHE_MODE0, i32imm:$KCACHE_MODE1,
804 i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1, i32imm:$COUNT),
805 !strconcat(OpName, " $COUNT, @$ADDR, "
806 "KC0[CB$KCACHE_BANK0:$KCACHE_ADDR0-$KCACHE_ADDR0+32]"
807 ", KC1[CB$KCACHE_BANK1:$KCACHE_ADDR1-$KCACHE_ADDR1+32]"),
808 [] >, CF_ALU_WORD0, CF_ALU_WORD1 {
813 let WHOLE_QUAD_MODE = 0;
816 let Inst{31-0} = Word0;
817 let Inst{63-32} = Word1;
820 class CF_WORD0_R600 {
821 field bits<32> Word0;
828 class CF_WORD1_R600 {
829 field bits<32> Word1;
837 bits<1> END_OF_PROGRAM;
838 bits<1> VALID_PIXEL_MODE;
840 bits<1> WHOLE_QUAD_MODE;
843 let Word1{2-0} = POP_COUNT;
844 let Word1{7-3} = CF_CONST;
845 let Word1{9-8} = COND;
846 let Word1{12-10} = COUNT;
847 let Word1{18-13} = CALL_COUNT;
848 let Word1{19} = COUNT_3;
849 let Word1{21} = END_OF_PROGRAM;
850 let Word1{22} = VALID_PIXEL_MODE;
851 let Word1{29-23} = CF_INST;
852 let Word1{30} = WHOLE_QUAD_MODE;
853 let Word1{31} = BARRIER;
856 class CF_CLAUSE_R600 <bits<7> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
857 ins, AsmPrint, [] >, CF_WORD0_R600, CF_WORD1_R600 {
863 let VALID_PIXEL_MODE = 0;
867 let END_OF_PROGRAM = 0;
868 let WHOLE_QUAD_MODE = 0;
870 let Inst{31-0} = Word0;
871 let Inst{63-32} = Word1;
875 field bits<32> Word0;
878 bits<3> JUMPTABLE_SEL;
880 let Word0{23-0} = ADDR;
881 let Word0{26-24} = JUMPTABLE_SEL;
885 field bits<32> Word1;
891 bits<1> VALID_PIXEL_MODE;
892 bits<1> END_OF_PROGRAM;
896 let Word1{2-0} = POP_COUNT;
897 let Word1{7-3} = CF_CONST;
898 let Word1{9-8} = COND;
899 let Word1{15-10} = COUNT;
900 let Word1{20} = VALID_PIXEL_MODE;
901 let Word1{21} = END_OF_PROGRAM;
902 let Word1{29-22} = CF_INST;
903 let Word1{31} = BARRIER;
906 class CF_CLAUSE_EG <bits<8> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
907 ins, AsmPrint, [] >, CF_WORD0_EG, CF_WORD1_EG {
912 let JUMPTABLE_SEL = 0;
914 let VALID_PIXEL_MODE = 0;
916 let END_OF_PROGRAM = 0;
918 let Inst{31-0} = Word0;
919 let Inst{63-32} = Word1;
922 def CF_ALU : ALU_CLAUSE<8, "ALU">;
923 def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">;
925 def PAD : AMDGPUInst <(outs), (ins), "PAD", [] > {
929 let Predicates = [isR600toCayman] in {
931 //===----------------------------------------------------------------------===//
932 // Common Instructions R600, R700, Evergreen, Cayman
933 //===----------------------------------------------------------------------===//
935 def ADD : R600_2OP_Helper <0x0, "ADD", fadd>;
936 // Non-IEEE MUL: 0 * anything = 0
937 def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE", int_AMDGPU_mul>;
938 def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>;
939 def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax>;
940 def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin>;
942 // For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
943 // so some of the instruction names don't match the asm string.
944 // XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
945 def SETE : R600_2OP <
947 [(set R600_Reg32:$dst,
948 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
954 [(set R600_Reg32:$dst,
955 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
961 [(set R600_Reg32:$dst,
962 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
968 [(set R600_Reg32:$dst,
969 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
973 def SETE_DX10 : R600_2OP <
975 [(set R600_Reg32:$dst,
976 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
980 def SETGT_DX10 : R600_2OP <
982 [(set R600_Reg32:$dst,
983 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
987 def SETGE_DX10 : R600_2OP <
989 [(set R600_Reg32:$dst,
990 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
994 def SETNE_DX10 : R600_2OP <
996 [(set R600_Reg32:$dst,
997 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
1001 def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>;
1002 def TRUNC : R600_1OP_Helper <0x11, "TRUNC", int_AMDGPU_trunc>;
1003 def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>;
1004 def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>;
1005 def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>;
1007 def MOV : R600_1OP <0x19, "MOV", []>;
1009 let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in {
1011 class MOV_IMM <ValueType vt, Operand immType> : AMDGPUInst <
1012 (outs R600_Reg32:$dst),
1018 } // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1
1020 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
1023 (MOV_IMM_I32 imm:$val)
1026 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
1029 (MOV_IMM_F32 fpimm:$val)
1032 def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>;
1033 def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>;
1034 def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>;
1035 def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>;
1037 let hasSideEffects = 1 in {
1039 def KILLGT : R600_2OP <0x2D, "KILLGT", []>;
1041 } // end hasSideEffects
1043 def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>;
1044 def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>;
1045 def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>;
1046 def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>;
1047 def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>;
1048 def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>;
1049 def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", AMDGPUsmax>;
1050 def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", AMDGPUsmin>;
1051 def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", AMDGPUumax>;
1052 def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", AMDGPUumin>;
1054 def SETE_INT : R600_2OP <
1056 [(set (i32 R600_Reg32:$dst),
1057 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))]
1060 def SETGT_INT : R600_2OP <
1062 [(set (i32 R600_Reg32:$dst),
1063 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))]
1066 def SETGE_INT : R600_2OP <
1068 [(set (i32 R600_Reg32:$dst),
1069 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
1072 def SETNE_INT : R600_2OP <
1074 [(set (i32 R600_Reg32:$dst),
1075 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
1078 def SETGT_UINT : R600_2OP <
1080 [(set (i32 R600_Reg32:$dst),
1081 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))]
1084 def SETGE_UINT : R600_2OP <
1086 [(set (i32 R600_Reg32:$dst),
1087 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
1090 def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>;
1091 def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>;
1092 def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>;
1093 def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>;
1095 def CNDE_INT : R600_3OP <
1097 [(set (i32 R600_Reg32:$dst),
1098 (selectcc (i32 R600_Reg32:$src0), 0,
1099 (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
1103 def CNDGE_INT : R600_3OP <
1105 [(set (i32 R600_Reg32:$dst),
1106 (selectcc (i32 R600_Reg32:$src0), 0,
1107 (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
1111 def CNDGT_INT : R600_3OP <
1113 [(set (i32 R600_Reg32:$dst),
1114 (selectcc (i32 R600_Reg32:$src0), 0,
1115 (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
1119 //===----------------------------------------------------------------------===//
1120 // Texture instructions
1121 //===----------------------------------------------------------------------===//
1123 def TEX_LD : R600_TEX <
1125 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txf R600_Reg128:$SRC_GPR,
1126 imm:$OFFSET_X, imm:$OFFSET_Y, imm:$OFFSET_Z, imm:$RESOURCE_ID,
1127 imm:$SAMPLER_ID, imm:$textureTarget))]
1129 let AsmString = "TEX_LD $DST_GPR, $SRC_GPR, $OFFSET_X, $OFFSET_Y, $OFFSET_Z,"
1130 "$RESOURCE_ID, $SAMPLER_ID, $textureTarget";
1131 let InOperandList = (ins R600_Reg128:$SRC_GPR, i32imm:$OFFSET_X,
1132 i32imm:$OFFSET_Y, i32imm:$OFFSET_Z, i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID,
1133 i32imm:$textureTarget);
1136 def TEX_GET_TEXTURE_RESINFO : R600_TEX <
1137 0x04, "TEX_GET_TEXTURE_RESINFO",
1138 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txq R600_Reg128:$SRC_GPR,
1139 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1142 def TEX_GET_GRADIENTS_H : R600_TEX <
1143 0x07, "TEX_GET_GRADIENTS_H",
1144 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_ddx R600_Reg128:$SRC_GPR,
1145 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1148 def TEX_GET_GRADIENTS_V : R600_TEX <
1149 0x08, "TEX_GET_GRADIENTS_V",
1150 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_ddy R600_Reg128:$SRC_GPR,
1151 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1154 def TEX_SET_GRADIENTS_H : R600_TEX <
1155 0x0B, "TEX_SET_GRADIENTS_H",
1159 def TEX_SET_GRADIENTS_V : R600_TEX <
1160 0x0C, "TEX_SET_GRADIENTS_V",
1164 def TEX_SAMPLE : R600_TEX <
1166 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_tex R600_Reg128:$SRC_GPR,
1167 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1170 def TEX_SAMPLE_C : R600_TEX <
1171 0x18, "TEX_SAMPLE_C",
1172 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_tex R600_Reg128:$SRC_GPR,
1173 imm:$RESOURCE_ID, imm:$SAMPLER_ID, TEX_SHADOW:$textureTarget))]
1176 def TEX_SAMPLE_L : R600_TEX <
1177 0x11, "TEX_SAMPLE_L",
1178 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txl R600_Reg128:$SRC_GPR,
1179 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1182 def TEX_SAMPLE_C_L : R600_TEX <
1183 0x19, "TEX_SAMPLE_C_L",
1184 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txl R600_Reg128:$SRC_GPR,
1185 imm:$RESOURCE_ID, imm:$SAMPLER_ID, TEX_SHADOW:$textureTarget))]
1188 def TEX_SAMPLE_LB : R600_TEX <
1189 0x12, "TEX_SAMPLE_LB",
1190 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txb R600_Reg128:$SRC_GPR,
1191 imm:$RESOURCE_ID, imm:$SAMPLER_ID, imm:$textureTarget))]
1194 def TEX_SAMPLE_C_LB : R600_TEX <
1195 0x1A, "TEX_SAMPLE_C_LB",
1196 [(set R600_Reg128:$DST_GPR, (int_AMDGPU_txb R600_Reg128:$SRC_GPR,
1197 imm:$RESOURCE_ID, imm:$SAMPLER_ID, TEX_SHADOW:$textureTarget))]
1200 def TEX_SAMPLE_G : R600_TEX <
1201 0x14, "TEX_SAMPLE_G",
1205 def TEX_SAMPLE_C_G : R600_TEX <
1206 0x1C, "TEX_SAMPLE_C_G",
1210 //===----------------------------------------------------------------------===//
1211 // Helper classes for common instructions
1212 //===----------------------------------------------------------------------===//
1214 class MUL_LIT_Common <bits<5> inst> : R600_3OP <
1219 class MULADD_Common <bits<5> inst> : R600_3OP <
1224 class MULADD_IEEE_Common <bits<5> inst> : R600_3OP <
1225 inst, "MULADD_IEEE",
1226 [(set (f32 R600_Reg32:$dst),
1227 (fadd (fmul R600_Reg32:$src0, R600_Reg32:$src1), R600_Reg32:$src2))]
1230 class CNDE_Common <bits<5> inst> : R600_3OP <
1232 [(set R600_Reg32:$dst,
1233 (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
1234 (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
1238 class CNDGT_Common <bits<5> inst> : R600_3OP <
1240 [(set R600_Reg32:$dst,
1241 (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
1242 (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
1246 class CNDGE_Common <bits<5> inst> : R600_3OP <
1248 [(set R600_Reg32:$dst,
1249 (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
1250 (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
1254 multiclass DOT4_Common <bits<11> inst> {
1256 def _pseudo : R600_REDUCTION <inst,
1257 (ins R600_Reg128:$src0, R600_Reg128:$src1),
1258 "DOT4 $dst $src0, $src1",
1259 [(set R600_Reg32:$dst, (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1))]
1262 def _real : R600_2OP <inst, "DOT4", []>;
1265 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
1266 multiclass CUBE_Common <bits<11> inst> {
1268 def _pseudo : InstR600 <
1269 (outs R600_Reg128:$dst),
1270 (ins R600_Reg128:$src),
1272 [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))],
1278 def _real : R600_2OP <inst, "CUBE", []>;
1280 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
1282 class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1283 inst, "EXP_IEEE", fexp2
1286 class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper <
1287 inst, "FLT_TO_INT", fp_to_sint
1290 class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1291 inst, "INT_TO_FLT", sint_to_fp
1294 class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1295 inst, "FLT_TO_UINT", fp_to_uint
1298 class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1299 inst, "UINT_TO_FLT", uint_to_fp
1302 class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP <
1303 inst, "LOG_CLAMPED", []
1306 class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1307 inst, "LOG_IEEE", flog2
1310 class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>;
1311 class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>;
1312 class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>;
1313 class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper <
1314 inst, "MULHI_INT", mulhs
1316 class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper <
1317 inst, "MULHI", mulhu
1319 class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper <
1320 inst, "MULLO_INT", mul
1322 class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []>;
1324 class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP <
1325 inst, "RECIP_CLAMPED", []
1328 class RECIP_IEEE_Common <bits<11> inst> : R600_1OP <
1329 inst, "RECIP_IEEE", [(set R600_Reg32:$dst, (fdiv FP_ONE, R600_Reg32:$src0))]
1332 class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1333 inst, "RECIP_UINT", AMDGPUurecip
1336 class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper <
1337 inst, "RECIPSQRT_CLAMPED", int_AMDGPU_rsq
1340 class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP <
1341 inst, "RECIPSQRT_IEEE", []
1344 class SIN_Common <bits<11> inst> : R600_1OP <
1349 class COS_Common <bits<11> inst> : R600_1OP <
1354 //===----------------------------------------------------------------------===//
1355 // Helper patterns for complex intrinsics
1356 //===----------------------------------------------------------------------===//
1358 multiclass DIV_Common <InstR600 recip_ieee> {
1360 (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
1361 (MUL_IEEE R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
1365 (fdiv R600_Reg32:$src0, R600_Reg32:$src1),
1366 (MUL_IEEE R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
1370 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> : Pat <
1371 (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w),
1372 (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x))
1375 //===----------------------------------------------------------------------===//
1376 // R600 / R700 Instructions
1377 //===----------------------------------------------------------------------===//
1379 let Predicates = [isR600] in {
1381 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
1382 def MULADD_r600 : MULADD_Common<0x10>;
1383 def MULADD_IEEE_r600 : MULADD_IEEE_Common<0x14>;
1384 def CNDE_r600 : CNDE_Common<0x18>;
1385 def CNDGT_r600 : CNDGT_Common<0x19>;
1386 def CNDGE_r600 : CNDGE_Common<0x1A>;
1387 defm DOT4_r600 : DOT4_Common<0x50>;
1388 defm CUBE_r600 : CUBE_Common<0x52>;
1389 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
1390 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
1391 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
1392 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
1393 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
1394 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
1395 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
1396 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
1397 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
1398 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
1399 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
1400 def SIN_r600 : SIN_Common<0x6E>;
1401 def COS_r600 : COS_Common<0x6F>;
1402 def ASHR_r600 : ASHR_Common<0x70>;
1403 def LSHR_r600 : LSHR_Common<0x71>;
1404 def LSHL_r600 : LSHL_Common<0x72>;
1405 def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
1406 def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
1407 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
1408 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
1409 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
1411 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
1412 def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL, R600_Reg32>;
1413 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
1415 def : Pat<(fsqrt R600_Reg32:$src),
1416 (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_r600 R600_Reg32:$src))>;
1418 def R600_ExportSwz : ExportSwzInst {
1419 let Word1{20-17} = 0; // BURST_COUNT
1420 let Word1{21} = eop;
1421 let Word1{22} = 1; // VALID_PIXEL_MODE
1422 let Word1{30-23} = inst;
1423 let Word1{31} = 1; // BARRIER
1425 defm : ExportPattern<R600_ExportSwz, 39>;
1427 def R600_ExportBuf : ExportBufInst {
1428 let Word1{20-17} = 0; // BURST_COUNT
1429 let Word1{21} = eop;
1430 let Word1{22} = 1; // VALID_PIXEL_MODE
1431 let Word1{30-23} = inst;
1432 let Word1{31} = 1; // BARRIER
1434 defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>;
1436 def CF_TC_R600 : CF_CLAUSE_R600<1, (ins i32imm:$ADDR, i32imm:$COUNT),
1437 "TEX $COUNT @$ADDR"> {
1440 def CF_VC_R600 : CF_CLAUSE_R600<2, (ins i32imm:$ADDR, i32imm:$COUNT),
1441 "VTX $COUNT @$ADDR"> {
1444 def WHILE_LOOP_R600 : CF_CLAUSE_R600<6, (ins i32imm:$ADDR),
1445 "LOOP_START_DX10 @$ADDR"> {
1449 def END_LOOP_R600 : CF_CLAUSE_R600<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1453 def LOOP_BREAK_R600 : CF_CLAUSE_R600<9, (ins i32imm:$ADDR),
1454 "LOOP_BREAK @$ADDR"> {
1458 def CF_CONTINUE_R600 : CF_CLAUSE_R600<8, (ins i32imm:$ADDR),
1459 "CONTINUE @$ADDR"> {
1463 def CF_JUMP_R600 : CF_CLAUSE_R600<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1464 "JUMP @$ADDR POP:$POP_COUNT"> {
1467 def CF_ELSE_R600 : CF_CLAUSE_R600<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1468 "ELSE @$ADDR POP:$POP_COUNT"> {
1471 def CF_CALL_FS_R600 : CF_CLAUSE_R600<19, (ins), "CALL_FS"> {
1476 def POP_R600 : CF_CLAUSE_R600<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1477 "POP @$ADDR POP:$POP_COUNT"> {
1480 def CF_END_R600 : CF_CLAUSE_R600<0, (ins), "CF_END"> {
1484 let END_OF_PROGRAM = 1;
1489 // Helper pattern for normalizing inputs to triginomic instructions for R700+
1491 class COS_PAT <InstR600 trig> : Pat<
1492 (fcos R600_Reg32:$src),
1493 (trig (MUL_IEEE (MOV_IMM_I32 CONST.TWO_PI_INV), R600_Reg32:$src))
1496 class SIN_PAT <InstR600 trig> : Pat<
1497 (fsin R600_Reg32:$src),
1498 (trig (MUL_IEEE (MOV_IMM_I32 CONST.TWO_PI_INV), R600_Reg32:$src))
1501 //===----------------------------------------------------------------------===//
1502 // R700 Only instructions
1503 //===----------------------------------------------------------------------===//
1505 let Predicates = [isR700] in {
1506 def SIN_r700 : SIN_Common<0x6E>;
1507 def COS_r700 : COS_Common<0x6F>;
1509 // R700 normalizes inputs to SIN/COS the same as EG
1510 def : SIN_PAT <SIN_r700>;
1511 def : COS_PAT <COS_r700>;
1514 //===----------------------------------------------------------------------===//
1515 // Evergreen Only instructions
1516 //===----------------------------------------------------------------------===//
1518 let Predicates = [isEG] in {
1520 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>;
1521 defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
1523 def MULLO_INT_eg : MULLO_INT_Common<0x8F>;
1524 def MULHI_INT_eg : MULHI_INT_Common<0x90>;
1525 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
1526 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
1527 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
1528 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>;
1529 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
1530 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
1531 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>;
1532 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>;
1533 def SIN_eg : SIN_Common<0x8D>;
1534 def COS_eg : COS_Common<0x8E>;
1536 def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL, R600_Reg32>;
1537 def : SIN_PAT <SIN_eg>;
1538 def : COS_PAT <COS_eg>;
1539 def : Pat<(fsqrt R600_Reg32:$src),
1540 (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_eg R600_Reg32:$src))>;
1541 } // End Predicates = [isEG]
1543 //===----------------------------------------------------------------------===//
1544 // Evergreen / Cayman Instructions
1545 //===----------------------------------------------------------------------===//
1547 let Predicates = [isEGorCayman] in {
1549 // BFE_UINT - bit_extract, an optimization for mask and shift
1554 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width)
1559 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0
1560 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8
1561 // (16,8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16
1562 // (24,8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24
1563 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT",
1564 [(set R600_Reg32:$dst, (int_AMDIL_bit_extract_u32 R600_Reg32:$src0,
1566 R600_Reg32:$src2))],
1570 def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", []>;
1571 defm : BFIPatterns <BFI_INT_eg>;
1573 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT",
1574 [(set R600_Reg32:$dst, (AMDGPUbitalign R600_Reg32:$src0, R600_Reg32:$src1,
1575 R600_Reg32:$src2))],
1579 def MULADD_eg : MULADD_Common<0x14>;
1580 def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>;
1581 def ASHR_eg : ASHR_Common<0x15>;
1582 def LSHR_eg : LSHR_Common<0x16>;
1583 def LSHL_eg : LSHL_Common<0x17>;
1584 def CNDE_eg : CNDE_Common<0x19>;
1585 def CNDGT_eg : CNDGT_Common<0x1A>;
1586 def CNDGE_eg : CNDGE_Common<0x1B>;
1587 def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
1588 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
1589 defm DOT4_eg : DOT4_Common<0xBE>;
1590 defm CUBE_eg : CUBE_Common<0xC0>;
1592 let hasSideEffects = 1 in {
1593 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", []>;
1596 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
1598 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
1602 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
1604 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
1608 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
1610 // TRUNC is used for the FLT_TO_INT instructions to work around a
1611 // perceived problem where the rounding modes are applied differently
1612 // depending on the instruction and the slot they are in.
1614 // https://bugs.freedesktop.org/show_bug.cgi?id=50232
1615 // Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c
1617 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
1618 // which do not need to be truncated since the fp values are 0.0f or 1.0f.
1619 // We should look into handling these cases separately.
1620 def : Pat<(fp_to_sint R600_Reg32:$src0),
1621 (FLT_TO_INT_eg (TRUNC R600_Reg32:$src0))>;
1623 def : Pat<(fp_to_uint R600_Reg32:$src0),
1624 (FLT_TO_UINT_eg (TRUNC R600_Reg32:$src0))>;
1626 def EG_ExportSwz : ExportSwzInst {
1627 let Word1{19-16} = 0; // BURST_COUNT
1628 let Word1{20} = 1; // VALID_PIXEL_MODE
1629 let Word1{21} = eop;
1630 let Word1{29-22} = inst;
1631 let Word1{30} = 0; // MARK
1632 let Word1{31} = 1; // BARRIER
1634 defm : ExportPattern<EG_ExportSwz, 83>;
1636 def EG_ExportBuf : ExportBufInst {
1637 let Word1{19-16} = 0; // BURST_COUNT
1638 let Word1{20} = 1; // VALID_PIXEL_MODE
1639 let Word1{21} = eop;
1640 let Word1{29-22} = inst;
1641 let Word1{30} = 0; // MARK
1642 let Word1{31} = 1; // BARRIER
1644 defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>;
1646 def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT),
1647 "TEX $COUNT @$ADDR"> {
1650 def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT),
1651 "VTX $COUNT @$ADDR"> {
1654 def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR),
1655 "LOOP_START_DX10 @$ADDR"> {
1659 def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1663 def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR),
1664 "LOOP_BREAK @$ADDR"> {
1668 def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR),
1669 "CONTINUE @$ADDR"> {
1673 def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1674 "JUMP @$ADDR POP:$POP_COUNT"> {
1677 def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1678 "ELSE @$ADDR POP:$POP_COUNT"> {
1681 def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> {
1686 def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1687 "POP @$ADDR POP:$POP_COUNT"> {
1690 def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> {
1694 let END_OF_PROGRAM = 1;
1697 //===----------------------------------------------------------------------===//
1698 // Memory read/write instructions
1699 //===----------------------------------------------------------------------===//
1700 let usesCustomInserter = 1 in {
1702 class RAT_WRITE_CACHELESS_eg <dag ins, bits<4> comp_mask, string name,
1704 : EG_CF_RAT <0x57, 0x2, 0, (outs), ins,
1705 !strconcat(name, " $rw_gpr, $index_gpr, $eop"), pattern> {
1707 // XXX: Have a separate instruction for non-indexed writes.
1713 let COMP_MASK = comp_mask;
1714 let BURST_COUNT = 0;
1720 } // End usesCustomInserter = 1
1723 def RAT_WRITE_CACHELESS_32_eg : RAT_WRITE_CACHELESS_eg <
1724 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1725 0x1, "RAT_WRITE_CACHELESS_32_eg",
1726 [(global_store (i32 R600_TReg32_X:$rw_gpr), R600_TReg32_X:$index_gpr)]
1730 def RAT_WRITE_CACHELESS_128_eg : RAT_WRITE_CACHELESS_eg <
1731 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
1732 0xf, "RAT_WRITE_CACHELESS_128",
1733 [(global_store (v4i32 R600_Reg128:$rw_gpr), R600_TReg32_X:$index_gpr)]
1736 class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
1737 : InstR600ISA <outs, (ins MEMxi:$ptr), name#" $dst, $ptr", pattern>,
1738 VTX_WORD1_GPR, VTX_WORD0 {
1743 let FETCH_WHOLE_QUAD = 0;
1744 let BUFFER_ID = buffer_id;
1746 // XXX: We can infer this field based on the SRC_GPR. This would allow us
1747 // to store vertex addresses in any channel, not just X.
1750 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL,
1751 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored,
1752 // however, based on my testing if USE_CONST_FIELDS is set, then all
1753 // these fields need to be set to 0.
1754 let USE_CONST_FIELDS = 0;
1755 let NUM_FORMAT_ALL = 1;
1756 let FORMAT_COMP_ALL = 0;
1757 let SRF_MODE_ALL = 0;
1759 let Inst{31-0} = Word0;
1760 let Inst{63-32} = Word1;
1761 // LLVM can only encode 64-bit instructions, so these fields are manually
1762 // encoded in R600CodeEmitter
1765 // bits<2> ENDIAN_SWAP = 0;
1766 // bits<1> CONST_BUF_NO_STRIDE = 0;
1767 // bits<1> MEGA_FETCH = 0;
1768 // bits<1> ALT_CONST = 0;
1769 // bits<2> BUFFER_INDEX_MODE = 0;
1773 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1774 // is done in R600CodeEmitter
1776 // Inst{79-64} = OFFSET;
1777 // Inst{81-80} = ENDIAN_SWAP;
1778 // Inst{82} = CONST_BUF_NO_STRIDE;
1779 // Inst{83} = MEGA_FETCH;
1780 // Inst{84} = ALT_CONST;
1781 // Inst{86-85} = BUFFER_INDEX_MODE;
1782 // Inst{95-86} = 0; Reserved
1784 // VTX_WORD3 (Padding)
1786 // Inst{127-96} = 0;
1789 class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
1790 : VTX_READ_eg <"VTX_READ_8", buffer_id, (outs R600_TReg32_X:$dst),
1793 let MEGA_FETCH_COUNT = 1;
1795 let DST_SEL_Y = 7; // Masked
1796 let DST_SEL_Z = 7; // Masked
1797 let DST_SEL_W = 7; // Masked
1798 let DATA_FORMAT = 1; // FMT_8
1801 class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern>
1802 : VTX_READ_eg <"VTX_READ_16", buffer_id, (outs R600_TReg32_X:$dst),
1804 let MEGA_FETCH_COUNT = 2;
1806 let DST_SEL_Y = 7; // Masked
1807 let DST_SEL_Z = 7; // Masked
1808 let DST_SEL_W = 7; // Masked
1809 let DATA_FORMAT = 5; // FMT_16
1813 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
1814 : VTX_READ_eg <"VTX_READ_32", buffer_id, (outs R600_TReg32_X:$dst),
1817 let MEGA_FETCH_COUNT = 4;
1819 let DST_SEL_Y = 7; // Masked
1820 let DST_SEL_Z = 7; // Masked
1821 let DST_SEL_W = 7; // Masked
1822 let DATA_FORMAT = 0xD; // COLOR_32
1824 // This is not really necessary, but there were some GPU hangs that appeared
1825 // to be caused by ALU instructions in the next instruction group that wrote
1826 // to the $ptr registers of the VTX_READ.
1828 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
1829 // %T2_X<def> = MOV %ZERO
1830 //Adding this constraint prevents this from happening.
1831 let Constraints = "$ptr.ptr = $dst";
1834 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
1835 : VTX_READ_eg <"VTX_READ_128", buffer_id, (outs R600_Reg128:$dst),
1838 let MEGA_FETCH_COUNT = 16;
1843 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
1845 // XXX: Need to force VTX_READ_128 instructions to write to the same register
1846 // that holds its buffer address to avoid potential hangs. We can't use
1847 // the same constraint as VTX_READ_32_eg, because the $ptr.ptr and $dst
1848 // registers are different sizes.
1851 //===----------------------------------------------------------------------===//
1852 // VTX Read from parameter memory space
1853 //===----------------------------------------------------------------------===//
1855 def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <0,
1856 [(set (i32 R600_TReg32_X:$dst), (load_param_zexti8 ADDRVTX_READ:$ptr))]
1859 def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <0,
1860 [(set (i32 R600_TReg32_X:$dst), (load_param_zexti16 ADDRVTX_READ:$ptr))]
1863 def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <0,
1864 [(set (i32 R600_TReg32_X:$dst), (load_param ADDRVTX_READ:$ptr))]
1867 def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <0,
1868 [(set (v4i32 R600_Reg128:$dst), (load_param ADDRVTX_READ:$ptr))]
1871 //===----------------------------------------------------------------------===//
1872 // VTX Read from global memory space
1873 //===----------------------------------------------------------------------===//
1876 def VTX_READ_GLOBAL_8_eg : VTX_READ_8_eg <1,
1877 [(set (i32 R600_TReg32_X:$dst), (zextloadi8_global ADDRVTX_READ:$ptr))]
1881 def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1,
1882 [(set (i32 R600_TReg32_X:$dst), (global_load ADDRVTX_READ:$ptr))]
1886 def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1,
1887 [(set (v4i32 R600_Reg128:$dst), (global_load ADDRVTX_READ:$ptr))]
1890 //===----------------------------------------------------------------------===//
1892 // XXX: We are currently storing all constants in the global address space.
1893 //===----------------------------------------------------------------------===//
1895 def CONSTANT_LOAD_eg : VTX_READ_32_eg <1,
1896 [(set (i32 R600_TReg32_X:$dst), (constant_load ADDRVTX_READ:$ptr))]
1901 //===----------------------------------------------------------------------===//
1902 // Regist loads and stores - for indirect addressing
1903 //===----------------------------------------------------------------------===//
1905 defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>;
1907 let Predicates = [isCayman] in {
1909 let isVector = 1 in {
1911 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
1913 def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
1914 def MULHI_INT_cm : MULHI_INT_Common<0x90>;
1915 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
1916 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
1917 def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>;
1918 def EXP_IEEE_cm : EXP_IEEE_Common<0x81>;
1919 def LOG_IEEE_cm : LOG_IEEE_Common<0x83>;
1920 def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>;
1921 def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>;
1922 def SIN_cm : SIN_Common<0x8D>;
1923 def COS_cm : COS_Common<0x8E>;
1924 } // End isVector = 1
1926 def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL, R600_Reg32>;
1927 def : SIN_PAT <SIN_cm>;
1928 def : COS_PAT <COS_cm>;
1930 defm DIV_cm : DIV_Common<RECIP_IEEE_cm>;
1932 // RECIP_UINT emulation for Cayman
1933 // The multiplication scales from [0,1] to the unsigned integer range
1935 (AMDGPUurecip R600_Reg32:$src0),
1936 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg R600_Reg32:$src0)),
1937 (MOV_IMM_I32 CONST.FP_UINT_MAX_PLUS_1)))
1940 def CF_END_CM : CF_CLAUSE_EG<32, (ins), "CF_END"> {
1946 def : Pat<(fsqrt R600_Reg32:$src),
1947 (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm R600_Reg32:$src))>;
1951 //===----------------------------------------------------------------------===//
1952 // Branch Instructions
1953 //===----------------------------------------------------------------------===//
1956 def IF_PREDICATE_SET : ILFormat<(outs), (ins GPRI32:$src),
1957 "IF_PREDICATE_SET $src", []>;
1959 def PREDICATED_BREAK : ILFormat<(outs), (ins GPRI32:$src),
1960 "PREDICATED_BREAK $src", []>;
1962 //===----------------------------------------------------------------------===//
1963 // Pseudo instructions
1964 //===----------------------------------------------------------------------===//
1966 let isPseudo = 1 in {
1968 def PRED_X : InstR600 <
1969 (outs R600_Predicate_Bit:$dst),
1970 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
1972 let FlagOperandIdx = 3;
1975 let isTerminator = 1, isBranch = 1 in {
1976 def JUMP_COND : InstR600 <
1978 (ins brtarget:$target, R600_Predicate_Bit:$p),
1979 "JUMP $target ($p)",
1983 def JUMP : InstR600 <
1985 (ins brtarget:$target),
1990 let isPredicable = 1;
1994 } // End isTerminator = 1, isBranch = 1
1996 let usesCustomInserter = 1 in {
1998 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
2000 def MASK_WRITE : AMDGPUShaderInst <
2002 (ins R600_Reg32:$src),
2007 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 1
2011 (outs R600_Reg128:$dst),
2012 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
2013 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
2014 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$resourceId, imm:$samplerId, imm:$textureTarget))], NullALU> {
2017 def TXD_SHADOW: InstR600 <
2018 (outs R600_Reg128:$dst),
2019 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
2020 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
2021 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))], NullALU
2024 } // End isPseudo = 1
2025 } // End usesCustomInserter = 1
2027 def CLAMP_R600 : CLAMP <R600_Reg32>;
2028 def FABS_R600 : FABS<R600_Reg32>;
2029 def FNEG_R600 : FNEG<R600_Reg32>;
2031 //===---------------------------------------------------------------------===//
2032 // Return instruction
2033 //===---------------------------------------------------------------------===//
2034 let isTerminator = 1, isReturn = 1, hasCtrlDep = 1,
2035 usesCustomInserter = 1 in {
2036 def RETURN : ILFormat<(outs), (ins variable_ops),
2037 "RETURN", [(IL_retflag)]>;
2041 //===----------------------------------------------------------------------===//
2042 // Constant Buffer Addressing Support
2043 //===----------------------------------------------------------------------===//
2045 let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
2046 def CONST_COPY : Instruction {
2047 let OutOperandList = (outs R600_Reg32:$dst);
2048 let InOperandList = (ins i32imm:$src);
2050 [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))];
2051 let AsmString = "CONST_COPY";
2052 let neverHasSideEffects = 1;
2053 let isAsCheapAsAMove = 1;
2054 let Itinerary = NullALU;
2056 } // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"
2058 def TEX_VTX_CONSTBUF :
2059 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "VTX_READ_eg $dst, $ptr",
2060 [(set R600_Reg128:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$BUFFER_ID)))]>,
2061 VTX_WORD1_GPR, VTX_WORD0 {
2065 let FETCH_WHOLE_QUAD = 0;
2069 let USE_CONST_FIELDS = 0;
2070 let NUM_FORMAT_ALL = 2;
2071 let FORMAT_COMP_ALL = 1;
2072 let SRF_MODE_ALL = 1;
2073 let MEGA_FETCH_COUNT = 16;
2078 let DATA_FORMAT = 35;
2080 let Inst{31-0} = Word0;
2081 let Inst{63-32} = Word1;
2083 // LLVM can only encode 64-bit instructions, so these fields are manually
2084 // encoded in R600CodeEmitter
2087 // bits<2> ENDIAN_SWAP = 0;
2088 // bits<1> CONST_BUF_NO_STRIDE = 0;
2089 // bits<1> MEGA_FETCH = 0;
2090 // bits<1> ALT_CONST = 0;
2091 // bits<2> BUFFER_INDEX_MODE = 0;
2095 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
2096 // is done in R600CodeEmitter
2098 // Inst{79-64} = OFFSET;
2099 // Inst{81-80} = ENDIAN_SWAP;
2100 // Inst{82} = CONST_BUF_NO_STRIDE;
2101 // Inst{83} = MEGA_FETCH;
2102 // Inst{84} = ALT_CONST;
2103 // Inst{86-85} = BUFFER_INDEX_MODE;
2104 // Inst{95-86} = 0; Reserved
2106 // VTX_WORD3 (Padding)
2108 // Inst{127-96} = 0;
2112 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr",
2113 [(set R600_Reg128:$dst, (int_R600_load_texbuf ADDRGA_VAR_OFFSET:$ptr, imm:$BUFFER_ID))]>,
2114 VTX_WORD1_GPR, VTX_WORD0 {
2118 let FETCH_WHOLE_QUAD = 0;
2122 let USE_CONST_FIELDS = 1;
2123 let NUM_FORMAT_ALL = 0;
2124 let FORMAT_COMP_ALL = 0;
2125 let SRF_MODE_ALL = 1;
2126 let MEGA_FETCH_COUNT = 16;
2131 let DATA_FORMAT = 0;
2133 let Inst{31-0} = Word0;
2134 let Inst{63-32} = Word1;
2136 // LLVM can only encode 64-bit instructions, so these fields are manually
2137 // encoded in R600CodeEmitter
2140 // bits<2> ENDIAN_SWAP = 0;
2141 // bits<1> CONST_BUF_NO_STRIDE = 0;
2142 // bits<1> MEGA_FETCH = 0;
2143 // bits<1> ALT_CONST = 0;
2144 // bits<2> BUFFER_INDEX_MODE = 0;
2148 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
2149 // is done in R600CodeEmitter
2151 // Inst{79-64} = OFFSET;
2152 // Inst{81-80} = ENDIAN_SWAP;
2153 // Inst{82} = CONST_BUF_NO_STRIDE;
2154 // Inst{83} = MEGA_FETCH;
2155 // Inst{84} = ALT_CONST;
2156 // Inst{86-85} = BUFFER_INDEX_MODE;
2157 // Inst{95-86} = 0; Reserved
2159 // VTX_WORD3 (Padding)
2161 // Inst{127-96} = 0;
2166 //===--------------------------------------------------------------------===//
2167 // Instructions support
2168 //===--------------------------------------------------------------------===//
2169 //===---------------------------------------------------------------------===//
2170 // Custom Inserter for Branches and returns, this eventually will be a
2172 //===---------------------------------------------------------------------===//
2173 let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in {
2174 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
2175 "; Pseudo unconditional branch instruction",
2177 defm BRANCH_COND : BranchConditional<IL_brcond>;
2180 //===---------------------------------------------------------------------===//
2181 // Flow and Program control Instructions
2182 //===---------------------------------------------------------------------===//
2183 let isTerminator=1 in {
2184 def SWITCH : ILFormat< (outs), (ins GPRI32:$src),
2185 !strconcat("SWITCH", " $src"), []>;
2186 def CASE : ILFormat< (outs), (ins GPRI32:$src),
2187 !strconcat("CASE", " $src"), []>;
2188 def BREAK : ILFormat< (outs), (ins),
2190 def CONTINUE : ILFormat< (outs), (ins),
2192 def DEFAULT : ILFormat< (outs), (ins),
2194 def ELSE : ILFormat< (outs), (ins),
2196 def ENDSWITCH : ILFormat< (outs), (ins),
2198 def ENDMAIN : ILFormat< (outs), (ins),
2200 def END : ILFormat< (outs), (ins),
2202 def ENDFUNC : ILFormat< (outs), (ins),
2204 def ENDIF : ILFormat< (outs), (ins),
2206 def WHILELOOP : ILFormat< (outs), (ins),
2208 def ENDLOOP : ILFormat< (outs), (ins),
2210 def FUNC : ILFormat< (outs), (ins),
2212 def RETDYN : ILFormat< (outs), (ins),
2214 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2215 defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">;
2216 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2217 defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">;
2218 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2219 defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">;
2220 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2221 defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">;
2222 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2223 defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">;
2224 // This opcode has custom swizzle pattern encoded in Swizzle Encoder
2225 defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">;
2226 defm IFC : BranchInstr2<"IFC">;
2227 defm BREAKC : BranchInstr2<"BREAKC">;
2228 defm CONTINUEC : BranchInstr2<"CONTINUEC">;
2231 //===----------------------------------------------------------------------===//
2233 //===----------------------------------------------------------------------===//
2235 // CND*_INT Pattterns for f32 True / False values
2237 class CND_INT_f32 <InstR600 cnd, CondCode cc> : Pat <
2238 (selectcc (i32 R600_Reg32:$src0), 0, (f32 R600_Reg32:$src1),
2239 R600_Reg32:$src2, cc),
2240 (cnd R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2)
2243 def : CND_INT_f32 <CNDE_INT, SETEQ>;
2244 def : CND_INT_f32 <CNDGT_INT, SETGT>;
2245 def : CND_INT_f32 <CNDGE_INT, SETGE>;
2247 //CNDGE_INT extra pattern
2249 (selectcc (i32 R600_Reg32:$src0), -1, (i32 R600_Reg32:$src1),
2250 (i32 R600_Reg32:$src2), COND_GT),
2251 (CNDGE_INT R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2)
2257 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
2261 (int_AMDGPU_kill R600_Reg32:$src0),
2262 (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0)))
2267 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LT),
2268 (SGT R600_Reg32:$src1, R600_Reg32:$src0)
2273 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LE),
2274 (SGE R600_Reg32:$src1, R600_Reg32:$src0)
2277 // SETGT_DX10 reverse args
2279 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, COND_LT),
2280 (SETGT_DX10 R600_Reg32:$src1, R600_Reg32:$src0)
2283 // SETGE_DX10 reverse args
2285 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, COND_LE),
2286 (SETGE_DX10 R600_Reg32:$src1, R600_Reg32:$src0)
2289 // SETGT_INT reverse args
2291 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT),
2292 (SETGT_INT R600_Reg32:$src1, R600_Reg32:$src0)
2295 // SETGE_INT reverse args
2297 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLE),
2298 (SETGE_INT R600_Reg32:$src1, R600_Reg32:$src0)
2301 // SETGT_UINT reverse args
2303 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULT),
2304 (SETGT_UINT R600_Reg32:$src1, R600_Reg32:$src0)
2307 // SETGE_UINT reverse args
2309 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULE),
2310 (SETGE_UINT R600_Reg32:$src1, R600_Reg32:$src0)
2313 // The next two patterns are special cases for handling 'true if ordered' and
2314 // 'true if unordered' conditionals. The assumption here is that the behavior of
2315 // SETE and SNE conforms to the Direct3D 10 rules for floating point values
2317 // http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx#alpha_32_bit
2318 // We assume that SETE returns false when one of the operands is NAN and
2319 // SNE returns true when on of the operands is NAN
2321 //SETE - 'true if ordered'
2323 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETO),
2324 (SETE R600_Reg32:$src0, R600_Reg32:$src1)
2327 //SETE_DX10 - 'true if ordered'
2329 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETO),
2330 (SETE_DX10 R600_Reg32:$src0, R600_Reg32:$src1)
2333 //SNE - 'true if unordered'
2335 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETUO),
2336 (SNE R600_Reg32:$src0, R600_Reg32:$src1)
2339 //SETNE_DX10 - 'true if ordered'
2341 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUO),
2342 (SETNE_DX10 R600_Reg32:$src0, R600_Reg32:$src1)
2345 def : Extract_Element <f32, v4f32, R600_Reg128, 0, sub0>;
2346 def : Extract_Element <f32, v4f32, R600_Reg128, 1, sub1>;
2347 def : Extract_Element <f32, v4f32, R600_Reg128, 2, sub2>;
2348 def : Extract_Element <f32, v4f32, R600_Reg128, 3, sub3>;
2350 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 0, sub0>;
2351 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 1, sub1>;
2352 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 2, sub2>;
2353 def : Insert_Element <f32, v4f32, R600_Reg32, R600_Reg128, 3, sub3>;
2355 def : Extract_Element <i32, v4i32, R600_Reg128, 0, sub0>;
2356 def : Extract_Element <i32, v4i32, R600_Reg128, 1, sub1>;
2357 def : Extract_Element <i32, v4i32, R600_Reg128, 2, sub2>;
2358 def : Extract_Element <i32, v4i32, R600_Reg128, 3, sub3>;
2360 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 0, sub0>;
2361 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 1, sub1>;
2362 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 2, sub2>;
2363 def : Insert_Element <i32, v4i32, R600_Reg32, R600_Reg128, 3, sub3>;
2365 def : Vector4_Build <v4f32, R600_Reg128, f32, R600_Reg32>;
2366 def : Vector4_Build <v4i32, R600_Reg128, i32, R600_Reg32>;
2368 // bitconvert patterns
2370 def : BitConvert <i32, f32, R600_Reg32>;
2371 def : BitConvert <f32, i32, R600_Reg32>;
2372 def : BitConvert <v4f32, v4i32, R600_Reg128>;
2373 def : BitConvert <v4i32, v4f32, R600_Reg128>;
2375 // DWORDADDR pattern
2376 def : DwordAddrPat <i32, R600_Reg32>;
2378 } // End isR600toCayman Predicate