1 //===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief R600 Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
15 #include "R600InstrInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "R600Defines.h"
20 #include "R600MachineFunctionInfo.h"
21 #include "R600RegisterInfo.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #define GET_INSTRINFO_CTOR
27 #include "AMDGPUGenDFAPacketizer.inc"
31 R600InstrInfo::R600InstrInfo(AMDGPUTargetMachine &tm)
32 : AMDGPUInstrInfo(tm),
34 ST(tm.getSubtarget<AMDGPUSubtarget>())
37 const R600RegisterInfo &R600InstrInfo::getRegisterInfo() const {
41 bool R600InstrInfo::isTrig(const MachineInstr &MI) const {
42 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
45 bool R600InstrInfo::isVector(const MachineInstr &MI) const {
46 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
50 R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
51 MachineBasicBlock::iterator MI, DebugLoc DL,
52 unsigned DestReg, unsigned SrcReg,
54 if (AMDGPU::R600_Reg128RegClass.contains(DestReg)
55 && AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
56 for (unsigned I = 0; I < 4; I++) {
57 unsigned SubRegIndex = RI.getSubRegFromChannel(I);
58 buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
59 RI.getSubReg(DestReg, SubRegIndex),
60 RI.getSubReg(SrcReg, SubRegIndex))
62 RegState::Define | RegState::Implicit);
66 // We can't copy vec4 registers
67 assert(!AMDGPU::R600_Reg128RegClass.contains(DestReg)
68 && !AMDGPU::R600_Reg128RegClass.contains(SrcReg));
70 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
72 NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0))
77 MachineInstr * R600InstrInfo::getMovImmInstr(MachineFunction *MF,
78 unsigned DstReg, int64_t Imm) const {
79 MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc());
80 MachineInstrBuilder MIB(*MF, MI);
81 MIB.addReg(DstReg, RegState::Define);
82 MIB.addReg(AMDGPU::ALU_LITERAL_X);
84 MIB.addReg(0); // PREDICATE_BIT
89 unsigned R600InstrInfo::getIEQOpcode() const {
90 return AMDGPU::SETE_INT;
93 bool R600InstrInfo::isMov(unsigned Opcode) const {
97 default: return false;
99 case AMDGPU::MOV_IMM_F32:
100 case AMDGPU::MOV_IMM_I32:
105 // Some instructions act as place holders to emulate operations that the GPU
106 // hardware does automatically. This function can be used to check if
107 // an opcode falls into this category.
108 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const {
110 default: return false;
116 bool R600InstrInfo::isReductionOp(unsigned Opcode) const {
118 default: return false;
122 bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
124 default: return false;
125 case AMDGPU::CUBE_r600_pseudo:
126 case AMDGPU::CUBE_r600_real:
127 case AMDGPU::CUBE_eg_pseudo:
128 case AMDGPU::CUBE_eg_real:
133 bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
134 unsigned TargetFlags = get(Opcode).TSFlags;
136 return (TargetFlags & R600_InstFlag::ALU_INST);
139 bool R600InstrInfo::hasInstrModifiers(unsigned Opcode) const {
140 unsigned TargetFlags = get(Opcode).TSFlags;
142 return ((TargetFlags & R600_InstFlag::OP1) |
143 (TargetFlags & R600_InstFlag::OP2) |
144 (TargetFlags & R600_InstFlag::OP3));
147 bool R600InstrInfo::isLDSInstr(unsigned Opcode) const {
148 unsigned TargetFlags = get(Opcode).TSFlags;
150 return ((TargetFlags & R600_InstFlag::LDS_1A) |
151 (TargetFlags & R600_InstFlag::LDS_1A1D));
154 bool R600InstrInfo::isTransOnly(unsigned Opcode) const {
155 return (get(Opcode).TSFlags & R600_InstFlag::TRANS_ONLY);
158 bool R600InstrInfo::isTransOnly(const MachineInstr *MI) const {
159 return isTransOnly(MI->getOpcode());
162 bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {
163 return ST.hasVertexCache() && IS_VTX(get(Opcode));
166 bool R600InstrInfo::usesVertexCache(const MachineInstr *MI) const {
167 const R600MachineFunctionInfo *MFI = MI->getParent()->getParent()->getInfo<R600MachineFunctionInfo>();
168 return MFI->ShaderType != ShaderType::COMPUTE && usesVertexCache(MI->getOpcode());
171 bool R600InstrInfo::usesTextureCache(unsigned Opcode) const {
172 return (!ST.hasVertexCache() && IS_VTX(get(Opcode))) || IS_TEX(get(Opcode));
175 bool R600InstrInfo::usesTextureCache(const MachineInstr *MI) const {
176 const R600MachineFunctionInfo *MFI = MI->getParent()->getParent()->getInfo<R600MachineFunctionInfo>();
177 return (MFI->ShaderType == ShaderType::COMPUTE && usesVertexCache(MI->getOpcode())) ||
178 usesTextureCache(MI->getOpcode());
181 bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const {
184 case AMDGPU::GROUP_BARRIER:
191 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
192 R600InstrInfo::getSrcs(MachineInstr *MI) const {
193 SmallVector<std::pair<MachineOperand *, int64_t>, 3> Result;
195 if (MI->getOpcode() == AMDGPU::DOT_4) {
196 static const unsigned OpTable[8][2] = {
197 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
198 {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
199 {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
200 {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
201 {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
202 {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
203 {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
204 {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W},
207 for (unsigned j = 0; j < 8; j++) {
208 MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
210 unsigned Reg = MO.getReg();
211 if (Reg == AMDGPU::ALU_CONST) {
212 unsigned Sel = MI->getOperand(getOperandIdx(MI->getOpcode(),
213 OpTable[j][1])).getImm();
214 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Sel));
222 static const unsigned OpTable[3][2] = {
223 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
224 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
225 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
228 for (unsigned j = 0; j < 3; j++) {
229 int SrcIdx = getOperandIdx(MI->getOpcode(), OpTable[j][0]);
232 MachineOperand &MO = MI->getOperand(SrcIdx);
233 unsigned Reg = MI->getOperand(SrcIdx).getReg();
234 if (Reg == AMDGPU::ALU_CONST) {
235 unsigned Sel = MI->getOperand(
236 getOperandIdx(MI->getOpcode(), OpTable[j][1])).getImm();
237 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Sel));
240 if (Reg == AMDGPU::ALU_LITERAL_X) {
241 unsigned Imm = MI->getOperand(
242 getOperandIdx(MI->getOpcode(), AMDGPU::OpName::literal)).getImm();
243 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, Imm));
246 Result.push_back(std::pair<MachineOperand *, int64_t>(&MO, 0));
251 std::vector<std::pair<int, unsigned> >
252 R600InstrInfo::ExtractSrcs(MachineInstr *MI,
253 const DenseMap<unsigned, unsigned> &PV)
255 const SmallVector<std::pair<MachineOperand *, int64_t>, 3> Srcs = getSrcs(MI);
256 const std::pair<int, unsigned> DummyPair(-1, 0);
257 std::vector<std::pair<int, unsigned> > Result;
259 for (unsigned n = Srcs.size(); i < n; ++i) {
260 unsigned Reg = Srcs[i].first->getReg();
261 unsigned Index = RI.getEncodingValue(Reg) & 0xff;
262 unsigned Chan = RI.getHWRegChan(Reg);
263 if (Reg == AMDGPU::OQAP) {
264 Result.push_back(std::pair<int, unsigned>(Index, 0));
267 Result.push_back(DummyPair);
270 if (PV.find(Reg) != PV.end()) {
271 Result.push_back(DummyPair);
274 Result.push_back(std::pair<int, unsigned>(Index, Chan));
277 Result.push_back(DummyPair);
281 static std::vector<std::pair<int, unsigned> >
282 Swizzle(std::vector<std::pair<int, unsigned> > Src,
283 R600InstrInfo::BankSwizzle Swz) {
285 case R600InstrInfo::ALU_VEC_012_SCL_210:
287 case R600InstrInfo::ALU_VEC_021_SCL_122:
288 std::swap(Src[1], Src[2]);
290 case R600InstrInfo::ALU_VEC_102_SCL_221:
291 std::swap(Src[0], Src[1]);
293 case R600InstrInfo::ALU_VEC_120_SCL_212:
294 std::swap(Src[0], Src[1]);
295 std::swap(Src[0], Src[2]);
297 case R600InstrInfo::ALU_VEC_201:
298 std::swap(Src[0], Src[2]);
299 std::swap(Src[0], Src[1]);
301 case R600InstrInfo::ALU_VEC_210:
302 std::swap(Src[0], Src[2]);
309 R600InstrInfo::isLegal(
310 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
311 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
312 unsigned CheckedSize) const {
314 memset(Vector, -1, sizeof(Vector));
315 for (unsigned i = 0; i < CheckedSize; i++) {
316 const std::vector<std::pair<int, unsigned> > &Srcs =
317 Swizzle(IGSrcs[i], Swz[i]);
318 for (unsigned j = 0; j < 3; j++) {
319 const std::pair<int, unsigned> &Src = Srcs[j];
322 if (Src.first == GET_REG_INDEX(RI.getEncodingValue(AMDGPU::OQAP))) {
323 if (Swz[i] != R600InstrInfo::ALU_VEC_012 &&
324 Swz[i] != R600InstrInfo::ALU_VEC_021) {
325 // The value from output queue A (denoted by register OQAP) can
326 // only be fetched during the first cycle.
329 // OQAP does not count towards the normal read port restrictions
332 if (Vector[Src.second][j] < 0)
333 Vector[Src.second][j] = Src.first;
334 if (Vector[Src.second][j] != Src.first)
342 R600InstrInfo::recursiveFitsFPLimitation(
343 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
344 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
345 unsigned Depth) const {
346 if (!isLegal(IGSrcs, SwzCandidate, Depth))
348 if (IGSrcs.size() == Depth)
350 unsigned i = SwzCandidate[Depth];
352 SwzCandidate[Depth] = (R600InstrInfo::BankSwizzle) i;
353 if (recursiveFitsFPLimitation(IGSrcs, SwzCandidate, Depth + 1))
356 SwzCandidate[Depth] = R600InstrInfo::ALU_VEC_012;
361 R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG,
362 const DenseMap<unsigned, unsigned> &PV,
363 std::vector<BankSwizzle> &ValidSwizzle)
365 //Todo : support shared src0 - src1 operand
367 std::vector<std::vector<std::pair<int, unsigned> > > IGSrcs;
368 ValidSwizzle.clear();
369 for (unsigned i = 0, e = IG.size(); i < e; ++i) {
370 IGSrcs.push_back(ExtractSrcs(IG[i], PV));
371 unsigned Op = getOperandIdx(IG[i]->getOpcode(),
372 AMDGPU::OpName::bank_swizzle);
373 ValidSwizzle.push_back( (R600InstrInfo::BankSwizzle)
374 IG[i]->getOperand(Op).getImm());
376 bool Result = recursiveFitsFPLimitation(IGSrcs, ValidSwizzle);
384 R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts)
386 assert (Consts.size() <= 12 && "Too many operands in instructions group");
387 unsigned Pair1 = 0, Pair2 = 0;
388 for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
389 unsigned ReadConstHalf = Consts[i] & 2;
390 unsigned ReadConstIndex = Consts[i] & (~3);
391 unsigned ReadHalfConst = ReadConstIndex | ReadConstHalf;
393 Pair1 = ReadHalfConst;
396 if (Pair1 == ReadHalfConst)
399 Pair2 = ReadHalfConst;
402 if (Pair2 != ReadHalfConst)
409 R600InstrInfo::canBundle(const std::vector<MachineInstr *> &MIs) const {
410 std::vector<unsigned> Consts;
411 for (unsigned i = 0, n = MIs.size(); i < n; i++) {
412 MachineInstr *MI = MIs[i];
413 if (!isALUInstr(MI->getOpcode()))
416 const SmallVector<std::pair<MachineOperand *, int64_t>, 3> &Srcs =
419 for (unsigned j = 0, e = Srcs.size(); j < e; j++) {
420 std::pair<MachineOperand *, unsigned> Src = Srcs[j];
421 if (Src.first->getReg() == AMDGPU::ALU_CONST)
422 Consts.push_back(Src.second);
423 if (AMDGPU::R600_KC0RegClass.contains(Src.first->getReg()) ||
424 AMDGPU::R600_KC1RegClass.contains(Src.first->getReg())) {
425 unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff;
426 unsigned Chan = RI.getHWRegChan(Src.first->getReg());
427 Consts.push_back((Index << 2) | Chan);
431 return fitsConstReadLimitations(Consts);
434 DFAPacketizer *R600InstrInfo::CreateTargetScheduleState(const TargetMachine *TM,
435 const ScheduleDAG *DAG) const {
436 const InstrItineraryData *II = TM->getInstrItineraryData();
437 return TM->getSubtarget<AMDGPUSubtarget>().createDFAPacketizer(II);
441 isPredicateSetter(unsigned Opcode) {
450 static MachineInstr *
451 findFirstPredicateSetterFrom(MachineBasicBlock &MBB,
452 MachineBasicBlock::iterator I) {
453 while (I != MBB.begin()) {
455 MachineInstr *MI = I;
456 if (isPredicateSetter(MI->getOpcode()))
464 bool isJump(unsigned Opcode) {
465 return Opcode == AMDGPU::JUMP || Opcode == AMDGPU::JUMP_COND;
469 R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
470 MachineBasicBlock *&TBB,
471 MachineBasicBlock *&FBB,
472 SmallVectorImpl<MachineOperand> &Cond,
473 bool AllowModify) const {
474 // Most of the following comes from the ARM implementation of AnalyzeBranch
476 // If the block has no terminators, it just falls into the block after it.
477 MachineBasicBlock::iterator I = MBB.end();
478 if (I == MBB.begin())
481 while (I->isDebugValue()) {
482 if (I == MBB.begin())
486 if (!isJump(static_cast<MachineInstr *>(I)->getOpcode())) {
490 // Get the last instruction in the block.
491 MachineInstr *LastInst = I;
493 // If there is only one terminator instruction, process it.
494 unsigned LastOpc = LastInst->getOpcode();
495 if (I == MBB.begin() ||
496 !isJump(static_cast<MachineInstr *>(--I)->getOpcode())) {
497 if (LastOpc == AMDGPU::JUMP) {
498 TBB = LastInst->getOperand(0).getMBB();
500 } else if (LastOpc == AMDGPU::JUMP_COND) {
501 MachineInstr *predSet = I;
502 while (!isPredicateSetter(predSet->getOpcode())) {
505 TBB = LastInst->getOperand(0).getMBB();
506 Cond.push_back(predSet->getOperand(1));
507 Cond.push_back(predSet->getOperand(2));
508 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
511 return true; // Can't handle indirect branch.
514 // Get the instruction before it if it is a terminator.
515 MachineInstr *SecondLastInst = I;
516 unsigned SecondLastOpc = SecondLastInst->getOpcode();
518 // If the block ends with a B and a Bcc, handle it.
519 if (SecondLastOpc == AMDGPU::JUMP_COND && LastOpc == AMDGPU::JUMP) {
520 MachineInstr *predSet = --I;
521 while (!isPredicateSetter(predSet->getOpcode())) {
524 TBB = SecondLastInst->getOperand(0).getMBB();
525 FBB = LastInst->getOperand(0).getMBB();
526 Cond.push_back(predSet->getOperand(1));
527 Cond.push_back(predSet->getOperand(2));
528 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
532 // Otherwise, can't handle this.
536 int R600InstrInfo::getBranchInstr(const MachineOperand &op) const {
537 const MachineInstr *MI = op.getParent();
539 switch (MI->getDesc().OpInfo->RegClass) {
540 default: // FIXME: fallthrough??
541 case AMDGPU::GPRI32RegClassID: return AMDGPU::BRANCH_COND_i32;
542 case AMDGPU::GPRF32RegClassID: return AMDGPU::BRANCH_COND_f32;
547 R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
548 MachineBasicBlock *TBB,
549 MachineBasicBlock *FBB,
550 const SmallVectorImpl<MachineOperand> &Cond,
552 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
556 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB);
559 MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
560 assert(PredSet && "No previous predicate !");
561 addFlag(PredSet, 0, MO_FLAG_PUSH);
562 PredSet->getOperand(2).setImm(Cond[1].getImm());
564 BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
566 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
570 MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
571 assert(PredSet && "No previous predicate !");
572 addFlag(PredSet, 0, MO_FLAG_PUSH);
573 PredSet->getOperand(2).setImm(Cond[1].getImm());
574 BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
576 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
577 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB);
583 R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
585 // Note : we leave PRED* instructions there.
586 // They may be needed when predicating instructions.
588 MachineBasicBlock::iterator I = MBB.end();
590 if (I == MBB.begin()) {
594 switch (I->getOpcode()) {
597 case AMDGPU::JUMP_COND: {
598 MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
599 clearFlag(predSet, 0, MO_FLAG_PUSH);
600 I->eraseFromParent();
604 I->eraseFromParent();
609 if (I == MBB.begin()) {
613 switch (I->getOpcode()) {
614 // FIXME: only one case??
617 case AMDGPU::JUMP_COND: {
618 MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
619 clearFlag(predSet, 0, MO_FLAG_PUSH);
620 I->eraseFromParent();
624 I->eraseFromParent();
631 R600InstrInfo::isPredicated(const MachineInstr *MI) const {
632 int idx = MI->findFirstPredOperandIdx();
636 unsigned Reg = MI->getOperand(idx).getReg();
638 default: return false;
639 case AMDGPU::PRED_SEL_ONE:
640 case AMDGPU::PRED_SEL_ZERO:
641 case AMDGPU::PREDICATE_BIT:
647 R600InstrInfo::isPredicable(MachineInstr *MI) const {
648 // XXX: KILL* instructions can be predicated, but they must be the last
649 // instruction in a clause, so this means any instructions after them cannot
650 // be predicated. Until we have proper support for instruction clauses in the
651 // backend, we will mark KILL* instructions as unpredicable.
653 if (MI->getOpcode() == AMDGPU::KILLGT) {
655 } else if (isVector(*MI)) {
658 return AMDGPUInstrInfo::isPredicable(MI);
664 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
666 unsigned ExtraPredCycles,
667 const BranchProbability &Probability) const{
672 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
674 unsigned ExtraTCycles,
675 MachineBasicBlock &FMBB,
677 unsigned ExtraFCycles,
678 const BranchProbability &Probability) const {
683 R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
685 const BranchProbability &Probability)
691 R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
692 MachineBasicBlock &FMBB) const {
698 R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
699 MachineOperand &MO = Cond[1];
700 switch (MO.getImm()) {
701 case OPCODE_IS_ZERO_INT:
702 MO.setImm(OPCODE_IS_NOT_ZERO_INT);
704 case OPCODE_IS_NOT_ZERO_INT:
705 MO.setImm(OPCODE_IS_ZERO_INT);
708 MO.setImm(OPCODE_IS_NOT_ZERO);
710 case OPCODE_IS_NOT_ZERO:
711 MO.setImm(OPCODE_IS_ZERO);
717 MachineOperand &MO2 = Cond[2];
718 switch (MO2.getReg()) {
719 case AMDGPU::PRED_SEL_ZERO:
720 MO2.setReg(AMDGPU::PRED_SEL_ONE);
722 case AMDGPU::PRED_SEL_ONE:
723 MO2.setReg(AMDGPU::PRED_SEL_ZERO);
732 R600InstrInfo::DefinesPredicate(MachineInstr *MI,
733 std::vector<MachineOperand> &Pred) const {
734 return isPredicateSetter(MI->getOpcode());
739 R600InstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
740 const SmallVectorImpl<MachineOperand> &Pred2) const {
746 R600InstrInfo::PredicateInstruction(MachineInstr *MI,
747 const SmallVectorImpl<MachineOperand> &Pred) const {
748 int PIdx = MI->findFirstPredOperandIdx();
751 MachineOperand &PMO = MI->getOperand(PIdx);
752 PMO.setReg(Pred[2].getReg());
753 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
754 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
761 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
762 const MachineInstr *MI,
763 unsigned *PredCost) const {
769 int R600InstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
770 const MachineRegisterInfo &MRI = MF.getRegInfo();
771 const MachineFrameInfo *MFI = MF.getFrameInfo();
774 if (MFI->getNumObjects() == 0) {
778 if (MRI.livein_empty()) {
782 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
783 LE = MRI.livein_end();
785 Offset = std::max(Offset,
786 GET_REG_INDEX(RI.getEncodingValue(LI->first)));
792 int R600InstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
794 const MachineFrameInfo *MFI = MF.getFrameInfo();
796 // Variable sized objects are not supported
797 assert(!MFI->hasVarSizedObjects());
799 if (MFI->getNumObjects() == 0) {
803 Offset = TM.getFrameLowering()->getFrameIndexOffset(MF, -1);
805 return getIndirectIndexBegin(MF) + Offset;
808 std::vector<unsigned> R600InstrInfo::getIndirectReservedRegs(
809 const MachineFunction &MF) const {
810 const AMDGPUFrameLowering *TFL =
811 static_cast<const AMDGPUFrameLowering*>(TM.getFrameLowering());
812 std::vector<unsigned> Regs;
814 unsigned StackWidth = TFL->getStackWidth(MF);
815 int End = getIndirectIndexEnd(MF);
821 for (int Index = getIndirectIndexBegin(MF); Index <= End; ++Index) {
822 unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
823 Regs.push_back(SuperReg);
824 for (unsigned Chan = 0; Chan < StackWidth; ++Chan) {
825 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
832 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex,
833 unsigned Channel) const {
834 // XXX: Remove when we support a stack width > 2
835 assert(Channel == 0);
839 const TargetRegisterClass * R600InstrInfo::getIndirectAddrStoreRegClass(
840 unsigned SourceReg) const {
841 return &AMDGPU::R600_TReg32RegClass;
844 const TargetRegisterClass *R600InstrInfo::getIndirectAddrLoadRegClass() const {
845 return &AMDGPU::TRegMemRegClass;
848 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
849 MachineBasicBlock::iterator I,
850 unsigned ValueReg, unsigned Address,
851 unsigned OffsetReg) const {
852 unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
853 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
854 AMDGPU::AR_X, OffsetReg);
855 setImmOperand(MOVA, AMDGPU::OpName::write, 0);
857 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
859 .addReg(AMDGPU::AR_X,
860 RegState::Implicit | RegState::Kill);
861 setImmOperand(Mov, AMDGPU::OpName::dst_rel, 1);
865 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
866 MachineBasicBlock::iterator I,
867 unsigned ValueReg, unsigned Address,
868 unsigned OffsetReg) const {
869 unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
870 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
873 setImmOperand(MOVA, AMDGPU::OpName::write, 0);
874 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
877 .addReg(AMDGPU::AR_X,
878 RegState::Implicit | RegState::Kill);
879 setImmOperand(Mov, AMDGPU::OpName::src0_rel, 1);
884 const TargetRegisterClass *R600InstrInfo::getSuperIndirectRegClass() const {
885 return &AMDGPU::IndirectRegRegClass;
888 unsigned R600InstrInfo::getMaxAlusPerClause() const {
892 MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB,
893 MachineBasicBlock::iterator I,
897 unsigned Src1Reg) const {
898 MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
902 MIB.addImm(0) // $update_exec_mask
903 .addImm(0); // $update_predicate
905 MIB.addImm(1) // $write
907 .addImm(0) // $dst_rel
908 .addImm(0) // $dst_clamp
909 .addReg(Src0Reg) // $src0
910 .addImm(0) // $src0_neg
911 .addImm(0) // $src0_rel
912 .addImm(0) // $src0_abs
913 .addImm(-1); // $src0_sel
916 MIB.addReg(Src1Reg) // $src1
917 .addImm(0) // $src1_neg
918 .addImm(0) // $src1_rel
919 .addImm(0) // $src1_abs
920 .addImm(-1); // $src1_sel
923 //XXX: The r600g finalizer expects this to be 1, once we've moved the
924 //scheduling to the backend, we can change the default to 0.
925 MIB.addImm(1) // $last
926 .addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel
927 .addImm(0) // $literal
928 .addImm(0); // $bank_swizzle
933 #define OPERAND_CASE(Label) \
935 static const unsigned Ops[] = \
945 static unsigned getSlotedOps(unsigned Op, unsigned Slot) {
947 OPERAND_CASE(AMDGPU::OpName::update_exec_mask)
948 OPERAND_CASE(AMDGPU::OpName::update_pred)
949 OPERAND_CASE(AMDGPU::OpName::write)
950 OPERAND_CASE(AMDGPU::OpName::omod)
951 OPERAND_CASE(AMDGPU::OpName::dst_rel)
952 OPERAND_CASE(AMDGPU::OpName::clamp)
953 OPERAND_CASE(AMDGPU::OpName::src0)
954 OPERAND_CASE(AMDGPU::OpName::src0_neg)
955 OPERAND_CASE(AMDGPU::OpName::src0_rel)
956 OPERAND_CASE(AMDGPU::OpName::src0_abs)
957 OPERAND_CASE(AMDGPU::OpName::src0_sel)
958 OPERAND_CASE(AMDGPU::OpName::src1)
959 OPERAND_CASE(AMDGPU::OpName::src1_neg)
960 OPERAND_CASE(AMDGPU::OpName::src1_rel)
961 OPERAND_CASE(AMDGPU::OpName::src1_abs)
962 OPERAND_CASE(AMDGPU::OpName::src1_sel)
963 OPERAND_CASE(AMDGPU::OpName::pred_sel)
965 llvm_unreachable("Wrong Operand");
971 MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction(
972 MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg)
974 assert (MI->getOpcode() == AMDGPU::DOT_4 && "Not Implemented");
976 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
977 if (ST.getGeneration() <= AMDGPUSubtarget::R700)
978 Opcode = AMDGPU::DOT4_r600;
980 Opcode = AMDGPU::DOT4_eg;
981 MachineBasicBlock::iterator I = MI;
982 MachineOperand &Src0 = MI->getOperand(
983 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src0, Slot)));
984 MachineOperand &Src1 = MI->getOperand(
985 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src1, Slot)));
986 MachineInstr *MIB = buildDefaultInstruction(
987 MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
988 static const unsigned Operands[14] = {
989 AMDGPU::OpName::update_exec_mask,
990 AMDGPU::OpName::update_pred,
991 AMDGPU::OpName::write,
992 AMDGPU::OpName::omod,
993 AMDGPU::OpName::dst_rel,
994 AMDGPU::OpName::clamp,
995 AMDGPU::OpName::src0_neg,
996 AMDGPU::OpName::src0_rel,
997 AMDGPU::OpName::src0_abs,
998 AMDGPU::OpName::src0_sel,
999 AMDGPU::OpName::src1_neg,
1000 AMDGPU::OpName::src1_rel,
1001 AMDGPU::OpName::src1_abs,
1002 AMDGPU::OpName::src1_sel,
1005 for (unsigned i = 0; i < 14; i++) {
1006 MachineOperand &MO = MI->getOperand(
1007 getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));
1008 assert (MO.isImm());
1009 setImmOperand(MIB, Operands[i], MO.getImm());
1011 MIB->getOperand(20).setImm(0);
1015 MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB,
1016 MachineBasicBlock::iterator I,
1018 uint64_t Imm) const {
1019 MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg,
1020 AMDGPU::ALU_LITERAL_X);
1021 setImmOperand(MovImm, AMDGPU::OpName::literal, Imm);
1025 int R600InstrInfo::getOperandIdx(const MachineInstr &MI, unsigned Op) const {
1026 return getOperandIdx(MI.getOpcode(), Op);
1029 int R600InstrInfo::getOperandIdx(unsigned Opcode, unsigned Op) const {
1030 return AMDGPU::getNamedOperandIdx(Opcode, Op);
1033 void R600InstrInfo::setImmOperand(MachineInstr *MI, unsigned Op,
1034 int64_t Imm) const {
1035 int Idx = getOperandIdx(*MI, Op);
1036 assert(Idx != -1 && "Operand not supported for this instruction.");
1037 assert(MI->getOperand(Idx).isImm());
1038 MI->getOperand(Idx).setImm(Imm);
1041 //===----------------------------------------------------------------------===//
1042 // Instruction flag getters/setters
1043 //===----------------------------------------------------------------------===//
1045 bool R600InstrInfo::hasFlagOperand(const MachineInstr &MI) const {
1046 return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
1049 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr *MI, unsigned SrcIdx,
1050 unsigned Flag) const {
1051 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1054 // If we pass something other than the default value of Flag to this
1055 // function, it means we are want to set a flag on an instruction
1056 // that uses native encoding.
1057 assert(HAS_NATIVE_OPERANDS(TargetFlags));
1058 bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3;
1061 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::clamp);
1064 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::write);
1066 case MO_FLAG_NOT_LAST:
1068 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::last);
1072 case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_neg); break;
1073 case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_neg); break;
1074 case 2: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src2_neg); break;
1079 assert(!IsOP3 && "Cannot set absolute value modifier for OP3 "
1083 case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_abs); break;
1084 case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_abs); break;
1092 assert(FlagIndex != -1 && "Flag not supported for this instruction");
1094 FlagIndex = GET_FLAG_OPERAND_IDX(TargetFlags);
1095 assert(FlagIndex != 0 &&
1096 "Instruction flags not supported for this instruction");
1099 MachineOperand &FlagOp = MI->getOperand(FlagIndex);
1100 assert(FlagOp.isImm());
1104 void R600InstrInfo::addFlag(MachineInstr *MI, unsigned Operand,
1105 unsigned Flag) const {
1106 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1110 if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1111 MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1112 if (Flag == MO_FLAG_NOT_LAST) {
1113 clearFlag(MI, Operand, MO_FLAG_LAST);
1114 } else if (Flag == MO_FLAG_MASK) {
1115 clearFlag(MI, Operand, Flag);
1120 MachineOperand &FlagOp = getFlagOp(MI, Operand);
1121 FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand)));
1125 void R600InstrInfo::clearFlag(MachineInstr *MI, unsigned Operand,
1126 unsigned Flag) const {
1127 unsigned TargetFlags = get(MI->getOpcode()).TSFlags;
1128 if (HAS_NATIVE_OPERANDS(TargetFlags)) {
1129 MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1132 MachineOperand &FlagOp = getFlagOp(MI);
1133 unsigned InstFlags = FlagOp.getImm();
1134 InstFlags &= ~(Flag << (NUM_MO_FLAGS * Operand));
1135 FlagOp.setImm(InstFlags);