1 //===-- R600InstrFormats.td - R600 Instruction Encodings ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // R600 Instruction format definitions.
12 //===----------------------------------------------------------------------===//
14 class InstR600 <dag outs, dag ins, string asm, list<dag> pattern,
16 : AMDGPUInst <outs, ins, asm, pattern> {
23 bits<2> FlagOperandIdx = 0;
28 bit HasNativeOperands = 0;
35 let Namespace = "AMDGPU";
36 let OutOperandList = outs;
37 let InOperandList = ins;
39 let Pattern = pattern;
42 let TSFlags{0} = TransOnly;
43 let TSFlags{4} = Trig;
46 // Vector instructions are instructions that must fill all slots in an
48 let TSFlags{6} = isVector;
49 let TSFlags{8-7} = FlagOperandIdx;
50 let TSFlags{9} = HasNativeOperands;
51 let TSFlags{10} = Op1;
52 let TSFlags{11} = Op2;
53 let TSFlags{12} = VTXInst;
54 let TSFlags{13} = TEXInst;
55 let TSFlags{14} = ALUInst;
56 let TSFlags{15} = LDS_1A;
57 let TSFlags{16} = LDS_1A1D;
58 let TSFlags{17} = IsExport;
59 let TSFlags{18} = LDS_1A2D;
62 //===----------------------------------------------------------------------===//
64 //===----------------------------------------------------------------------===//
66 class R600_ALU_LDS_Word0 {
73 bits<3> index_mode = 0;
77 bits<9> src0_sel = src0{8-0};
78 bits<2> src0_chan = src0{10-9};
79 bits<9> src1_sel = src1{8-0};
80 bits<2> src1_chan = src1{10-9};
82 let Word0{8-0} = src0_sel;
83 let Word0{9} = src0_rel;
84 let Word0{11-10} = src0_chan;
85 let Word0{21-13} = src1_sel;
86 let Word0{22} = src1_rel;
87 let Word0{24-23} = src1_chan;
88 let Word0{28-26} = index_mode;
89 let Word0{30-29} = pred_sel;
93 class R600ALU_Word0 : R600_ALU_LDS_Word0 {
98 let Word0{12} = src0_neg;
99 let Word0{25} = src1_neg;
102 class R600ALU_Word1 {
103 field bits<32> Word1;
106 bits<3> bank_swizzle;
110 bits<7> dst_sel = dst{6-0};
111 bits<2> dst_chan = dst{10-9};
113 let Word1{20-18} = bank_swizzle;
114 let Word1{27-21} = dst_sel;
115 let Word1{28} = dst_rel;
116 let Word1{30-29} = dst_chan;
117 let Word1{31} = clamp;
120 class R600ALU_Word1_OP2 <bits<11> alu_inst> : R600ALU_Word1{
124 bits<1> update_exec_mask;
129 let Word1{0} = src0_abs;
130 let Word1{1} = src1_abs;
131 let Word1{2} = update_exec_mask;
132 let Word1{3} = update_pred;
133 let Word1{4} = write;
134 let Word1{6-5} = omod;
135 let Word1{17-7} = alu_inst;
138 class R600ALU_Word1_OP3 <bits<5> alu_inst> : R600ALU_Word1{
144 bits<9> src2_sel = src2{8-0};
145 bits<2> src2_chan = src2{10-9};
147 let Word1{8-0} = src2_sel;
148 let Word1{9} = src2_rel;
149 let Word1{11-10} = src2_chan;
150 let Word1{12} = src2_neg;
151 let Word1{17-13} = alu_inst;
154 class R600LDS_Word1 {
155 field bits<32> Word1;
158 bits<9> src2_sel = src2{8-0};
159 bits<2> src2_chan = src2{10-9};
161 // offset specifies the stride offset to the second set of data to be read
162 // from. This is a dword offset.
163 bits<5> alu_inst = 17; // OP3_INST_LDS_IDX_OP
164 bits<3> bank_swizzle;
166 bits<2> dst_chan = 0;
168 let Word1{8-0} = src2_sel;
169 let Word1{9} = src2_rel;
170 let Word1{11-10} = src2_chan;
171 let Word1{17-13} = alu_inst;
172 let Word1{20-18} = bank_swizzle;
173 let Word1{26-21} = lds_op;
174 let Word1{30-29} = dst_chan;
179 XXX: R600 subtarget uses a slightly different encoding than the other
180 subtargets. We currently handle this in R600MCCodeEmitter, but we may
181 want to use these instruction classes in the future.
183 class R600ALU_Word1_OP2_r600 : R600ALU_Word1_OP2 {
188 let Inst{37} = fog_merge;
189 let Inst{39-38} = omod;
190 let Inst{49-40} = alu_inst;
193 class R600ALU_Word1_OP2_r700 : R600ALU_Word1_OP2 {
197 let Inst{38-37} = omod;
198 let Inst{49-39} = alu_inst;
202 //===----------------------------------------------------------------------===//
203 // Vertex Fetch instructions
204 //===----------------------------------------------------------------------===//
207 field bits<32> Word0;
211 bits<1> FETCH_WHOLE_QUAD;
216 let Word0{4-0} = VC_INST;
217 let Word0{6-5} = FETCH_TYPE;
218 let Word0{7} = FETCH_WHOLE_QUAD;
219 let Word0{15-8} = BUFFER_ID;
220 let Word0{22-16} = src_gpr;
221 let Word0{23} = SRC_REL;
222 let Word0{25-24} = SRC_SEL_X;
225 class VTX_WORD0_eg : VTX_WORD0 {
227 bits<6> MEGA_FETCH_COUNT;
229 let Word0{31-26} = MEGA_FETCH_COUNT;
232 class VTX_WORD0_cm : VTX_WORD0 {
235 bits<2> STRUCTURED_READ;
237 bits<1> COALESCED_READ;
239 let Word0{27-26} = SRC_SEL_Y;
240 let Word0{29-28} = STRUCTURED_READ;
241 let Word0{30} = LDS_REQ;
242 let Word0{31} = COALESCED_READ;
245 class VTX_WORD1_GPR {
246 field bits<32> Word1;
253 bits<1> USE_CONST_FIELDS;
255 bits<2> NUM_FORMAT_ALL;
256 bits<1> FORMAT_COMP_ALL;
257 bits<1> SRF_MODE_ALL;
259 let Word1{6-0} = dst_gpr;
260 let Word1{7} = DST_REL;
261 let Word1{8} = 0; // Reserved
262 let Word1{11-9} = DST_SEL_X;
263 let Word1{14-12} = DST_SEL_Y;
264 let Word1{17-15} = DST_SEL_Z;
265 let Word1{20-18} = DST_SEL_W;
266 let Word1{21} = USE_CONST_FIELDS;
267 let Word1{27-22} = DATA_FORMAT;
268 let Word1{29-28} = NUM_FORMAT_ALL;
269 let Word1{30} = FORMAT_COMP_ALL;
270 let Word1{31} = SRF_MODE_ALL;
273 //===----------------------------------------------------------------------===//
274 // Texture fetch instructions
275 //===----------------------------------------------------------------------===//
278 field bits<32> Word0;
282 bits<1> FETCH_WHOLE_QUAD;
287 bits<2> RESOURCE_INDEX_MODE;
288 bits<2> SAMPLER_INDEX_MODE;
290 let Word0{4-0} = TEX_INST;
291 let Word0{6-5} = INST_MOD;
292 let Word0{7} = FETCH_WHOLE_QUAD;
293 let Word0{15-8} = RESOURCE_ID;
294 let Word0{22-16} = SRC_GPR;
295 let Word0{23} = SRC_REL;
296 let Word0{24} = ALT_CONST;
297 let Word0{26-25} = RESOURCE_INDEX_MODE;
298 let Word0{28-27} = SAMPLER_INDEX_MODE;
302 field bits<32> Word1;
311 bits<1> COORD_TYPE_X;
312 bits<1> COORD_TYPE_Y;
313 bits<1> COORD_TYPE_Z;
314 bits<1> COORD_TYPE_W;
316 let Word1{6-0} = DST_GPR;
317 let Word1{7} = DST_REL;
318 let Word1{11-9} = DST_SEL_X;
319 let Word1{14-12} = DST_SEL_Y;
320 let Word1{17-15} = DST_SEL_Z;
321 let Word1{20-18} = DST_SEL_W;
322 let Word1{27-21} = LOD_BIAS;
323 let Word1{28} = COORD_TYPE_X;
324 let Word1{29} = COORD_TYPE_Y;
325 let Word1{30} = COORD_TYPE_Z;
326 let Word1{31} = COORD_TYPE_W;
330 field bits<32> Word2;
341 let Word2{4-0} = OFFSET_X;
342 let Word2{9-5} = OFFSET_Y;
343 let Word2{14-10} = OFFSET_Z;
344 let Word2{19-15} = SAMPLER_ID;
345 let Word2{22-20} = SRC_SEL_X;
346 let Word2{25-23} = SRC_SEL_Y;
347 let Word2{28-26} = SRC_SEL_Z;
348 let Word2{31-29} = SRC_SEL_W;
351 //===----------------------------------------------------------------------===//
352 // Control Flow Instructions
353 //===----------------------------------------------------------------------===//
355 class CF_WORD1_R600 {
356 field bits<32> Word1;
364 bits<1> END_OF_PROGRAM;
365 bits<1> VALID_PIXEL_MODE;
367 bits<1> WHOLE_QUAD_MODE;
370 let Word1{2-0} = POP_COUNT;
371 let Word1{7-3} = CF_CONST;
372 let Word1{9-8} = COND;
373 let Word1{12-10} = COUNT;
374 let Word1{18-13} = CALL_COUNT;
375 let Word1{19} = COUNT_3;
376 let Word1{21} = END_OF_PROGRAM;
377 let Word1{22} = VALID_PIXEL_MODE;
378 let Word1{29-23} = CF_INST;
379 let Word1{30} = WHOLE_QUAD_MODE;
380 let Word1{31} = BARRIER;
384 field bits<32> Word0;
387 bits<3> JUMPTABLE_SEL;
389 let Word0{23-0} = ADDR;
390 let Word0{26-24} = JUMPTABLE_SEL;
394 field bits<32> Word1;
400 bits<1> VALID_PIXEL_MODE;
401 bits<1> END_OF_PROGRAM;
405 let Word1{2-0} = POP_COUNT;
406 let Word1{7-3} = CF_CONST;
407 let Word1{9-8} = COND;
408 let Word1{15-10} = COUNT;
409 let Word1{20} = VALID_PIXEL_MODE;
410 let Word1{21} = END_OF_PROGRAM;
411 let Word1{29-22} = CF_INST;
412 let Word1{31} = BARRIER;
416 field bits<32> Word0;
419 bits<4> KCACHE_BANK0;
420 bits<4> KCACHE_BANK1;
421 bits<2> KCACHE_MODE0;
423 let Word0{21-0} = ADDR;
424 let Word0{25-22} = KCACHE_BANK0;
425 let Word0{29-26} = KCACHE_BANK1;
426 let Word0{31-30} = KCACHE_MODE0;
430 field bits<32> Word1;
432 bits<2> KCACHE_MODE1;
433 bits<8> KCACHE_ADDR0;
434 bits<8> KCACHE_ADDR1;
438 bits<1> WHOLE_QUAD_MODE;
441 let Word1{1-0} = KCACHE_MODE1;
442 let Word1{9-2} = KCACHE_ADDR0;
443 let Word1{17-10} = KCACHE_ADDR1;
444 let Word1{24-18} = COUNT;
445 let Word1{25} = ALT_CONST;
446 let Word1{29-26} = CF_INST;
447 let Word1{30} = WHOLE_QUAD_MODE;
448 let Word1{31} = BARRIER;
451 class CF_ALLOC_EXPORT_WORD0_RAT {
452 field bits<32> Word0;
463 let Word0{3-0} = rat_id;
464 let Word0{9-4} = rat_inst;
465 let Word0{10} = 0; // Reserved
466 let Word0{12-11} = rim;
467 let Word0{14-13} = type;
468 let Word0{21-15} = rw_gpr;
469 let Word0{22} = rw_rel;
470 let Word0{29-23} = index_gpr;
471 let Word0{31-30} = elem_size;
474 class CF_ALLOC_EXPORT_WORD1_BUF {
475 field bits<32> Word1;
486 let Word1{11-0} = array_size;
487 let Word1{15-12} = comp_mask;
488 let Word1{19-16} = burst_count;
491 let Word1{29-22} = cf_inst;
492 let Word1{30} = mark;
493 let Word1{31} = barrier;