1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for R600
13 //===----------------------------------------------------------------------===//
15 #include "R600ISelLowering.h"
16 #include "R600Defines.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineFunctionInfo.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/IR/Argument.h"
24 #include "llvm/IR/Function.h"
28 R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
29 AMDGPUTargetLowering(TM),
30 TII(static_cast<const R600InstrInfo*>(TM.getInstrInfo())) {
31 setOperationAction(ISD::MUL, MVT::i64, Expand);
32 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
33 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
34 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
35 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
36 computeRegisterProperties();
38 setOperationAction(ISD::FADD, MVT::v4f32, Expand);
39 setOperationAction(ISD::FMUL, MVT::v4f32, Expand);
40 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
41 setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
43 setOperationAction(ISD::ADD, MVT::v4i32, Expand);
44 setOperationAction(ISD::AND, MVT::v4i32, Expand);
45 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Expand);
46 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Expand);
47 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Expand);
48 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Expand);
49 setOperationAction(ISD::UDIV, MVT::v4i32, Expand);
50 setOperationAction(ISD::UREM, MVT::v4i32, Expand);
51 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
53 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
54 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
56 setOperationAction(ISD::FSUB, MVT::f32, Expand);
58 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
59 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
60 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
61 setOperationAction(ISD::FPOW, MVT::f32, Custom);
63 setOperationAction(ISD::ROTL, MVT::i32, Custom);
65 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
66 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
68 setOperationAction(ISD::SETCC, MVT::i32, Custom);
69 setOperationAction(ISD::SETCC, MVT::f32, Custom);
70 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
72 setOperationAction(ISD::SELECT, MVT::i32, Custom);
73 setOperationAction(ISD::SELECT, MVT::f32, Custom);
75 // Legalize loads and stores to the private address space.
76 setOperationAction(ISD::LOAD, MVT::i32, Custom);
77 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
78 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
79 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
80 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
81 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
82 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Custom);
83 setOperationAction(ISD::STORE, MVT::i8, Custom);
84 setOperationAction(ISD::STORE, MVT::i32, Custom);
85 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
86 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
88 setOperationAction(ISD::LOAD, MVT::i32, Custom);
89 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
90 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
92 setTargetDAGCombine(ISD::FP_ROUND);
93 setTargetDAGCombine(ISD::FP_TO_SINT);
94 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
95 setTargetDAGCombine(ISD::SELECT_CC);
97 setSchedulingPreference(Sched::VLIW);
100 MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
101 MachineInstr * MI, MachineBasicBlock * BB) const {
102 MachineFunction * MF = BB->getParent();
103 MachineRegisterInfo &MRI = MF->getRegInfo();
104 MachineBasicBlock::iterator I = *MI;
106 switch (MI->getOpcode()) {
107 default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
108 case AMDGPU::SHADER_TYPE: break;
109 case AMDGPU::CLAMP_R600: {
110 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
112 MI->getOperand(0).getReg(),
113 MI->getOperand(1).getReg());
114 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
118 case AMDGPU::FABS_R600: {
119 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
121 MI->getOperand(0).getReg(),
122 MI->getOperand(1).getReg());
123 TII->addFlag(NewMI, 0, MO_FLAG_ABS);
127 case AMDGPU::FNEG_R600: {
128 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
130 MI->getOperand(0).getReg(),
131 MI->getOperand(1).getReg());
132 TII->addFlag(NewMI, 0, MO_FLAG_NEG);
136 case AMDGPU::MASK_WRITE: {
137 unsigned maskedRegister = MI->getOperand(0).getReg();
138 assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
139 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
140 TII->addFlag(defInstr, 0, MO_FLAG_MASK);
144 case AMDGPU::MOV_IMM_F32:
145 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
146 MI->getOperand(1).getFPImm()->getValueAPF()
147 .bitcastToAPInt().getZExtValue());
149 case AMDGPU::MOV_IMM_I32:
150 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
151 MI->getOperand(1).getImm());
153 case AMDGPU::CONST_COPY: {
154 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
155 MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
156 TII->setImmOperand(NewMI, R600Operands::SRC0_SEL,
157 MI->getOperand(1).getImm());
161 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
162 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
163 unsigned EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
165 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
166 .addOperand(MI->getOperand(0))
167 .addOperand(MI->getOperand(1))
168 .addImm(EOP); // Set End of program bit
173 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
174 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
176 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
177 .addOperand(MI->getOperand(3))
178 .addOperand(MI->getOperand(4))
179 .addOperand(MI->getOperand(5))
180 .addOperand(MI->getOperand(6));
181 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
182 .addOperand(MI->getOperand(2))
183 .addOperand(MI->getOperand(4))
184 .addOperand(MI->getOperand(5))
185 .addOperand(MI->getOperand(6));
186 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
187 .addOperand(MI->getOperand(0))
188 .addOperand(MI->getOperand(1))
189 .addOperand(MI->getOperand(4))
190 .addOperand(MI->getOperand(5))
191 .addOperand(MI->getOperand(6))
192 .addReg(T0, RegState::Implicit)
193 .addReg(T1, RegState::Implicit);
197 case AMDGPU::TXD_SHADOW: {
198 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
199 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
201 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
202 .addOperand(MI->getOperand(3))
203 .addOperand(MI->getOperand(4))
204 .addOperand(MI->getOperand(5))
205 .addOperand(MI->getOperand(6));
206 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
207 .addOperand(MI->getOperand(2))
208 .addOperand(MI->getOperand(4))
209 .addOperand(MI->getOperand(5))
210 .addOperand(MI->getOperand(6));
211 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
212 .addOperand(MI->getOperand(0))
213 .addOperand(MI->getOperand(1))
214 .addOperand(MI->getOperand(4))
215 .addOperand(MI->getOperand(5))
216 .addOperand(MI->getOperand(6))
217 .addReg(T0, RegState::Implicit)
218 .addReg(T1, RegState::Implicit);
223 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
224 .addOperand(MI->getOperand(0))
228 case AMDGPU::BRANCH_COND_f32: {
229 MachineInstr *NewMI =
230 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
231 AMDGPU::PREDICATE_BIT)
232 .addOperand(MI->getOperand(1))
233 .addImm(OPCODE_IS_NOT_ZERO)
235 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
236 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
237 .addOperand(MI->getOperand(0))
238 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
242 case AMDGPU::BRANCH_COND_i32: {
243 MachineInstr *NewMI =
244 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
245 AMDGPU::PREDICATE_BIT)
246 .addOperand(MI->getOperand(1))
247 .addImm(OPCODE_IS_NOT_ZERO_INT)
249 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
250 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
251 .addOperand(MI->getOperand(0))
252 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
256 case AMDGPU::EG_ExportSwz:
257 case AMDGPU::R600_ExportSwz: {
258 // Instruction is left unmodified if its not the last one of its type
259 bool isLastInstructionOfItsType = true;
260 unsigned InstExportType = MI->getOperand(1).getImm();
261 for (MachineBasicBlock::iterator NextExportInst = llvm::next(I),
262 EndBlock = BB->end(); NextExportInst != EndBlock;
263 NextExportInst = llvm::next(NextExportInst)) {
264 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
265 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
266 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
268 if (CurrentInstExportType == InstExportType) {
269 isLastInstructionOfItsType = false;
274 bool EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN)? 1 : 0;
275 if (!EOP && !isLastInstructionOfItsType)
277 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
278 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
279 .addOperand(MI->getOperand(0))
280 .addOperand(MI->getOperand(1))
281 .addOperand(MI->getOperand(2))
282 .addOperand(MI->getOperand(3))
283 .addOperand(MI->getOperand(4))
284 .addOperand(MI->getOperand(5))
285 .addOperand(MI->getOperand(6))
290 case AMDGPU::RETURN: {
291 // RETURN instructions must have the live-out registers as implicit uses,
292 // otherwise they appear dead.
293 R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
294 MachineInstrBuilder MIB(*MF, MI);
295 for (unsigned i = 0, e = MFI->LiveOuts.size(); i != e; ++i)
296 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
301 MI->eraseFromParent();
305 //===----------------------------------------------------------------------===//
306 // Custom DAG Lowering Operations
307 //===----------------------------------------------------------------------===//
309 using namespace llvm::Intrinsic;
310 using namespace llvm::AMDGPUIntrinsic;
312 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
313 switch (Op.getOpcode()) {
314 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
315 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
316 case ISD::ROTL: return LowerROTL(Op, DAG);
317 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
318 case ISD::SELECT: return LowerSELECT(Op, DAG);
319 case ISD::SETCC: return LowerSETCC(Op, DAG);
320 case ISD::STORE: return LowerSTORE(Op, DAG);
321 case ISD::LOAD: return LowerLOAD(Op, DAG);
322 case ISD::FPOW: return LowerFPOW(Op, DAG);
323 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
324 case ISD::INTRINSIC_VOID: {
325 SDValue Chain = Op.getOperand(0);
326 unsigned IntrinsicID =
327 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
328 switch (IntrinsicID) {
329 case AMDGPUIntrinsic::AMDGPU_store_output: {
330 MachineFunction &MF = DAG.getMachineFunction();
331 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
332 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
333 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
334 MFI->LiveOuts.push_back(Reg);
335 return DAG.getCopyToReg(Chain, Op.getDebugLoc(), Reg, Op.getOperand(2));
337 case AMDGPUIntrinsic::R600_store_swizzle: {
338 const SDValue Args[8] = {
340 Op.getOperand(2), // Export Value
341 Op.getOperand(3), // ArrayBase
342 Op.getOperand(4), // Type
343 DAG.getConstant(0, MVT::i32), // SWZ_X
344 DAG.getConstant(1, MVT::i32), // SWZ_Y
345 DAG.getConstant(2, MVT::i32), // SWZ_Z
346 DAG.getConstant(3, MVT::i32) // SWZ_W
348 return DAG.getNode(AMDGPUISD::EXPORT, Op.getDebugLoc(), Op.getValueType(),
352 // default for switch(IntrinsicID)
355 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
358 case ISD::INTRINSIC_WO_CHAIN: {
359 unsigned IntrinsicID =
360 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
361 EVT VT = Op.getValueType();
362 DebugLoc DL = Op.getDebugLoc();
363 switch(IntrinsicID) {
364 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
365 case AMDGPUIntrinsic::R600_load_input: {
366 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
367 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
368 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT);
371 case AMDGPUIntrinsic::R600_interp_input: {
372 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
373 int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
374 MachineSDNode *interp;
376 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
377 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
378 return DAG.getTargetExtractSubreg(
379 TII->getRegisterInfo().getSubRegFromChannel(slot % 4),
380 DL, MVT::f32, SDValue(interp, 0));
384 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
385 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
386 CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
387 AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1), MVT::f32),
388 CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
389 AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb), MVT::f32));
391 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
392 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
393 CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
394 AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1), MVT::f32),
395 CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
396 AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb), MVT::f32));
398 return SDValue(interp, slot % 2);
401 case r600_read_ngroups_x:
402 return LowerImplicitParameter(DAG, VT, DL, 0);
403 case r600_read_ngroups_y:
404 return LowerImplicitParameter(DAG, VT, DL, 1);
405 case r600_read_ngroups_z:
406 return LowerImplicitParameter(DAG, VT, DL, 2);
407 case r600_read_global_size_x:
408 return LowerImplicitParameter(DAG, VT, DL, 3);
409 case r600_read_global_size_y:
410 return LowerImplicitParameter(DAG, VT, DL, 4);
411 case r600_read_global_size_z:
412 return LowerImplicitParameter(DAG, VT, DL, 5);
413 case r600_read_local_size_x:
414 return LowerImplicitParameter(DAG, VT, DL, 6);
415 case r600_read_local_size_y:
416 return LowerImplicitParameter(DAG, VT, DL, 7);
417 case r600_read_local_size_z:
418 return LowerImplicitParameter(DAG, VT, DL, 8);
420 case r600_read_tgid_x:
421 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
423 case r600_read_tgid_y:
424 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
426 case r600_read_tgid_z:
427 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
429 case r600_read_tidig_x:
430 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
432 case r600_read_tidig_y:
433 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
435 case r600_read_tidig_z:
436 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
439 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
442 } // end switch(Op.getOpcode())
446 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
447 SmallVectorImpl<SDValue> &Results,
448 SelectionDAG &DAG) const {
449 switch (N->getOpcode()) {
451 case ISD::FP_TO_UINT: Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
454 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
455 Results.push_back(SDValue(Node, 0));
456 Results.push_back(SDValue(Node, 1));
457 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
459 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
463 SDNode *Node = LowerSTORE(SDValue(N, 0), DAG).getNode();
464 Results.push_back(SDValue(Node, 0));
469 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
474 Op, DAG.getConstantFP(0.0f, MVT::f32),
475 DAG.getCondCode(ISD::SETNE)
479 SDValue R600TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
480 SDValue Chain = Op.getOperand(0);
481 SDValue CC = Op.getOperand(1);
482 SDValue LHS = Op.getOperand(2);
483 SDValue RHS = Op.getOperand(3);
484 SDValue JumpT = Op.getOperand(4);
488 if (LHS.getValueType() == MVT::i32) {
489 CmpValue = DAG.getNode(
494 DAG.getConstant(-1, MVT::i32),
495 DAG.getConstant(0, MVT::i32),
497 } else if (LHS.getValueType() == MVT::f32) {
498 CmpValue = DAG.getNode(
503 DAG.getConstantFP(1.0f, MVT::f32),
504 DAG.getConstantFP(0.0f, MVT::f32),
507 assert(0 && "Not valid type for br_cc");
509 Result = DAG.getNode(
510 AMDGPUISD::BRANCH_COND,
511 CmpValue.getDebugLoc(),
517 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
519 unsigned DwordOffset) const {
520 unsigned ByteOffset = DwordOffset * 4;
521 PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
522 AMDGPUAS::PARAM_I_ADDRESS);
524 // We shouldn't be using an offset wider than 16-bits for implicit parameters.
525 assert(isInt<16>(ByteOffset));
527 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
528 DAG.getConstant(ByteOffset, MVT::i32), // PTR
529 MachinePointerInfo(ConstantPointerNull::get(PtrType)),
530 false, false, false, 0);
533 SDValue R600TargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
535 MachineFunction &MF = DAG.getMachineFunction();
536 const AMDGPUFrameLowering *TFL =
537 static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering());
539 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op);
542 unsigned FrameIndex = FIN->getIndex();
543 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
544 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), MVT::i32);
547 SDValue R600TargetLowering::LowerROTL(SDValue Op, SelectionDAG &DAG) const {
548 DebugLoc DL = Op.getDebugLoc();
549 EVT VT = Op.getValueType();
551 return DAG.getNode(AMDGPUISD::BITALIGN, DL, VT,
554 DAG.getNode(ISD::SUB, DL, VT,
555 DAG.getConstant(32, MVT::i32),
559 bool R600TargetLowering::isZero(SDValue Op) const {
560 if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
561 return Cst->isNullValue();
562 } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
563 return CstFP->isZero();
569 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
570 DebugLoc DL = Op.getDebugLoc();
571 EVT VT = Op.getValueType();
573 SDValue LHS = Op.getOperand(0);
574 SDValue RHS = Op.getOperand(1);
575 SDValue True = Op.getOperand(2);
576 SDValue False = Op.getOperand(3);
577 SDValue CC = Op.getOperand(4);
580 // LHS and RHS are guaranteed to be the same value type
581 EVT CompareVT = LHS.getValueType();
583 // Check if we can lower this to a native operation.
585 // Try to lower to a CND* instruction:
586 // CND* instructions requires RHS to be zero. Some SELECT_CC nodes that
587 // can be lowered to CND* instructions can also be lowered to SET*
588 // instructions. CND* instructions are cheaper, because they dont't
589 // require additional instructions to convert their result to the correct
590 // value type, so this check should be first.
591 if (isZero(LHS) || isZero(RHS)) {
592 SDValue Cond = (isZero(LHS) ? RHS : LHS);
593 SDValue Zero = (isZero(LHS) ? LHS : RHS);
594 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
595 if (CompareVT != VT) {
596 // Bitcast True / False to the correct types. This will end up being
597 // a nop, but it allows us to define only a single pattern in the
598 // .TD files for each CND* instruction rather than having to have
599 // one pattern for integer True/False and one for fp True/False
600 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
601 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
604 CCOpcode = ISD::getSetCCSwappedOperands(CCOpcode);
617 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
625 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
628 DAG.getCondCode(CCOpcode));
629 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
632 // Try to lower to a SET* instruction:
634 // CompareVT == MVT::f32 and VT == MVT::i32 is supported by the hardware,
635 // but for the other case where CompareVT != VT, all operands of
636 // SELECT_CC need to have the same value type, so we need to change True and
637 // False to be the same type as LHS and RHS, and then convert the result of
638 // the select_cc back to the correct type.
640 // Move hardware True/False values to the correct operand.
641 if (isHWTrueValue(False) && isHWFalseValue(True)) {
642 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
643 std::swap(False, True);
644 CC = DAG.getCondCode(ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32));
647 if (isHWTrueValue(True) && isHWFalseValue(False)) {
648 if (CompareVT != VT && VT == MVT::f32 && CompareVT == MVT::i32) {
649 SDValue Boolean = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
651 DAG.getConstant(-1, MVT::i32),
652 DAG.getConstant(0, MVT::i32),
654 // Convert integer values of true (-1) and false (0) to fp values of
655 // true (1.0f) and false (0.0f).
656 SDValue LSB = DAG.getNode(ISD::AND, DL, MVT::i32, Boolean,
657 DAG.getConstant(1, MVT::i32));
658 return DAG.getNode(ISD::UINT_TO_FP, DL, VT, LSB);
660 // This SELECT_CC is already legal.
661 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
665 // Possible Min/Max pattern
666 SDValue MinMax = LowerMinMax(Op, DAG);
667 if (MinMax.getNode()) {
671 // If we make it this for it means we have no native instructions to handle
672 // this SELECT_CC, so we must lower it.
673 SDValue HWTrue, HWFalse;
675 if (CompareVT == MVT::f32) {
676 HWTrue = DAG.getConstantFP(1.0f, CompareVT);
677 HWFalse = DAG.getConstantFP(0.0f, CompareVT);
678 } else if (CompareVT == MVT::i32) {
679 HWTrue = DAG.getConstant(-1, CompareVT);
680 HWFalse = DAG.getConstant(0, CompareVT);
683 assert(!"Unhandled value type in LowerSELECT_CC");
686 // Lower this unsupported SELECT_CC into a combination of two supported
687 // SELECT_CC operations.
688 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
690 return DAG.getNode(ISD::SELECT_CC, DL, VT,
693 DAG.getCondCode(ISD::SETNE));
696 SDValue R600TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
697 return DAG.getNode(ISD::SELECT_CC,
701 DAG.getConstant(0, MVT::i32),
704 DAG.getCondCode(ISD::SETNE));
707 SDValue R600TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
709 SDValue LHS = Op.getOperand(0);
710 SDValue RHS = Op.getOperand(1);
711 SDValue CC = Op.getOperand(2);
712 DebugLoc DL = Op.getDebugLoc();
713 assert(Op.getValueType() == MVT::i32);
714 if (LHS.getValueType() == MVT::i32) {
720 DAG.getConstant(-1, MVT::i32),
721 DAG.getConstant(0, MVT::i32),
723 } else if (LHS.getValueType() == MVT::f32) {
729 DAG.getConstantFP(1.0f, MVT::f32),
730 DAG.getConstantFP(0.0f, MVT::f32),
738 assert(0 && "Not valid type for set_cc");
744 DAG.getConstant(1, MVT::i32),
749 /// LLVM generates byte-addresed pointers. For indirect addressing, we need to
750 /// convert these pointers to a register index. Each register holds
751 /// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
752 /// \p StackWidth, which tells us how many of the 4 sub-registrers will be used
753 /// for indirect addressing.
754 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
756 SelectionDAG &DAG) const {
768 default: llvm_unreachable("Invalid stack width");
771 return DAG.getNode(ISD::SRL, Ptr.getDebugLoc(), Ptr.getValueType(), Ptr,
772 DAG.getConstant(SRLPad, MVT::i32));
775 void R600TargetLowering::getStackAddress(unsigned StackWidth,
778 unsigned &PtrIncr) const {
779 switch (StackWidth) {
790 Channel = ElemIdx % 2;
804 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
805 DebugLoc DL = Op.getDebugLoc();
806 StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
807 SDValue Chain = Op.getOperand(0);
808 SDValue Value = Op.getOperand(1);
809 SDValue Ptr = Op.getOperand(2);
811 if (StoreNode->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
812 Ptr->getOpcode() != AMDGPUISD::DWORDADDR) {
813 // Convert pointer from byte address to dword address.
814 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(),
815 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
816 Ptr, DAG.getConstant(2, MVT::i32)));
818 if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
819 assert(!"Truncated and indexed stores not supported yet");
821 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
826 EVT ValueVT = Value.getValueType();
828 if (StoreNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
832 // Lowering for indirect addressing
834 const MachineFunction &MF = DAG.getMachineFunction();
835 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
836 getTargetMachine().getFrameLowering());
837 unsigned StackWidth = TFL->getStackWidth(MF);
839 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
841 if (ValueVT.isVector()) {
842 unsigned NumElemVT = ValueVT.getVectorNumElements();
843 EVT ElemVT = ValueVT.getVectorElementType();
846 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
847 "vector width in load");
849 for (unsigned i = 0; i < NumElemVT; ++i) {
850 unsigned Channel, PtrIncr;
851 getStackAddress(StackWidth, i, Channel, PtrIncr);
852 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
853 DAG.getConstant(PtrIncr, MVT::i32));
854 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT,
855 Value, DAG.getConstant(i, MVT::i32));
857 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
859 DAG.getTargetConstant(Channel, MVT::i32));
861 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores, NumElemVT);
863 if (ValueVT == MVT::i8) {
864 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
866 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr,
867 DAG.getTargetConstant(0, MVT::i32)); // Channel
873 // return (512 + (kc_bank << 12)
875 ConstantAddressBlock(unsigned AddressSpace) {
876 switch (AddressSpace) {
877 case AMDGPUAS::CONSTANT_BUFFER_0:
879 case AMDGPUAS::CONSTANT_BUFFER_1:
881 case AMDGPUAS::CONSTANT_BUFFER_2:
882 return 512 + 4096 * 2;
883 case AMDGPUAS::CONSTANT_BUFFER_3:
884 return 512 + 4096 * 3;
885 case AMDGPUAS::CONSTANT_BUFFER_4:
886 return 512 + 4096 * 4;
887 case AMDGPUAS::CONSTANT_BUFFER_5:
888 return 512 + 4096 * 5;
889 case AMDGPUAS::CONSTANT_BUFFER_6:
890 return 512 + 4096 * 6;
891 case AMDGPUAS::CONSTANT_BUFFER_7:
892 return 512 + 4096 * 7;
893 case AMDGPUAS::CONSTANT_BUFFER_8:
894 return 512 + 4096 * 8;
895 case AMDGPUAS::CONSTANT_BUFFER_9:
896 return 512 + 4096 * 9;
897 case AMDGPUAS::CONSTANT_BUFFER_10:
898 return 512 + 4096 * 10;
899 case AMDGPUAS::CONSTANT_BUFFER_11:
900 return 512 + 4096 * 11;
901 case AMDGPUAS::CONSTANT_BUFFER_12:
902 return 512 + 4096 * 12;
903 case AMDGPUAS::CONSTANT_BUFFER_13:
904 return 512 + 4096 * 13;
905 case AMDGPUAS::CONSTANT_BUFFER_14:
906 return 512 + 4096 * 14;
907 case AMDGPUAS::CONSTANT_BUFFER_15:
908 return 512 + 4096 * 15;
914 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
916 EVT VT = Op.getValueType();
917 DebugLoc DL = Op.getDebugLoc();
918 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
919 SDValue Chain = Op.getOperand(0);
920 SDValue Ptr = Op.getOperand(1);
923 int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
924 if (ConstantBlock > -1) {
926 if (dyn_cast<ConstantExpr>(LoadNode->getSrcValue()) ||
927 dyn_cast<Constant>(LoadNode->getSrcValue()) ||
928 dyn_cast<ConstantSDNode>(Ptr)) {
930 for (unsigned i = 0; i < 4; i++) {
931 // We want Const position encoded with the following formula :
932 // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
933 // const_index is Ptr computed by llvm using an alignment of 16.
934 // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
935 // then div by 4 at the ISel step
936 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
937 DAG.getConstant(4 * i + ConstantBlock * 16, MVT::i32));
938 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
940 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Slots, 4);
942 // non constant ptr cant be folded, keeps it as a v4f32 load
943 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
944 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
945 DAG.getConstant(LoadNode->getAddressSpace() - 9, MVT::i32)
949 if (!VT.isVector()) {
950 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
951 DAG.getConstant(0, MVT::i32));
954 SDValue MergedValues[2] = {
958 return DAG.getMergeValues(MergedValues, 2, DL);
961 if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
965 // Lowering for indirect addressing
966 const MachineFunction &MF = DAG.getMachineFunction();
967 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
968 getTargetMachine().getFrameLowering());
969 unsigned StackWidth = TFL->getStackWidth(MF);
971 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
974 unsigned NumElemVT = VT.getVectorNumElements();
975 EVT ElemVT = VT.getVectorElementType();
978 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
979 "vector width in load");
981 for (unsigned i = 0; i < NumElemVT; ++i) {
982 unsigned Channel, PtrIncr;
983 getStackAddress(StackWidth, i, Channel, PtrIncr);
984 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
985 DAG.getConstant(PtrIncr, MVT::i32));
986 Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT,
988 DAG.getTargetConstant(Channel, MVT::i32),
991 for (unsigned i = NumElemVT; i < 4; ++i) {
992 Loads[i] = DAG.getUNDEF(ElemVT);
994 EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, 4);
995 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads, 4);
997 LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
999 DAG.getTargetConstant(0, MVT::i32), // Channel
1004 Ops[0] = LoweredLoad;
1007 return DAG.getMergeValues(Ops, 2, DL);
1010 SDValue R600TargetLowering::LowerFPOW(SDValue Op,
1011 SelectionDAG &DAG) const {
1012 DebugLoc DL = Op.getDebugLoc();
1013 EVT VT = Op.getValueType();
1014 SDValue LogBase = DAG.getNode(ISD::FLOG2, DL, VT, Op.getOperand(0));
1015 SDValue MulLogBase = DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), LogBase);
1016 return DAG.getNode(ISD::FEXP2, DL, VT, MulLogBase);
1019 /// XXX Only kernel functions are supported, so we can assume for now that
1020 /// every function is a kernel function, but in the future we should use
1021 /// separate calling conventions for kernel and non-kernel functions.
1022 SDValue R600TargetLowering::LowerFormalArguments(
1024 CallingConv::ID CallConv,
1026 const SmallVectorImpl<ISD::InputArg> &Ins,
1027 DebugLoc DL, SelectionDAG &DAG,
1028 SmallVectorImpl<SDValue> &InVals) const {
1029 unsigned ParamOffsetBytes = 36;
1030 Function::const_arg_iterator FuncArg =
1031 DAG.getMachineFunction().getFunction()->arg_begin();
1032 for (unsigned i = 0, e = Ins.size(); i < e; ++i, ++FuncArg) {
1034 Type *ArgType = FuncArg->getType();
1035 unsigned ArgSizeInBits = ArgType->isPointerTy() ?
1036 32 : ArgType->getPrimitiveSizeInBits();
1037 unsigned ArgBytes = ArgSizeInBits >> 3;
1039 if (ArgSizeInBits < VT.getSizeInBits()) {
1040 assert(!ArgType->isFloatTy() &&
1041 "Extending floating point arguments not supported yet");
1042 ArgVT = MVT::getIntegerVT(ArgSizeInBits);
1046 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1047 AMDGPUAS::PARAM_I_ADDRESS);
1048 SDValue Arg = DAG.getExtLoad(ISD::ZEXTLOAD, DL, VT, DAG.getRoot(),
1049 DAG.getConstant(ParamOffsetBytes, MVT::i32),
1050 MachinePointerInfo(UndefValue::get(PtrTy)),
1051 ArgVT, false, false, ArgBytes);
1052 InVals.push_back(Arg);
1053 ParamOffsetBytes += ArgBytes;
1058 EVT R600TargetLowering::getSetCCResultType(EVT VT) const {
1059 if (!VT.isVector()) return MVT::i32;
1060 return VT.changeVectorElementTypeToInteger();
1063 //===----------------------------------------------------------------------===//
1064 // Custom DAG Optimizations
1065 //===----------------------------------------------------------------------===//
1067 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
1068 DAGCombinerInfo &DCI) const {
1069 SelectionDAG &DAG = DCI.DAG;
1071 switch (N->getOpcode()) {
1072 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1073 case ISD::FP_ROUND: {
1074 SDValue Arg = N->getOperand(0);
1075 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1076 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), N->getValueType(0),
1082 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1083 // (i32 select_cc f32, f32, -1, 0 cc)
1085 // Mesa's GLSL frontend generates the above pattern a lot and we can lower
1086 // this to one of the SET*_DX10 instructions.
1087 case ISD::FP_TO_SINT: {
1088 SDValue FNeg = N->getOperand(0);
1089 if (FNeg.getOpcode() != ISD::FNEG) {
1092 SDValue SelectCC = FNeg.getOperand(0);
1093 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1094 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1095 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
1096 !isHWTrueValue(SelectCC.getOperand(2)) ||
1097 !isHWFalseValue(SelectCC.getOperand(3))) {
1101 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N->getValueType(0),
1102 SelectCC.getOperand(0), // LHS
1103 SelectCC.getOperand(1), // RHS
1104 DAG.getConstant(-1, MVT::i32), // True
1105 DAG.getConstant(0, MVT::i32), // Flase
1106 SelectCC.getOperand(4)); // CC
1110 // Extract_vec (Build_vector) generated by custom lowering
1111 // also needs to be customly combined
1112 case ISD::EXTRACT_VECTOR_ELT: {
1113 SDValue Arg = N->getOperand(0);
1114 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1115 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1116 unsigned Element = Const->getZExtValue();
1117 return Arg->getOperand(Element);
1120 if (Arg.getOpcode() == ISD::BITCAST &&
1121 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
1122 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1123 unsigned Element = Const->getZExtValue();
1124 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getVTList(),
1125 Arg->getOperand(0).getOperand(Element));
1130 case ISD::SELECT_CC: {
1131 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1132 // selectcc x, y, a, b, inv(cc)
1133 SDValue LHS = N->getOperand(0);
1134 if (LHS.getOpcode() != ISD::SELECT_CC) {
1138 SDValue RHS = N->getOperand(1);
1139 SDValue True = N->getOperand(2);
1140 SDValue False = N->getOperand(3);
1142 if (LHS.getOperand(2).getNode() != True.getNode() ||
1143 LHS.getOperand(3).getNode() != False.getNode() ||
1144 RHS.getNode() != False.getNode() ||
1145 cast<CondCodeSDNode>(N->getOperand(4))->get() != ISD::SETEQ) {
1149 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(LHS->getOperand(4))->get();
1150 CCOpcode = ISD::getSetCCInverse(
1151 CCOpcode, LHS.getOperand(0).getValueType().isInteger());
1152 return DAG.getSelectCC(N->getDebugLoc(),
1159 case AMDGPUISD::EXPORT: {
1160 SDValue Arg = N->getOperand(1);
1161 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1163 SDValue NewBldVec[4] = {
1164 DAG.getUNDEF(MVT::f32),
1165 DAG.getUNDEF(MVT::f32),
1166 DAG.getUNDEF(MVT::f32),
1167 DAG.getUNDEF(MVT::f32)
1169 SDValue NewArgs[8] = {
1170 N->getOperand(0), // Chain
1172 N->getOperand(2), // ArrayBase
1173 N->getOperand(3), // Type
1174 N->getOperand(4), // SWZ_X
1175 N->getOperand(5), // SWZ_Y
1176 N->getOperand(6), // SWZ_Z
1177 N->getOperand(7) // SWZ_W
1179 for (unsigned i = 0; i < Arg.getNumOperands(); i++) {
1180 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Arg.getOperand(i))) {
1182 NewArgs[4 + i] = DAG.getConstant(4, MVT::i32); // SEL_0
1183 } else if (C->isExactlyValue(1.0)) {
1184 NewArgs[4 + i] = DAG.getConstant(5, MVT::i32); // SEL_0
1186 NewBldVec[i] = Arg.getOperand(i);
1189 NewBldVec[i] = Arg.getOperand(i);
1192 DebugLoc DL = N->getDebugLoc();
1193 NewArgs[1] = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4f32, NewBldVec, 4);
1194 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs, 8);