1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for R600
13 //===----------------------------------------------------------------------===//
15 #include "R600ISelLowering.h"
16 #include "R600Defines.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineFunctionInfo.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/IR/Argument.h"
25 #include "llvm/IR/Function.h"
29 R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
30 AMDGPUTargetLowering(TM),
31 Gen(TM.getSubtarget<AMDGPUSubtarget>().getGeneration()) {
32 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
33 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
34 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
35 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
36 computeRegisterProperties();
38 setOperationAction(ISD::FADD, MVT::v4f32, Expand);
39 setOperationAction(ISD::FMUL, MVT::v4f32, Expand);
40 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
41 setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
43 setOperationAction(ISD::FCOS, MVT::f32, Custom);
44 setOperationAction(ISD::FSIN, MVT::f32, Custom);
46 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Expand);
47 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Expand);
48 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Expand);
49 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Expand);
50 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
52 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
53 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
55 setOperationAction(ISD::FSUB, MVT::f32, Expand);
57 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
58 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
59 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
61 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
62 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
64 setOperationAction(ISD::SETCC, MVT::i32, Expand);
65 setOperationAction(ISD::SETCC, MVT::f32, Expand);
66 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
68 setOperationAction(ISD::SELECT, MVT::i32, Custom);
69 setOperationAction(ISD::SELECT, MVT::f32, Custom);
71 // Legalize loads and stores to the private address space.
72 setOperationAction(ISD::LOAD, MVT::i32, Custom);
73 setOperationAction(ISD::LOAD, MVT::v2i32, Expand);
74 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
75 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
76 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
77 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
78 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
79 setOperationAction(ISD::STORE, MVT::i8, Custom);
80 setOperationAction(ISD::STORE, MVT::i32, Custom);
81 setOperationAction(ISD::STORE, MVT::v2i32, Expand);
82 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
84 setOperationAction(ISD::LOAD, MVT::i32, Custom);
85 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
86 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
88 setTargetDAGCombine(ISD::FP_ROUND);
89 setTargetDAGCombine(ISD::FP_TO_SINT);
90 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
91 setTargetDAGCombine(ISD::SELECT_CC);
93 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
95 setBooleanContents(ZeroOrNegativeOneBooleanContent);
96 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
97 setSchedulingPreference(Sched::VLIW);
100 MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
101 MachineInstr * MI, MachineBasicBlock * BB) const {
102 MachineFunction * MF = BB->getParent();
103 MachineRegisterInfo &MRI = MF->getRegInfo();
104 MachineBasicBlock::iterator I = *MI;
105 const R600InstrInfo *TII =
106 static_cast<const R600InstrInfo*>(MF->getTarget().getInstrInfo());
108 switch (MI->getOpcode()) {
109 default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
110 case AMDGPU::CLAMP_R600: {
111 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
113 MI->getOperand(0).getReg(),
114 MI->getOperand(1).getReg());
115 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
119 case AMDGPU::FABS_R600: {
120 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
122 MI->getOperand(0).getReg(),
123 MI->getOperand(1).getReg());
124 TII->addFlag(NewMI, 0, MO_FLAG_ABS);
128 case AMDGPU::FNEG_R600: {
129 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
131 MI->getOperand(0).getReg(),
132 MI->getOperand(1).getReg());
133 TII->addFlag(NewMI, 0, MO_FLAG_NEG);
137 case AMDGPU::MASK_WRITE: {
138 unsigned maskedRegister = MI->getOperand(0).getReg();
139 assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
140 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
141 TII->addFlag(defInstr, 0, MO_FLAG_MASK);
145 case AMDGPU::LDS_READ_RET: {
146 MachineInstrBuilder NewMI = BuildMI(*BB, I, BB->findDebugLoc(I),
147 TII->get(MI->getOpcode()),
149 for (unsigned i = 1, e = MI->getNumOperands(); i < e; ++i) {
150 NewMI.addOperand(MI->getOperand(i));
152 TII->buildDefaultInstruction(*BB, I, AMDGPU::MOV,
153 MI->getOperand(0).getReg(),
158 case AMDGPU::MOV_IMM_F32:
159 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
160 MI->getOperand(1).getFPImm()->getValueAPF()
161 .bitcastToAPInt().getZExtValue());
163 case AMDGPU::MOV_IMM_I32:
164 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
165 MI->getOperand(1).getImm());
167 case AMDGPU::CONST_COPY: {
168 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
169 MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
170 TII->setImmOperand(NewMI, AMDGPU::OpName::src0_sel,
171 MI->getOperand(1).getImm());
175 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
176 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
177 unsigned EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
179 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
180 .addOperand(MI->getOperand(0))
181 .addOperand(MI->getOperand(1))
182 .addImm(EOP); // Set End of program bit
187 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
188 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
189 MachineOperand &RID = MI->getOperand(4);
190 MachineOperand &SID = MI->getOperand(5);
191 unsigned TextureId = MI->getOperand(6).getImm();
192 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
193 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
205 case 8: // ShadowRect
216 case 11: // Shadow1DArray
220 case 12: // Shadow2DArray
224 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
225 .addOperand(MI->getOperand(3))
243 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
244 .addOperand(MI->getOperand(2))
262 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
263 .addOperand(MI->getOperand(0))
264 .addOperand(MI->getOperand(1))
282 .addReg(T0, RegState::Implicit)
283 .addReg(T1, RegState::Implicit);
287 case AMDGPU::TXD_SHADOW: {
288 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
289 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
290 MachineOperand &RID = MI->getOperand(4);
291 MachineOperand &SID = MI->getOperand(5);
292 unsigned TextureId = MI->getOperand(6).getImm();
293 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
294 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
306 case 8: // ShadowRect
317 case 11: // Shadow1DArray
321 case 12: // Shadow2DArray
326 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
327 .addOperand(MI->getOperand(3))
345 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
346 .addOperand(MI->getOperand(2))
364 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
365 .addOperand(MI->getOperand(0))
366 .addOperand(MI->getOperand(1))
384 .addReg(T0, RegState::Implicit)
385 .addReg(T1, RegState::Implicit);
390 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
391 .addOperand(MI->getOperand(0));
394 case AMDGPU::BRANCH_COND_f32: {
395 MachineInstr *NewMI =
396 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
397 AMDGPU::PREDICATE_BIT)
398 .addOperand(MI->getOperand(1))
399 .addImm(OPCODE_IS_NOT_ZERO)
401 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
402 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
403 .addOperand(MI->getOperand(0))
404 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
408 case AMDGPU::BRANCH_COND_i32: {
409 MachineInstr *NewMI =
410 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
411 AMDGPU::PREDICATE_BIT)
412 .addOperand(MI->getOperand(1))
413 .addImm(OPCODE_IS_NOT_ZERO_INT)
415 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
416 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
417 .addOperand(MI->getOperand(0))
418 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
422 case AMDGPU::EG_ExportSwz:
423 case AMDGPU::R600_ExportSwz: {
424 // Instruction is left unmodified if its not the last one of its type
425 bool isLastInstructionOfItsType = true;
426 unsigned InstExportType = MI->getOperand(1).getImm();
427 for (MachineBasicBlock::iterator NextExportInst = llvm::next(I),
428 EndBlock = BB->end(); NextExportInst != EndBlock;
429 NextExportInst = llvm::next(NextExportInst)) {
430 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
431 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
432 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
434 if (CurrentInstExportType == InstExportType) {
435 isLastInstructionOfItsType = false;
440 bool EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN)? 1 : 0;
441 if (!EOP && !isLastInstructionOfItsType)
443 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
444 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
445 .addOperand(MI->getOperand(0))
446 .addOperand(MI->getOperand(1))
447 .addOperand(MI->getOperand(2))
448 .addOperand(MI->getOperand(3))
449 .addOperand(MI->getOperand(4))
450 .addOperand(MI->getOperand(5))
451 .addOperand(MI->getOperand(6))
456 case AMDGPU::RETURN: {
457 // RETURN instructions must have the live-out registers as implicit uses,
458 // otherwise they appear dead.
459 R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
460 MachineInstrBuilder MIB(*MF, MI);
461 for (unsigned i = 0, e = MFI->LiveOuts.size(); i != e; ++i)
462 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
467 MI->eraseFromParent();
471 //===----------------------------------------------------------------------===//
472 // Custom DAG Lowering Operations
473 //===----------------------------------------------------------------------===//
475 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
476 MachineFunction &MF = DAG.getMachineFunction();
477 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
478 switch (Op.getOpcode()) {
479 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
481 case ISD::FSIN: return LowerTrig(Op, DAG);
482 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
483 case ISD::SELECT: return LowerSELECT(Op, DAG);
484 case ISD::STORE: return LowerSTORE(Op, DAG);
485 case ISD::LOAD: return LowerLOAD(Op, DAG);
486 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
487 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
488 case ISD::INTRINSIC_VOID: {
489 SDValue Chain = Op.getOperand(0);
490 unsigned IntrinsicID =
491 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
492 switch (IntrinsicID) {
493 case AMDGPUIntrinsic::AMDGPU_store_output: {
494 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
495 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
496 MFI->LiveOuts.push_back(Reg);
497 return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2));
499 case AMDGPUIntrinsic::R600_store_swizzle: {
500 const SDValue Args[8] = {
502 Op.getOperand(2), // Export Value
503 Op.getOperand(3), // ArrayBase
504 Op.getOperand(4), // Type
505 DAG.getConstant(0, MVT::i32), // SWZ_X
506 DAG.getConstant(1, MVT::i32), // SWZ_Y
507 DAG.getConstant(2, MVT::i32), // SWZ_Z
508 DAG.getConstant(3, MVT::i32) // SWZ_W
510 return DAG.getNode(AMDGPUISD::EXPORT, SDLoc(Op), Op.getValueType(),
514 // default for switch(IntrinsicID)
517 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
520 case ISD::INTRINSIC_WO_CHAIN: {
521 unsigned IntrinsicID =
522 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
523 EVT VT = Op.getValueType();
525 switch(IntrinsicID) {
526 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
527 case AMDGPUIntrinsic::R600_load_input: {
528 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
529 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
530 MachineFunction &MF = DAG.getMachineFunction();
531 MachineRegisterInfo &MRI = MF.getRegInfo();
533 return DAG.getCopyFromReg(DAG.getEntryNode(),
534 SDLoc(DAG.getEntryNode()), Reg, VT);
537 case AMDGPUIntrinsic::R600_interp_input: {
538 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
539 int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
540 MachineSDNode *interp;
542 const MachineFunction &MF = DAG.getMachineFunction();
543 const R600InstrInfo *TII =
544 static_cast<const R600InstrInfo*>(MF.getTarget().getInstrInfo());
545 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
546 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
547 return DAG.getTargetExtractSubreg(
548 TII->getRegisterInfo().getSubRegFromChannel(slot % 4),
549 DL, MVT::f32, SDValue(interp, 0));
552 MachineFunction &MF = DAG.getMachineFunction();
553 MachineRegisterInfo &MRI = MF.getRegInfo();
554 unsigned RegisterI = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb);
555 unsigned RegisterJ = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1);
556 MRI.addLiveIn(RegisterI);
557 MRI.addLiveIn(RegisterJ);
558 SDValue RegisterINode = DAG.getCopyFromReg(DAG.getEntryNode(),
559 SDLoc(DAG.getEntryNode()), RegisterI, MVT::f32);
560 SDValue RegisterJNode = DAG.getCopyFromReg(DAG.getEntryNode(),
561 SDLoc(DAG.getEntryNode()), RegisterJ, MVT::f32);
564 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
565 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
566 RegisterJNode, RegisterINode);
568 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
569 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
570 RegisterJNode, RegisterINode);
571 return SDValue(interp, slot % 2);
573 case AMDGPUIntrinsic::R600_tex:
574 case AMDGPUIntrinsic::R600_texc:
575 case AMDGPUIntrinsic::R600_txl:
576 case AMDGPUIntrinsic::R600_txlc:
577 case AMDGPUIntrinsic::R600_txb:
578 case AMDGPUIntrinsic::R600_txbc:
579 case AMDGPUIntrinsic::R600_txf:
580 case AMDGPUIntrinsic::R600_txq:
581 case AMDGPUIntrinsic::R600_ddx:
582 case AMDGPUIntrinsic::R600_ddy: {
584 switch (IntrinsicID) {
585 case AMDGPUIntrinsic::R600_tex:
588 case AMDGPUIntrinsic::R600_texc:
591 case AMDGPUIntrinsic::R600_txl:
594 case AMDGPUIntrinsic::R600_txlc:
597 case AMDGPUIntrinsic::R600_txb:
600 case AMDGPUIntrinsic::R600_txbc:
603 case AMDGPUIntrinsic::R600_txf:
606 case AMDGPUIntrinsic::R600_txq:
609 case AMDGPUIntrinsic::R600_ddx:
612 case AMDGPUIntrinsic::R600_ddy:
616 llvm_unreachable("Unknow Texture Operation");
619 SDValue TexArgs[19] = {
620 DAG.getConstant(TextureOp, MVT::i32),
622 DAG.getConstant(0, MVT::i32),
623 DAG.getConstant(1, MVT::i32),
624 DAG.getConstant(2, MVT::i32),
625 DAG.getConstant(3, MVT::i32),
629 DAG.getConstant(0, MVT::i32),
630 DAG.getConstant(1, MVT::i32),
631 DAG.getConstant(2, MVT::i32),
632 DAG.getConstant(3, MVT::i32),
640 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs, 19);
642 case AMDGPUIntrinsic::AMDGPU_dp4: {
644 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
645 DAG.getConstant(0, MVT::i32)),
646 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
647 DAG.getConstant(0, MVT::i32)),
648 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
649 DAG.getConstant(1, MVT::i32)),
650 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
651 DAG.getConstant(1, MVT::i32)),
652 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
653 DAG.getConstant(2, MVT::i32)),
654 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
655 DAG.getConstant(2, MVT::i32)),
656 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
657 DAG.getConstant(3, MVT::i32)),
658 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
659 DAG.getConstant(3, MVT::i32))
661 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args, 8);
664 case Intrinsic::r600_read_ngroups_x:
665 return LowerImplicitParameter(DAG, VT, DL, 0);
666 case Intrinsic::r600_read_ngroups_y:
667 return LowerImplicitParameter(DAG, VT, DL, 1);
668 case Intrinsic::r600_read_ngroups_z:
669 return LowerImplicitParameter(DAG, VT, DL, 2);
670 case Intrinsic::r600_read_global_size_x:
671 return LowerImplicitParameter(DAG, VT, DL, 3);
672 case Intrinsic::r600_read_global_size_y:
673 return LowerImplicitParameter(DAG, VT, DL, 4);
674 case Intrinsic::r600_read_global_size_z:
675 return LowerImplicitParameter(DAG, VT, DL, 5);
676 case Intrinsic::r600_read_local_size_x:
677 return LowerImplicitParameter(DAG, VT, DL, 6);
678 case Intrinsic::r600_read_local_size_y:
679 return LowerImplicitParameter(DAG, VT, DL, 7);
680 case Intrinsic::r600_read_local_size_z:
681 return LowerImplicitParameter(DAG, VT, DL, 8);
683 case Intrinsic::r600_read_tgid_x:
684 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
686 case Intrinsic::r600_read_tgid_y:
687 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
689 case Intrinsic::r600_read_tgid_z:
690 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
692 case Intrinsic::r600_read_tidig_x:
693 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
695 case Intrinsic::r600_read_tidig_y:
696 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
698 case Intrinsic::r600_read_tidig_z:
699 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
702 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
705 } // end switch(Op.getOpcode())
709 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
710 SmallVectorImpl<SDValue> &Results,
711 SelectionDAG &DAG) const {
712 switch (N->getOpcode()) {
714 case ISD::FP_TO_UINT: Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
717 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
718 Results.push_back(SDValue(Node, 0));
719 Results.push_back(SDValue(Node, 1));
720 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
722 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
726 SDNode *Node = LowerSTORE(SDValue(N, 0), DAG).getNode();
727 Results.push_back(SDValue(Node, 0));
732 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
733 // On hw >= R700, COS/SIN input must be between -1. and 1.
734 // Thus we lower them to TRIG ( FRACT ( x / 2Pi + 0.5) - 0.5)
735 EVT VT = Op.getValueType();
736 SDValue Arg = Op.getOperand(0);
737 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,
738 DAG.getNode(ISD::FADD, SDLoc(Op), VT,
739 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
740 DAG.getConstantFP(0.15915494309, MVT::f32)),
741 DAG.getConstantFP(0.5, MVT::f32)));
743 switch (Op.getOpcode()) {
745 TrigNode = AMDGPUISD::COS_HW;
748 TrigNode = AMDGPUISD::SIN_HW;
751 llvm_unreachable("Wrong trig opcode");
753 SDValue TrigVal = DAG.getNode(TrigNode, SDLoc(Op), VT,
754 DAG.getNode(ISD::FADD, SDLoc(Op), VT, FractPart,
755 DAG.getConstantFP(-0.5, MVT::f32)));
756 if (Gen >= AMDGPUSubtarget::R700)
758 // On R600 hw, COS/SIN input must be between -Pi and Pi.
759 return DAG.getNode(ISD::FMUL, SDLoc(Op), VT, TrigVal,
760 DAG.getConstantFP(3.14159265359, MVT::f32));
763 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
768 Op, DAG.getConstantFP(0.0f, MVT::f32),
769 DAG.getCondCode(ISD::SETNE)
773 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
775 unsigned DwordOffset) const {
776 unsigned ByteOffset = DwordOffset * 4;
777 PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
778 AMDGPUAS::CONSTANT_BUFFER_0);
780 // We shouldn't be using an offset wider than 16-bits for implicit parameters.
781 assert(isInt<16>(ByteOffset));
783 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
784 DAG.getConstant(ByteOffset, MVT::i32), // PTR
785 MachinePointerInfo(ConstantPointerNull::get(PtrType)),
786 false, false, false, 0);
789 SDValue R600TargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
791 MachineFunction &MF = DAG.getMachineFunction();
792 const AMDGPUFrameLowering *TFL =
793 static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering());
795 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op);
798 unsigned FrameIndex = FIN->getIndex();
799 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
800 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), MVT::i32);
803 bool R600TargetLowering::isZero(SDValue Op) const {
804 if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
805 return Cst->isNullValue();
806 } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
807 return CstFP->isZero();
813 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
815 EVT VT = Op.getValueType();
817 SDValue LHS = Op.getOperand(0);
818 SDValue RHS = Op.getOperand(1);
819 SDValue True = Op.getOperand(2);
820 SDValue False = Op.getOperand(3);
821 SDValue CC = Op.getOperand(4);
824 // LHS and RHS are guaranteed to be the same value type
825 EVT CompareVT = LHS.getValueType();
827 // Check if we can lower this to a native operation.
829 // Try to lower to a SET* instruction:
831 // SET* can match the following patterns:
833 // select_cc f32, f32, -1, 0, cc_any
834 // select_cc f32, f32, 1.0f, 0.0f, cc_any
835 // select_cc i32, i32, -1, 0, cc_any
838 // Move hardware True/False values to the correct operand.
839 if (isHWTrueValue(False) && isHWFalseValue(True)) {
840 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
841 std::swap(False, True);
842 CC = DAG.getCondCode(ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32));
845 if (isHWTrueValue(True) && isHWFalseValue(False) &&
846 (CompareVT == VT || VT == MVT::i32)) {
847 // This can be matched by a SET* instruction.
848 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
851 // Try to lower to a CND* instruction:
853 // CND* can match the following patterns:
855 // select_cc f32, 0.0, f32, f32, cc_any
856 // select_cc f32, 0.0, i32, i32, cc_any
857 // select_cc i32, 0, f32, f32, cc_any
858 // select_cc i32, 0, i32, i32, cc_any
860 if (isZero(LHS) || isZero(RHS)) {
861 SDValue Cond = (isZero(LHS) ? RHS : LHS);
862 SDValue Zero = (isZero(LHS) ? LHS : RHS);
863 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
864 if (CompareVT != VT) {
865 // Bitcast True / False to the correct types. This will end up being
866 // a nop, but it allows us to define only a single pattern in the
867 // .TD files for each CND* instruction rather than having to have
868 // one pattern for integer True/False and one for fp True/False
869 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
870 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
873 CCOpcode = ISD::getSetCCSwappedOperands(CCOpcode);
886 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
894 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
897 DAG.getCondCode(CCOpcode));
898 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
902 // Possible Min/Max pattern
903 SDValue MinMax = LowerMinMax(Op, DAG);
904 if (MinMax.getNode()) {
908 // If we make it this for it means we have no native instructions to handle
909 // this SELECT_CC, so we must lower it.
910 SDValue HWTrue, HWFalse;
912 if (CompareVT == MVT::f32) {
913 HWTrue = DAG.getConstantFP(1.0f, CompareVT);
914 HWFalse = DAG.getConstantFP(0.0f, CompareVT);
915 } else if (CompareVT == MVT::i32) {
916 HWTrue = DAG.getConstant(-1, CompareVT);
917 HWFalse = DAG.getConstant(0, CompareVT);
920 assert(!"Unhandled value type in LowerSELECT_CC");
923 // Lower this unsupported SELECT_CC into a combination of two supported
924 // SELECT_CC operations.
925 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
927 return DAG.getNode(ISD::SELECT_CC, DL, VT,
930 DAG.getCondCode(ISD::SETNE));
933 SDValue R600TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
934 return DAG.getNode(ISD::SELECT_CC,
938 DAG.getConstant(0, MVT::i32),
941 DAG.getCondCode(ISD::SETNE));
944 /// LLVM generates byte-addresed pointers. For indirect addressing, we need to
945 /// convert these pointers to a register index. Each register holds
946 /// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
947 /// \p StackWidth, which tells us how many of the 4 sub-registrers will be used
948 /// for indirect addressing.
949 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
951 SelectionDAG &DAG) const {
963 default: llvm_unreachable("Invalid stack width");
966 return DAG.getNode(ISD::SRL, SDLoc(Ptr), Ptr.getValueType(), Ptr,
967 DAG.getConstant(SRLPad, MVT::i32));
970 void R600TargetLowering::getStackAddress(unsigned StackWidth,
973 unsigned &PtrIncr) const {
974 switch (StackWidth) {
985 Channel = ElemIdx % 2;
999 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1001 StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
1002 SDValue Chain = Op.getOperand(0);
1003 SDValue Value = Op.getOperand(1);
1004 SDValue Ptr = Op.getOperand(2);
1006 if (StoreNode->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
1007 Ptr->getOpcode() != AMDGPUISD::DWORDADDR) {
1008 // Convert pointer from byte address to dword address.
1009 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(),
1010 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
1011 Ptr, DAG.getConstant(2, MVT::i32)));
1013 if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
1014 assert(!"Truncated and indexed stores not supported yet");
1016 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
1021 EVT ValueVT = Value.getValueType();
1023 if (StoreNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1027 // Lowering for indirect addressing
1029 const MachineFunction &MF = DAG.getMachineFunction();
1030 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
1031 getTargetMachine().getFrameLowering());
1032 unsigned StackWidth = TFL->getStackWidth(MF);
1034 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1036 if (ValueVT.isVector()) {
1037 unsigned NumElemVT = ValueVT.getVectorNumElements();
1038 EVT ElemVT = ValueVT.getVectorElementType();
1041 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1042 "vector width in load");
1044 for (unsigned i = 0; i < NumElemVT; ++i) {
1045 unsigned Channel, PtrIncr;
1046 getStackAddress(StackWidth, i, Channel, PtrIncr);
1047 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1048 DAG.getConstant(PtrIncr, MVT::i32));
1049 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT,
1050 Value, DAG.getConstant(i, MVT::i32));
1052 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1054 DAG.getTargetConstant(Channel, MVT::i32));
1056 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores, NumElemVT);
1058 if (ValueVT == MVT::i8) {
1059 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
1061 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr,
1062 DAG.getTargetConstant(0, MVT::i32)); // Channel
1068 // return (512 + (kc_bank << 12)
1070 ConstantAddressBlock(unsigned AddressSpace) {
1071 switch (AddressSpace) {
1072 case AMDGPUAS::CONSTANT_BUFFER_0:
1074 case AMDGPUAS::CONSTANT_BUFFER_1:
1076 case AMDGPUAS::CONSTANT_BUFFER_2:
1077 return 512 + 4096 * 2;
1078 case AMDGPUAS::CONSTANT_BUFFER_3:
1079 return 512 + 4096 * 3;
1080 case AMDGPUAS::CONSTANT_BUFFER_4:
1081 return 512 + 4096 * 4;
1082 case AMDGPUAS::CONSTANT_BUFFER_5:
1083 return 512 + 4096 * 5;
1084 case AMDGPUAS::CONSTANT_BUFFER_6:
1085 return 512 + 4096 * 6;
1086 case AMDGPUAS::CONSTANT_BUFFER_7:
1087 return 512 + 4096 * 7;
1088 case AMDGPUAS::CONSTANT_BUFFER_8:
1089 return 512 + 4096 * 8;
1090 case AMDGPUAS::CONSTANT_BUFFER_9:
1091 return 512 + 4096 * 9;
1092 case AMDGPUAS::CONSTANT_BUFFER_10:
1093 return 512 + 4096 * 10;
1094 case AMDGPUAS::CONSTANT_BUFFER_11:
1095 return 512 + 4096 * 11;
1096 case AMDGPUAS::CONSTANT_BUFFER_12:
1097 return 512 + 4096 * 12;
1098 case AMDGPUAS::CONSTANT_BUFFER_13:
1099 return 512 + 4096 * 13;
1100 case AMDGPUAS::CONSTANT_BUFFER_14:
1101 return 512 + 4096 * 14;
1102 case AMDGPUAS::CONSTANT_BUFFER_15:
1103 return 512 + 4096 * 15;
1109 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
1111 EVT VT = Op.getValueType();
1113 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1114 SDValue Chain = Op.getOperand(0);
1115 SDValue Ptr = Op.getOperand(1);
1116 SDValue LoweredLoad;
1118 int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
1119 if (ConstantBlock > -1) {
1121 if (dyn_cast<ConstantExpr>(LoadNode->getSrcValue()) ||
1122 dyn_cast<Constant>(LoadNode->getSrcValue()) ||
1123 dyn_cast<ConstantSDNode>(Ptr)) {
1125 for (unsigned i = 0; i < 4; i++) {
1126 // We want Const position encoded with the following formula :
1127 // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
1128 // const_index is Ptr computed by llvm using an alignment of 16.
1129 // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
1130 // then div by 4 at the ISel step
1131 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1132 DAG.getConstant(4 * i + ConstantBlock * 16, MVT::i32));
1133 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1135 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Slots, 4);
1137 // non constant ptr cant be folded, keeps it as a v4f32 load
1138 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
1139 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
1140 DAG.getConstant(LoadNode->getAddressSpace() -
1141 AMDGPUAS::CONSTANT_BUFFER_0, MVT::i32)
1145 if (!VT.isVector()) {
1146 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1147 DAG.getConstant(0, MVT::i32));
1150 SDValue MergedValues[2] = {
1154 return DAG.getMergeValues(MergedValues, 2, DL);
1157 // For most operations returning SDValue() will result int he node being
1158 // expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so
1159 // we need to manually expand loads that may be legal in some address spaces
1160 // and illegal in others. SEXT loads from CONSTANT_BUFFER_0 are supported
1161 // for compute shaders, since the data is sign extended when it is uploaded
1162 // to the buffer. Howerver SEXT loads from other addresspaces are not
1163 // supported, so we need to expand them here.
1164 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
1165 EVT MemVT = LoadNode->getMemoryVT();
1166 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
1167 SDValue ShiftAmount =
1168 DAG.getConstant(VT.getSizeInBits() - MemVT.getSizeInBits(), MVT::i32);
1169 SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr,
1170 LoadNode->getPointerInfo(), MemVT,
1171 LoadNode->isVolatile(),
1172 LoadNode->isNonTemporal(),
1173 LoadNode->getAlignment());
1174 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, NewLoad, ShiftAmount);
1175 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Shl, ShiftAmount);
1177 SDValue MergedValues[2] = { Sra, Chain };
1178 return DAG.getMergeValues(MergedValues, 2, DL);
1181 if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1185 // Lowering for indirect addressing
1186 const MachineFunction &MF = DAG.getMachineFunction();
1187 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering*>(
1188 getTargetMachine().getFrameLowering());
1189 unsigned StackWidth = TFL->getStackWidth(MF);
1191 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1193 if (VT.isVector()) {
1194 unsigned NumElemVT = VT.getVectorNumElements();
1195 EVT ElemVT = VT.getVectorElementType();
1198 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1199 "vector width in load");
1201 for (unsigned i = 0; i < NumElemVT; ++i) {
1202 unsigned Channel, PtrIncr;
1203 getStackAddress(StackWidth, i, Channel, PtrIncr);
1204 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1205 DAG.getConstant(PtrIncr, MVT::i32));
1206 Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT,
1208 DAG.getTargetConstant(Channel, MVT::i32),
1211 for (unsigned i = NumElemVT; i < 4; ++i) {
1212 Loads[i] = DAG.getUNDEF(ElemVT);
1214 EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, 4);
1215 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads, 4);
1217 LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
1219 DAG.getTargetConstant(0, MVT::i32), // Channel
1224 Ops[0] = LoweredLoad;
1227 return DAG.getMergeValues(Ops, 2, DL);
1230 /// XXX Only kernel functions are supported, so we can assume for now that
1231 /// every function is a kernel function, but in the future we should use
1232 /// separate calling conventions for kernel and non-kernel functions.
1233 SDValue R600TargetLowering::LowerFormalArguments(
1235 CallingConv::ID CallConv,
1237 const SmallVectorImpl<ISD::InputArg> &Ins,
1238 SDLoc DL, SelectionDAG &DAG,
1239 SmallVectorImpl<SDValue> &InVals) const {
1240 SmallVector<CCValAssign, 16> ArgLocs;
1241 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1242 getTargetMachine(), ArgLocs, *DAG.getContext());
1244 AnalyzeFormalArguments(CCInfo, Ins);
1246 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1247 CCValAssign &VA = ArgLocs[i];
1248 EVT VT = VA.getLocVT();
1250 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1251 AMDGPUAS::CONSTANT_BUFFER_0);
1253 // The first 36 bytes of the input buffer contains information about
1254 // thread group and global sizes.
1255 SDValue Arg = DAG.getLoad(VT, DL, Chain,
1256 DAG.getConstant(36 + VA.getLocMemOffset(), MVT::i32),
1257 MachinePointerInfo(UndefValue::get(PtrTy)), false,
1258 false, false, 4); // 4 is the prefered alignment for
1259 // the CONSTANT memory space.
1260 InVals.push_back(Arg);
1265 EVT R600TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1266 if (!VT.isVector()) return MVT::i32;
1267 return VT.changeVectorElementTypeToInteger();
1271 CompactSwizzlableVector(SelectionDAG &DAG, SDValue VectorEntry,
1272 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1273 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1274 assert(RemapSwizzle.empty());
1275 SDValue NewBldVec[4] = {
1276 VectorEntry.getOperand(0),
1277 VectorEntry.getOperand(1),
1278 VectorEntry.getOperand(2),
1279 VectorEntry.getOperand(3)
1282 for (unsigned i = 0; i < 4; i++) {
1283 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(NewBldVec[i])) {
1285 RemapSwizzle[i] = 4; // SEL_0
1286 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1287 } else if (C->isExactlyValue(1.0)) {
1288 RemapSwizzle[i] = 5; // SEL_1
1289 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1293 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1295 for (unsigned j = 0; j < i; j++) {
1296 if (NewBldVec[i] == NewBldVec[j]) {
1297 NewBldVec[i] = DAG.getUNDEF(NewBldVec[i].getValueType());
1298 RemapSwizzle[i] = j;
1304 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1305 VectorEntry.getValueType(), NewBldVec, 4);
1308 static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
1309 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1310 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1311 assert(RemapSwizzle.empty());
1312 SDValue NewBldVec[4] = {
1313 VectorEntry.getOperand(0),
1314 VectorEntry.getOperand(1),
1315 VectorEntry.getOperand(2),
1316 VectorEntry.getOperand(3)
1318 bool isUnmovable[4] = { false, false, false, false };
1319 for (unsigned i = 0; i < 4; i++)
1320 RemapSwizzle[i] = i;
1322 for (unsigned i = 0; i < 4; i++) {
1323 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1324 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1326 if (!isUnmovable[Idx]) {
1328 std::swap(NewBldVec[Idx], NewBldVec[i]);
1329 std::swap(RemapSwizzle[RemapSwizzle[Idx]], RemapSwizzle[RemapSwizzle[i]]);
1331 isUnmovable[Idx] = true;
1335 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1336 VectorEntry.getValueType(), NewBldVec, 4);
1340 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector,
1341 SDValue Swz[4], SelectionDAG &DAG) const {
1342 assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR);
1343 // Old -> New swizzle values
1344 DenseMap<unsigned, unsigned> SwizzleRemap;
1346 BuildVector = CompactSwizzlableVector(DAG, BuildVector, SwizzleRemap);
1347 for (unsigned i = 0; i < 4; i++) {
1348 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1349 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1350 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1353 SwizzleRemap.clear();
1354 BuildVector = ReorganizeVector(DAG, BuildVector, SwizzleRemap);
1355 for (unsigned i = 0; i < 4; i++) {
1356 unsigned Idx = dyn_cast<ConstantSDNode>(Swz[i])->getZExtValue();
1357 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1358 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1365 //===----------------------------------------------------------------------===//
1366 // Custom DAG Optimizations
1367 //===----------------------------------------------------------------------===//
1369 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
1370 DAGCombinerInfo &DCI) const {
1371 SelectionDAG &DAG = DCI.DAG;
1373 switch (N->getOpcode()) {
1374 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1375 case ISD::FP_ROUND: {
1376 SDValue Arg = N->getOperand(0);
1377 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1378 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), N->getValueType(0),
1384 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1385 // (i32 select_cc f32, f32, -1, 0 cc)
1387 // Mesa's GLSL frontend generates the above pattern a lot and we can lower
1388 // this to one of the SET*_DX10 instructions.
1389 case ISD::FP_TO_SINT: {
1390 SDValue FNeg = N->getOperand(0);
1391 if (FNeg.getOpcode() != ISD::FNEG) {
1394 SDValue SelectCC = FNeg.getOperand(0);
1395 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1396 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1397 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
1398 !isHWTrueValue(SelectCC.getOperand(2)) ||
1399 !isHWFalseValue(SelectCC.getOperand(3))) {
1403 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
1404 SelectCC.getOperand(0), // LHS
1405 SelectCC.getOperand(1), // RHS
1406 DAG.getConstant(-1, MVT::i32), // True
1407 DAG.getConstant(0, MVT::i32), // Flase
1408 SelectCC.getOperand(4)); // CC
1412 // Extract_vec (Build_vector) generated by custom lowering
1413 // also needs to be customly combined
1414 case ISD::EXTRACT_VECTOR_ELT: {
1415 SDValue Arg = N->getOperand(0);
1416 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1417 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1418 unsigned Element = Const->getZExtValue();
1419 return Arg->getOperand(Element);
1422 if (Arg.getOpcode() == ISD::BITCAST &&
1423 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
1424 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1425 unsigned Element = Const->getZExtValue();
1426 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getVTList(),
1427 Arg->getOperand(0).getOperand(Element));
1432 case ISD::SELECT_CC: {
1433 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1434 // selectcc x, y, a, b, inv(cc)
1436 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
1437 // selectcc x, y, a, b, cc
1438 SDValue LHS = N->getOperand(0);
1439 if (LHS.getOpcode() != ISD::SELECT_CC) {
1443 SDValue RHS = N->getOperand(1);
1444 SDValue True = N->getOperand(2);
1445 SDValue False = N->getOperand(3);
1446 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1448 if (LHS.getOperand(2).getNode() != True.getNode() ||
1449 LHS.getOperand(3).getNode() != False.getNode() ||
1450 RHS.getNode() != False.getNode()) {
1455 default: return SDValue();
1456 case ISD::SETNE: return LHS;
1458 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
1459 LHSCC = ISD::getSetCCInverse(LHSCC,
1460 LHS.getOperand(0).getValueType().isInteger());
1461 return DAG.getSelectCC(SDLoc(N),
1470 case AMDGPUISD::EXPORT: {
1471 SDValue Arg = N->getOperand(1);
1472 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1475 SDValue NewArgs[8] = {
1476 N->getOperand(0), // Chain
1478 N->getOperand(2), // ArrayBase
1479 N->getOperand(3), // Type
1480 N->getOperand(4), // SWZ_X
1481 N->getOperand(5), // SWZ_Y
1482 N->getOperand(6), // SWZ_Z
1483 N->getOperand(7) // SWZ_W
1486 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG);
1487 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs, 8);
1489 case AMDGPUISD::TEXTURE_FETCH: {
1490 SDValue Arg = N->getOperand(1);
1491 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1494 SDValue NewArgs[19] = {
1515 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG);
1516 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, SDLoc(N), N->getVTList(),