1 //===- R600MCCodeEmitter.cpp - Code Emitter for R600->Cayman GPU families -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 /// This code emitter outputs bytecode that is understood by the r600g driver
13 /// in the Mesa [1] project. The bytecode is very similar to the hardware's ISA,
14 /// but it still needs to be run through a finalizer in order to be executed
17 /// [1] http://www.mesa3d.org/
19 //===----------------------------------------------------------------------===//
21 #include "R600Defines.h"
22 #include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
23 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
24 #include "llvm/MC/MCCodeEmitter.h"
25 #include "llvm/MC/MCContext.h"
26 #include "llvm/MC/MCInst.h"
27 #include "llvm/MC/MCInstrInfo.h"
28 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/MC/MCSubtargetInfo.h"
30 #include "llvm/Support/raw_ostream.h"
33 #define SRC_BYTE_COUNT 11
34 #define DST_BYTE_COUNT 5
40 class R600MCCodeEmitter : public AMDGPUMCCodeEmitter {
41 R600MCCodeEmitter(const R600MCCodeEmitter &) LLVM_DELETED_FUNCTION;
42 void operator=(const R600MCCodeEmitter &) LLVM_DELETED_FUNCTION;
43 const MCInstrInfo &MCII;
44 const MCRegisterInfo &MRI;
45 const MCSubtargetInfo &STI;
50 R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
51 const MCSubtargetInfo &sti, MCContext &ctx)
52 : MCII(mcii), MRI(mri), STI(sti), Ctx(ctx) { }
54 /// \brief Encode the instruction and write it to the OS.
55 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
56 SmallVectorImpl<MCFixup> &Fixups) const;
58 /// \returns the encoding for an MCOperand.
59 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
60 SmallVectorImpl<MCFixup> &Fixups) const;
63 void EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
64 raw_ostream &OS) const;
65 void EmitSrc(const MCInst &MI, unsigned OpIdx, raw_ostream &OS) const;
66 void EmitSrcISA(const MCInst &MI, unsigned RegOpIdx, unsigned SelOpIdx,
67 raw_ostream &OS) const;
68 void EmitDst(const MCInst &MI, raw_ostream &OS) const;
69 void EmitFCInstr(const MCInst &MI, raw_ostream &OS) const;
71 void EmitNullBytes(unsigned int byteCount, raw_ostream &OS) const;
73 void EmitByte(unsigned int byte, raw_ostream &OS) const;
75 void EmitTwoBytes(uint32_t bytes, raw_ostream &OS) const;
77 void Emit(uint32_t value, raw_ostream &OS) const;
78 void Emit(uint64_t value, raw_ostream &OS) const;
80 unsigned getHWRegChan(unsigned reg) const;
81 unsigned getHWReg(unsigned regNo) const;
83 bool isFCOp(unsigned opcode) const;
84 bool isTexOp(unsigned opcode) const;
85 bool isFlagSet(const MCInst &MI, unsigned Operand, unsigned Flag) const;
89 } // End anonymous namespace
129 TEXTURE_SHADOW1D_ARRAY,
130 TEXTURE_SHADOW2D_ARRAY
133 MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
134 const MCRegisterInfo &MRI,
135 const MCSubtargetInfo &STI,
137 return new R600MCCodeEmitter(MCII, MRI, STI, Ctx);
140 void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
141 SmallVectorImpl<MCFixup> &Fixups) const {
142 if (isFCOp(MI.getOpcode())){
144 } else if (MI.getOpcode() == AMDGPU::RETURN ||
145 MI.getOpcode() == AMDGPU::BUNDLE ||
146 MI.getOpcode() == AMDGPU::KILL) {
149 switch(MI.getOpcode()) {
150 case AMDGPU::STACK_SIZE: {
151 EmitByte(MI.getOperand(0).getImm(), OS);
154 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
155 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
156 uint64_t inst = getBinaryCodeForInstr(MI, Fixups);
157 EmitByte(INSTR_NATIVE, OS);
161 case AMDGPU::CONSTANT_LOAD_eg:
162 case AMDGPU::VTX_READ_PARAM_8_eg:
163 case AMDGPU::VTX_READ_PARAM_16_eg:
164 case AMDGPU::VTX_READ_PARAM_32_eg:
165 case AMDGPU::VTX_READ_PARAM_128_eg:
166 case AMDGPU::VTX_READ_GLOBAL_8_eg:
167 case AMDGPU::VTX_READ_GLOBAL_32_eg:
168 case AMDGPU::VTX_READ_GLOBAL_128_eg:
169 case AMDGPU::TEX_VTX_CONSTBUF:
170 case AMDGPU::TEX_VTX_TEXBUF : {
171 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups);
172 uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
174 EmitByte(INSTR_VTX, OS);
175 Emit(InstWord01, OS);
180 case AMDGPU::TEX_GET_TEXTURE_RESINFO:
181 case AMDGPU::TEX_SAMPLE:
182 case AMDGPU::TEX_SAMPLE_C:
183 case AMDGPU::TEX_SAMPLE_L:
184 case AMDGPU::TEX_SAMPLE_C_L:
185 case AMDGPU::TEX_SAMPLE_LB:
186 case AMDGPU::TEX_SAMPLE_C_LB:
187 case AMDGPU::TEX_SAMPLE_G:
188 case AMDGPU::TEX_SAMPLE_C_G:
189 case AMDGPU::TEX_GET_GRADIENTS_H:
190 case AMDGPU::TEX_GET_GRADIENTS_V:
191 case AMDGPU::TEX_SET_GRADIENTS_H:
192 case AMDGPU::TEX_SET_GRADIENTS_V: {
193 unsigned Opcode = MI.getOpcode();
194 bool HasOffsets = (Opcode == AMDGPU::TEX_LD);
195 unsigned OpOffset = HasOffsets ? 3 : 0;
196 int64_t Sampler = MI.getOperand(OpOffset + 3).getImm();
197 int64_t TextureType = MI.getOperand(OpOffset + 4).getImm();
199 uint32_t SrcSelect[4] = {0, 1, 2, 3};
200 uint32_t Offsets[3] = {0, 0, 0};
201 uint64_t CoordType[4] = {1, 1, 1, 1};
204 for (unsigned i = 0; i < 3; i++) {
205 int SignedOffset = MI.getOperand(i + 2).getImm();
206 Offsets[i] = (SignedOffset & 0x1F);
210 if (TextureType == TEXTURE_RECT ||
211 TextureType == TEXTURE_SHADOWRECT) {
212 CoordType[ELEMENT_X] = 0;
213 CoordType[ELEMENT_Y] = 0;
216 if (TextureType == TEXTURE_1D_ARRAY ||
217 TextureType == TEXTURE_SHADOW1D_ARRAY) {
218 if (Opcode == AMDGPU::TEX_SAMPLE_C_L ||
219 Opcode == AMDGPU::TEX_SAMPLE_C_LB) {
220 CoordType[ELEMENT_Y] = 0;
222 CoordType[ELEMENT_Z] = 0;
223 SrcSelect[ELEMENT_Z] = ELEMENT_Y;
225 } else if (TextureType == TEXTURE_2D_ARRAY ||
226 TextureType == TEXTURE_SHADOW2D_ARRAY) {
227 CoordType[ELEMENT_Z] = 0;
231 if ((TextureType == TEXTURE_SHADOW1D ||
232 TextureType == TEXTURE_SHADOW2D ||
233 TextureType == TEXTURE_SHADOWRECT ||
234 TextureType == TEXTURE_SHADOW1D_ARRAY) &&
235 Opcode != AMDGPU::TEX_SAMPLE_C_L &&
236 Opcode != AMDGPU::TEX_SAMPLE_C_LB) {
237 SrcSelect[ELEMENT_W] = ELEMENT_Z;
240 uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups) |
241 CoordType[ELEMENT_X] << 60 | CoordType[ELEMENT_Y] << 61 |
242 CoordType[ELEMENT_Z] << 62 | CoordType[ELEMENT_W] << 63;
243 uint32_t Word2 = Sampler << 15 | SrcSelect[ELEMENT_X] << 20 |
244 SrcSelect[ELEMENT_Y] << 23 | SrcSelect[ELEMENT_Z] << 26 |
245 SrcSelect[ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 |
248 EmitByte(INSTR_TEX, OS);
254 case AMDGPU::CF_ALU_PUSH_BEFORE: {
255 uint64_t Inst = getBinaryCodeForInstr(MI, Fixups);
256 EmitByte(INSTR_CFALU, OS);
260 case AMDGPU::CF_TC_EG:
261 case AMDGPU::CF_VC_EG:
262 case AMDGPU::CF_CALL_FS_EG:
263 case AMDGPU::CF_TC_R600:
264 case AMDGPU::CF_VC_R600:
265 case AMDGPU::CF_CALL_FS_R600:
267 case AMDGPU::WHILE_LOOP_EG:
268 case AMDGPU::END_LOOP_EG:
269 case AMDGPU::LOOP_BREAK_EG:
270 case AMDGPU::CF_CONTINUE_EG:
271 case AMDGPU::CF_JUMP_EG:
272 case AMDGPU::CF_ELSE_EG:
274 case AMDGPU::WHILE_LOOP_R600:
275 case AMDGPU::END_LOOP_R600:
276 case AMDGPU::LOOP_BREAK_R600:
277 case AMDGPU::CF_CONTINUE_R600:
278 case AMDGPU::CF_JUMP_R600:
279 case AMDGPU::CF_ELSE_R600:
280 case AMDGPU::POP_R600:
281 case AMDGPU::EG_ExportSwz:
282 case AMDGPU::R600_ExportSwz:
283 case AMDGPU::EG_ExportBuf:
284 case AMDGPU::R600_ExportBuf: {
285 uint64_t Inst = getBinaryCodeForInstr(MI, Fixups);
286 EmitByte(INSTR_NATIVE, OS);
291 EmitALUInstr(MI, Fixups, OS);
297 void R600MCCodeEmitter::EmitALUInstr(const MCInst &MI,
298 SmallVectorImpl<MCFixup> &Fixups,
299 raw_ostream &OS) const {
300 const MCInstrDesc &MCDesc = MCII.get(MI.getOpcode());
302 // Emit instruction type
303 EmitByte(INSTR_ALU, OS);
305 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups);
307 //older alu have different encoding for instructions with one or two src
309 if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
310 !(MCDesc.TSFlags & R600_InstFlag::OP3)) {
311 uint64_t ISAOpCode = InstWord01 & (0x3FFULL << 39);
312 InstWord01 &= ~(0x3FFULL << 39);
313 InstWord01 |= ISAOpCode << 1;
316 unsigned SrcNum = MCDesc.TSFlags & R600_InstFlag::OP3 ? 3 :
317 MCDesc.TSFlags & R600_InstFlag::OP2 ? 2 : 1;
319 EmitByte(SrcNum, OS);
321 const unsigned SrcOps[3][2] = {
322 {R600Operands::SRC0, R600Operands::SRC0_SEL},
323 {R600Operands::SRC1, R600Operands::SRC1_SEL},
324 {R600Operands::SRC2, R600Operands::SRC2_SEL}
327 for (unsigned SrcIdx = 0; SrcIdx < SrcNum; ++SrcIdx) {
328 unsigned RegOpIdx = R600Operands::ALUOpTable[SrcNum-1][SrcOps[SrcIdx][0]];
329 unsigned SelOpIdx = R600Operands::ALUOpTable[SrcNum-1][SrcOps[SrcIdx][1]];
330 EmitSrcISA(MI, RegOpIdx, SelOpIdx, OS);
333 Emit(InstWord01, OS);
337 void R600MCCodeEmitter::EmitSrc(const MCInst &MI, unsigned OpIdx,
338 raw_ostream &OS) const {
339 const MCOperand &MO = MI.getOperand(OpIdx);
345 // Emit the source select (2 bytes). For GPRs, this is the register index.
346 // For other potential instruction operands, (e.g. constant registers) the
347 // value of the source select is defined in the r600isa docs.
349 unsigned reg = MO.getReg();
350 EmitTwoBytes(getHWReg(reg), OS);
351 if (reg == AMDGPU::ALU_LITERAL_X) {
352 unsigned ImmOpIndex = MI.getNumOperands() - 1;
353 MCOperand ImmOp = MI.getOperand(ImmOpIndex);
354 if (ImmOp.isFPImm()) {
355 Value.f = ImmOp.getFPImm();
357 assert(ImmOp.isImm());
358 Value.i = ImmOp.getImm();
362 // XXX: Handle other operand types.
366 // Emit the source channel (1 byte)
368 EmitByte(getHWRegChan(MO.getReg()), OS);
373 // XXX: Emit isNegated (1 byte)
374 if ((!(isFlagSet(MI, OpIdx, MO_FLAG_ABS)))
375 && (isFlagSet(MI, OpIdx, MO_FLAG_NEG) ||
377 (MO.getReg() == AMDGPU::NEG_ONE || MO.getReg() == AMDGPU::NEG_HALF)))){
383 // Emit isAbsolute (1 byte)
384 if (isFlagSet(MI, OpIdx, MO_FLAG_ABS)) {
390 // XXX: Emit relative addressing mode (1 byte)
393 // Emit kc_bank, This will be adjusted later by r600_asm
396 // Emit the literal value, if applicable (4 bytes).
401 void R600MCCodeEmitter::EmitSrcISA(const MCInst &MI, unsigned RegOpIdx,
402 unsigned SelOpIdx, raw_ostream &OS) const {
403 const MCOperand &RegMO = MI.getOperand(RegOpIdx);
404 const MCOperand &SelMO = MI.getOperand(SelOpIdx);
410 InlineConstant.i = 0;
411 // Emit source type (1 byte) and source select (4 bytes). For GPRs type is 0
412 // and select is 0 (GPR index is encoded in the instr encoding. For constants
413 // type is 1 and select is the original const select passed from the driver.
414 unsigned Reg = RegMO.getReg();
415 if (Reg == AMDGPU::ALU_CONST) {
417 uint32_t Sel = SelMO.getImm();
421 Emit((uint32_t)0, OS);
424 if (Reg == AMDGPU::ALU_LITERAL_X) {
425 unsigned ImmOpIndex = MI.getNumOperands() - 1;
426 MCOperand ImmOp = MI.getOperand(ImmOpIndex);
427 if (ImmOp.isFPImm()) {
428 InlineConstant.f = ImmOp.getFPImm();
430 assert(ImmOp.isImm());
431 InlineConstant.i = ImmOp.getImm();
435 // Emit the literal value, if applicable (4 bytes).
436 Emit(InlineConstant.i, OS);
439 void R600MCCodeEmitter::EmitFCInstr(const MCInst &MI, raw_ostream &OS) const {
441 // Emit instruction type
442 EmitByte(INSTR_FC, OS);
445 unsigned NumOperands = MI.getNumOperands();
446 if (NumOperands > 0) {
447 assert(NumOperands == 1);
450 EmitNullBytes(SRC_BYTE_COUNT, OS);
453 // Emit FC Instruction
455 switch (MI.getOpcode()) {
456 case AMDGPU::PREDICATED_BREAK:
457 instr = FC_BREAK_PREDICATE;
459 case AMDGPU::CONTINUE:
462 case AMDGPU::IF_PREDICATE_SET:
463 instr = FC_IF_PREDICATE;
471 case AMDGPU::ENDLOOP:
474 case AMDGPU::WHILELOOP:
484 void R600MCCodeEmitter::EmitNullBytes(unsigned int ByteCount,
485 raw_ostream &OS) const {
487 for (unsigned int i = 0; i < ByteCount; i++) {
492 void R600MCCodeEmitter::EmitByte(unsigned int Byte, raw_ostream &OS) const {
493 OS.write((uint8_t) Byte & 0xff);
496 void R600MCCodeEmitter::EmitTwoBytes(unsigned int Bytes,
497 raw_ostream &OS) const {
498 OS.write((uint8_t) (Bytes & 0xff));
499 OS.write((uint8_t) ((Bytes >> 8) & 0xff));
502 void R600MCCodeEmitter::Emit(uint32_t Value, raw_ostream &OS) const {
503 for (unsigned i = 0; i < 4; i++) {
504 OS.write((uint8_t) ((Value >> (8 * i)) & 0xff));
508 void R600MCCodeEmitter::Emit(uint64_t Value, raw_ostream &OS) const {
509 for (unsigned i = 0; i < 8; i++) {
510 EmitByte((Value >> (8 * i)) & 0xff, OS);
514 unsigned R600MCCodeEmitter::getHWRegChan(unsigned reg) const {
515 return MRI.getEncodingValue(reg) >> HW_CHAN_SHIFT;
518 unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const {
519 return MRI.getEncodingValue(RegNo) & HW_REG_MASK;
522 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
524 SmallVectorImpl<MCFixup> &Fixup) const {
526 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) {
527 return MRI.getEncodingValue(MO.getReg());
529 return getHWReg(MO.getReg());
531 } else if (MO.isImm()) {
539 //===----------------------------------------------------------------------===//
540 // Encoding helper functions
541 //===----------------------------------------------------------------------===//
543 bool R600MCCodeEmitter::isFCOp(unsigned opcode) const {
545 default: return false;
546 case AMDGPU::PREDICATED_BREAK:
547 case AMDGPU::CONTINUE:
548 case AMDGPU::IF_PREDICATE_SET:
551 case AMDGPU::ENDLOOP:
552 case AMDGPU::WHILELOOP:
557 bool R600MCCodeEmitter::isTexOp(unsigned opcode) const {
559 default: return false;
561 case AMDGPU::TEX_GET_TEXTURE_RESINFO:
562 case AMDGPU::TEX_SAMPLE:
563 case AMDGPU::TEX_SAMPLE_C:
564 case AMDGPU::TEX_SAMPLE_L:
565 case AMDGPU::TEX_SAMPLE_C_L:
566 case AMDGPU::TEX_SAMPLE_LB:
567 case AMDGPU::TEX_SAMPLE_C_LB:
568 case AMDGPU::TEX_SAMPLE_G:
569 case AMDGPU::TEX_SAMPLE_C_G:
570 case AMDGPU::TEX_GET_GRADIENTS_H:
571 case AMDGPU::TEX_GET_GRADIENTS_V:
572 case AMDGPU::TEX_SET_GRADIENTS_H:
573 case AMDGPU::TEX_SET_GRADIENTS_V:
578 bool R600MCCodeEmitter::isFlagSet(const MCInst &MI, unsigned Operand,
579 unsigned Flag) const {
580 const MCInstrDesc &MCDesc = MCII.get(MI.getOpcode());
581 unsigned FlagIndex = GET_FLAG_OPERAND_IDX(MCDesc.TSFlags);
582 if (FlagIndex == 0) {
585 assert(MI.getOperand(FlagIndex).isImm());
586 return !!((MI.getOperand(FlagIndex).getImm() >>
587 (NUM_MO_FLAGS * Operand)) & Flag);
590 #include "AMDGPUGenMCCodeEmitter.inc"