1 //===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
14 #include "AMDGPUInstrInfo.h"
15 #include "AMDGPUISelLowering.h" // For AMDGPUISD
16 #include "AMDGPURegisterInfo.h"
17 #include "AMDILDevices.h"
18 #include "R600InstrInfo.h"
19 #include "llvm/ADT/ValueMap.h"
20 #include "llvm/CodeGen/PseudoSourceValue.h"
21 #include "llvm/CodeGen/SelectionDAGISel.h"
22 #include "llvm/Support/Compiler.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
29 //===----------------------------------------------------------------------===//
30 // Instruction Selector Implementation
31 //===----------------------------------------------------------------------===//
34 /// AMDGPU specific code to select AMDGPU machine instructions for
35 /// SelectionDAG operations.
36 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
37 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
38 // make the right decision when generating code for different targets.
39 const AMDGPUSubtarget &Subtarget;
41 AMDGPUDAGToDAGISel(TargetMachine &TM);
42 virtual ~AMDGPUDAGToDAGISel();
44 SDNode *Select(SDNode *N);
45 virtual const char *getPassName() const;
48 inline SDValue getSmallIPtrImm(unsigned Imm);
49 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
51 // Complex pattern selectors
52 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
53 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
54 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
56 static bool checkType(const Value *ptr, unsigned int addrspace);
57 static const Value *getBasePointerValue(const Value *V);
59 static bool isGlobalStore(const StoreSDNode *N);
60 static bool isPrivateStore(const StoreSDNode *N);
61 static bool isLocalStore(const StoreSDNode *N);
62 static bool isRegionStore(const StoreSDNode *N);
64 static bool isCPLoad(const LoadSDNode *N);
65 static bool isConstantLoad(const LoadSDNode *N, int cbID);
66 static bool isGlobalLoad(const LoadSDNode *N);
67 static bool isParamLoad(const LoadSDNode *N);
68 static bool isPrivateLoad(const LoadSDNode *N);
69 static bool isLocalLoad(const LoadSDNode *N);
70 static bool isRegionLoad(const LoadSDNode *N);
72 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
73 bool SelectGlobalValueVariableOffset(SDValue Addr,
74 SDValue &BaseReg, SDValue& Offset);
75 bool SelectADDR8BitOffset(SDValue Addr, SDValue& Base, SDValue& Offset);
76 bool SelectADDRReg(SDValue Addr, SDValue& Base, SDValue& Offset);
77 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
79 // Include the pieces autogenerated from the target description.
80 #include "AMDGPUGenDAGISel.inc"
82 } // end anonymous namespace
84 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
85 // DAG, ready for instruction scheduling.
86 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM
88 return new AMDGPUDAGToDAGISel(TM);
91 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM
93 : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>()) {
96 AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
99 SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
100 return CurDAG->getTargetConstant(Imm, MVT::i32);
103 bool AMDGPUDAGToDAGISel::SelectADDRParam(
104 SDValue Addr, SDValue& R1, SDValue& R2) {
106 if (Addr.getOpcode() == ISD::FrameIndex) {
107 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
108 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
109 R2 = CurDAG->getTargetConstant(0, MVT::i32);
112 R2 = CurDAG->getTargetConstant(0, MVT::i32);
114 } else if (Addr.getOpcode() == ISD::ADD) {
115 R1 = Addr.getOperand(0);
116 R2 = Addr.getOperand(1);
119 R2 = CurDAG->getTargetConstant(0, MVT::i32);
124 bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
125 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
126 Addr.getOpcode() == ISD::TargetGlobalAddress) {
129 return SelectADDRParam(Addr, R1, R2);
133 bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
134 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
135 Addr.getOpcode() == ISD::TargetGlobalAddress) {
139 if (Addr.getOpcode() == ISD::FrameIndex) {
140 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
141 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
142 R2 = CurDAG->getTargetConstant(0, MVT::i64);
145 R2 = CurDAG->getTargetConstant(0, MVT::i64);
147 } else if (Addr.getOpcode() == ISD::ADD) {
148 R1 = Addr.getOperand(0);
149 R2 = Addr.getOperand(1);
152 R2 = CurDAG->getTargetConstant(0, MVT::i64);
157 SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
158 unsigned int Opc = N->getOpcode();
159 if (N->isMachineOpcode()) {
160 return NULL; // Already selected.
164 case ISD::FrameIndex: {
165 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
166 unsigned int FI = FIN->getIndex();
167 EVT OpVT = N->getValueType(0);
168 unsigned int NewOpc = AMDGPU::COPY;
169 SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);
170 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, TFI);
174 case ISD::ConstantFP:
175 case ISD::Constant: {
176 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
177 // XXX: Custom immediate lowering not implemented yet. Instead we use
178 // pseudo instructions defined in SIInstructions.td
179 if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
182 const R600InstrInfo *TII = static_cast<const R600InstrInfo*>(TM.getInstrInfo());
184 uint64_t ImmValue = 0;
185 unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
187 if (N->getOpcode() == ISD::ConstantFP) {
188 // XXX: 64-bit Immediates not supported yet
189 assert(N->getValueType(0) != MVT::f64);
191 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N);
192 APFloat Value = C->getValueAPF();
193 float FloatValue = Value.convertToFloat();
194 if (FloatValue == 0.0) {
195 ImmReg = AMDGPU::ZERO;
196 } else if (FloatValue == 0.5) {
197 ImmReg = AMDGPU::HALF;
198 } else if (FloatValue == 1.0) {
199 ImmReg = AMDGPU::ONE;
201 ImmValue = Value.bitcastToAPInt().getZExtValue();
204 // XXX: 64-bit Immediates not supported yet
205 assert(N->getValueType(0) != MVT::i64);
207 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
208 if (C->getZExtValue() == 0) {
209 ImmReg = AMDGPU::ZERO;
210 } else if (C->getZExtValue() == 1) {
211 ImmReg = AMDGPU::ONE_INT;
213 ImmValue = C->getZExtValue();
217 for (SDNode::use_iterator Use = N->use_begin(), Next = llvm::next(Use);
218 Use != SDNode::use_end(); Use = Next) {
219 Next = llvm::next(Use);
220 std::vector<SDValue> Ops;
221 for (unsigned i = 0; i < Use->getNumOperands(); ++i) {
222 Ops.push_back(Use->getOperand(i));
225 if (!Use->isMachineOpcode()) {
226 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
227 // We can only use literal constants (e.g. AMDGPU::ZERO,
228 // AMDGPU::ONE, etc) in machine opcodes.
232 if (!TII->isALUInstr(Use->getMachineOpcode())) {
236 int ImmIdx = TII->getOperandIdx(Use->getMachineOpcode(), R600Operands::IMM);
237 assert(ImmIdx != -1);
239 // subtract one from ImmIdx, because the DST operand is usually index
240 // 0 for MachineInstrs, but we have no DST in the Ops vector.
243 // Check that we aren't already using an immediate.
244 // XXX: It's possible for an instruction to have more than one
245 // immediate operand, but this is not supported yet.
246 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
247 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Use->getOperand(ImmIdx));
250 if (C->getZExtValue() != 0) {
251 // This instruction is already using an immediate.
255 // Set the immediate value
256 Ops[ImmIdx] = CurDAG->getTargetConstant(ImmValue, MVT::i32);
259 // Set the immediate register
260 Ops[Use.getOperandNo()] = CurDAG->getRegister(ImmReg, MVT::i32);
262 CurDAG->UpdateNodeOperands(*Use, Ops.data(), Use->getNumOperands());
267 SDNode *Result = SelectCode(N);
269 // Fold operands of selected node
271 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
272 if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
273 const R600InstrInfo *TII =
274 static_cast<const R600InstrInfo*>(TM.getInstrInfo());
275 if (Result && TII->isALUInstr(Result->getMachineOpcode())) {
276 bool IsModified = false;
278 std::vector<SDValue> Ops;
279 for(SDNode::op_iterator I = Result->op_begin(), E = Result->op_end();
282 IsModified = FoldOperands(Result->getMachineOpcode(), TII, Ops);
284 Result = CurDAG->MorphNodeTo(Result, Result->getOpcode(),
285 Result->getVTList(), Ops.data(), Ops.size());
287 } while (IsModified);
294 bool AMDGPUDAGToDAGISel::FoldOperands(unsigned Opcode,
295 const R600InstrInfo *TII, std::vector<SDValue> &Ops) {
297 TII->getOperandIdx(Opcode, R600Operands::SRC0),
298 TII->getOperandIdx(Opcode, R600Operands::SRC1),
299 TII->getOperandIdx(Opcode, R600Operands::SRC2)
302 TII->getOperandIdx(Opcode, R600Operands::SRC0_SEL),
303 TII->getOperandIdx(Opcode, R600Operands::SRC1_SEL),
304 TII->getOperandIdx(Opcode, R600Operands::SRC2_SEL)
306 for (unsigned i = 0; i < 3; i++) {
307 if (OperandIdx[i] < 0)
309 SDValue Operand = Ops[OperandIdx[i] - 1];
310 switch (Operand.getOpcode()) {
311 case AMDGPUISD::CONST_ADDRESS: {
313 if (!Operand.getValueType().isVector() &&
314 SelectGlobalValueConstantOffset(Operand.getOperand(0), CstOffset)) {
315 Ops[OperandIdx[i] - 1] = CurDAG->getRegister(AMDGPU::ALU_CONST, MVT::f32);
316 Ops[SelIdx[i] - 1] = CstOffset;
322 Ops[OperandIdx[i] - 1] = Operand.getOperand(0);
331 bool AMDGPUDAGToDAGISel::checkType(const Value *ptr, unsigned int addrspace) {
335 Type *ptrType = ptr->getType();
336 return dyn_cast<PointerType>(ptrType)->getAddressSpace() == addrspace;
339 const Value * AMDGPUDAGToDAGISel::getBasePointerValue(const Value *V) {
343 const Value *ret = NULL;
344 ValueMap<const Value *, bool> ValueBitMap;
345 std::queue<const Value *, std::list<const Value *> > ValueQueue;
347 while (!ValueQueue.empty()) {
348 V = ValueQueue.front();
349 if (ValueBitMap.find(V) == ValueBitMap.end()) {
350 ValueBitMap[V] = true;
351 if (dyn_cast<Argument>(V) && dyn_cast<PointerType>(V->getType())) {
354 } else if (dyn_cast<GlobalVariable>(V)) {
357 } else if (dyn_cast<Constant>(V)) {
358 const ConstantExpr *CE = dyn_cast<ConstantExpr>(V);
360 ValueQueue.push(CE->getOperand(0));
362 } else if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
365 } else if (const Instruction *I = dyn_cast<Instruction>(V)) {
366 uint32_t numOps = I->getNumOperands();
367 for (uint32_t x = 0; x < numOps; ++x) {
368 ValueQueue.push(I->getOperand(x));
371 assert(!"Found a Value that we didn't know how to handle!");
379 bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
380 return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
383 bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
384 return (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
385 && !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
386 && !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS));
389 bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
390 return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
393 bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
394 return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
397 bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int cbID) {
398 if (checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)) {
401 MachineMemOperand *MMO = N->getMemOperand();
402 const Value *V = MMO->getValue();
403 const Value *BV = getBasePointerValue(V);
406 && ((V && dyn_cast<GlobalValue>(V))
407 || (BV && dyn_cast<GlobalValue>(
408 getBasePointerValue(MMO->getValue()))))) {
409 return checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS);
415 bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) {
416 return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
419 bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) {
420 return checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS);
423 bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) {
424 return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
427 bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) {
428 return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
431 bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) {
432 MachineMemOperand *MMO = N->getMemOperand();
433 if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
435 const Value *V = MMO->getValue();
436 const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V);
437 if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
445 bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) {
446 if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
447 // Check to make sure we are not a constant pool load or a constant load
448 // that is marked as a private load
449 if (isCPLoad(N) || isConstantLoad(N, -1)) {
453 if (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
454 && !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
455 && !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS)
456 && !checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)
457 && !checkType(N->getSrcValue(), AMDGPUAS::PARAM_D_ADDRESS)
458 && !checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS)) {
464 const char *AMDGPUDAGToDAGISel::getPassName() const {
465 return "AMDGPU DAG->DAG Pattern Instruction Selection";
473 ///==== AMDGPU Functions ====///
475 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
477 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
478 IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, true);
484 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
485 SDValue& BaseReg, SDValue &Offset) {
486 if (!dyn_cast<ConstantSDNode>(Addr)) {
488 Offset = CurDAG->getIntPtrConstant(0, true);
494 bool AMDGPUDAGToDAGISel::SelectADDR8BitOffset(SDValue Addr, SDValue& Base,
496 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
497 Addr.getOpcode() == ISD::TargetGlobalAddress) {
502 if (Addr.getOpcode() == ISD::ADD) {
505 // Find the base ptr and the offset
506 for (unsigned i = 0; i < Addr.getNumOperands(); i++) {
507 SDValue Arg = Addr.getOperand(i);
508 ConstantSDNode * OffsetNode = dyn_cast<ConstantSDNode>(Arg);
509 // This arg isn't a constant so it must be the base PTR.
511 Base = Addr.getOperand(i);
514 // Check if the constant argument fits in 8-bits. The offset is in bytes
515 // so we need to convert it to dwords.
516 if (isUInt<8>(OffsetNode->getZExtValue() >> 2)) {
518 Offset = CurDAG->getTargetConstant(OffsetNode->getZExtValue() >> 2,
525 // Default case, no offset
527 Offset = CurDAG->getTargetConstant(0, MVT::i32);
531 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
533 ConstantSDNode * IMMOffset;
535 if (Addr.getOpcode() == ISD::ADD
536 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
537 && isInt<16>(IMMOffset->getZExtValue())) {
539 Base = Addr.getOperand(0);
540 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
542 // If the pointer address is constant, we can move it to the offset field.
543 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
544 && isInt<16>(IMMOffset->getZExtValue())) {
545 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
546 CurDAG->getEntryNode().getDebugLoc(),
547 AMDGPU::ZERO, MVT::i32);
548 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
552 // Default case, no offset
554 Offset = CurDAG->getTargetConstant(0, MVT::i32);
558 bool AMDGPUDAGToDAGISel::SelectADDRReg(SDValue Addr, SDValue& Base,
560 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
561 Addr.getOpcode() == ISD::TargetGlobalAddress ||
562 Addr.getOpcode() != ISD::ADD) {
566 Base = Addr.getOperand(0);
567 Offset = Addr.getOperand(1);