1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information needed to emit code for R600 and SI GPUs.
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUTargetMachine.h"
18 #include "R600ISelLowering.h"
19 #include "R600InstrInfo.h"
20 #include "R600MachineScheduler.h"
21 #include "SIISelLowering.h"
22 #include "SIInstrInfo.h"
23 #include "llvm/Analysis/Passes.h"
24 #include "llvm/Analysis/Verifier.h"
25 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/PassManager.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Support/raw_os_ostream.h"
32 #include "llvm/Transforms/IPO.h"
33 #include "llvm/Transforms/Scalar.h"
34 #include <llvm/CodeGen/Passes.h>
39 extern "C" void LLVMInitializeR600Target() {
40 // Register the target
41 RegisterTargetMachine<AMDGPUTargetMachine> X(TheAMDGPUTarget);
44 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
45 return new ScheduleDAGMI(C, new R600SchedStrategy());
48 static MachineSchedRegistry
49 SchedCustomRegistry("r600", "Run R600's custom scheduler",
50 createR600MachineScheduler);
52 static std::string computeDataLayout(const AMDGPUSubtarget &ST) {
53 std::string DataLayout = std::string(
55 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
56 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
57 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
62 DataLayout.append("-f64:64:64");
65 DataLayout.append("-p:64:64:64");
67 DataLayout.append("-p:32:32:32");
69 if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
70 DataLayout.append("-p3:32:32:32");
75 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
76 StringRef CPU, StringRef FS,
77 TargetOptions Options,
78 Reloc::Model RM, CodeModel::Model CM,
79 CodeGenOpt::Level OptLevel
82 LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
83 Subtarget(TT, CPU, FS),
84 Layout(computeDataLayout(Subtarget)),
85 FrameLowering(TargetFrameLowering::StackGrowsUp,
86 64 * 16 // Maximum stack alignment (long16)
89 InstrItins(&Subtarget.getInstrItineraryData()) {
90 // TLInfo uses InstrInfo so it must be initialized after.
91 if (Subtarget.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
92 InstrInfo.reset(new R600InstrInfo(*this));
93 TLInfo.reset(new R600TargetLowering(*this));
95 InstrInfo.reset(new SIInstrInfo(*this));
96 TLInfo.reset(new SITargetLowering(*this));
98 setRequiresStructuredCFG(true);
102 AMDGPUTargetMachine::~AMDGPUTargetMachine() {
106 class AMDGPUPassConfig : public TargetPassConfig {
108 AMDGPUPassConfig(AMDGPUTargetMachine *TM, PassManagerBase &PM)
109 : TargetPassConfig(TM, PM) {}
111 AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
112 return getTM<AMDGPUTargetMachine>();
115 virtual ScheduleDAGInstrs *
116 createMachineScheduler(MachineSchedContext *C) const {
117 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
118 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
119 return createR600MachineScheduler(C);
123 virtual bool addPreISel();
124 virtual bool addInstSelector();
125 virtual bool addPreRegAlloc();
126 virtual bool addPostRegAlloc();
127 virtual bool addPreSched2();
128 virtual bool addPreEmitPass();
130 } // End of anonymous namespace
132 TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) {
133 return new AMDGPUPassConfig(this, PM);
136 //===----------------------------------------------------------------------===//
137 // AMDGPU Analysis Pass Setup
138 //===----------------------------------------------------------------------===//
140 void AMDGPUTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
141 // Add first the target-independent BasicTTI pass, then our AMDGPU pass. This
142 // allows the AMDGPU pass to delegate to the target independent layer when
144 PM.add(createBasicTargetTransformInfoPass(this));
145 PM.add(createAMDGPUTargetTransformInfoPass(this));
149 AMDGPUPassConfig::addPreISel() {
150 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
151 addPass(createFlattenCFGPass());
152 if (ST.IsIRStructurizerEnabled())
153 addPass(createStructurizeCFGPass());
154 if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
155 addPass(createSinkingPass());
156 addPass(createSITypeRewriter());
157 addPass(createSIAnnotateControlFlowPass());
159 addPass(createR600TextureIntrinsicsReplacer());
164 bool AMDGPUPassConfig::addInstSelector() {
165 addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
169 bool AMDGPUPassConfig::addPreRegAlloc() {
170 addPass(createAMDGPUConvertToISAPass(*TM));
171 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
173 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
174 addPass(createR600VectorRegMerger(*TM));
176 addPass(createSIFixSGPRCopiesPass(*TM));
181 bool AMDGPUPassConfig::addPostRegAlloc() {
182 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
184 if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
185 addPass(createSIInsertWaits(*TM));
190 bool AMDGPUPassConfig::addPreSched2() {
191 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
193 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
194 addPass(createR600EmitClauseMarkers());
195 if (ST.isIfCvtEnabled())
196 addPass(&IfConverterID);
197 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
198 addPass(createR600ClauseMergePass(*TM));
202 bool AMDGPUPassConfig::addPreEmitPass() {
203 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
204 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
205 addPass(createAMDGPUCFGStructurizerPass());
206 addPass(createR600ExpandSpecialInstrsPass(*TM));
207 addPass(&FinalizeMachineBundlesID);
208 addPass(createR600Packetizer(*TM));
209 addPass(createR600ControlFlowFinalizer(*TM));
211 addPass(createSILowerControlFlowPass(*TM));