1 //===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains DAG node defintions for the AMDGPU target.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // AMDGPU DAG Profiles
16 //===----------------------------------------------------------------------===//
18 def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
19 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
22 def AMDGPUTrigPreOp : SDTypeProfile<1, 2,
23 [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
26 def AMDGPULdExpOp : SDTypeProfile<1, 2,
27 [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
30 def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
31 [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
34 //===----------------------------------------------------------------------===//
38 // This argument to this node is a dword address.
39 def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
41 def AMDGPUcos : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
42 def AMDGPUsin : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
45 def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
48 def AMDGPUrcp : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
50 // out = 1.0 / sqrt(a)
51 def AMDGPUrsq : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
53 // out = 1.0 / sqrt(a)
54 def AMDGPUrsq_legacy : SDNode<"AMDGPUISD::RSQ_LEGACY", SDTFPUnaryOp>;
56 // out = 1.0 / sqrt(a) result clamped to +/- max_float.
57 def AMDGPUrsq_clamped : SDNode<"AMDGPUISD::RSQ_CLAMPED", SDTFPUnaryOp>;
59 def AMDGPUldexp : SDNode<"AMDGPUISD::LDEXP", AMDGPULdExpOp>;
61 // out = max(a, b) a and b are floats, where a nan comparison fails.
62 // This is not commutative because this gives the second operand:
63 // x < nan ? x : nan -> nan
64 // nan < x ? nan : x -> x
65 def AMDGPUfmax_legacy : SDNode<"AMDGPUISD::FMAX_LEGACY", SDTFPBinOp,
69 def AMDGPUclamp : SDNode<"AMDGPUISD::CLAMP", SDTFPTernaryOp, []>;
70 def AMDGPUmad : SDNode<"AMDGPUISD::MAD", SDTFPTernaryOp, []>;
72 // out = max(a, b) a and b are signed ints
73 def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp,
74 [SDNPCommutative, SDNPAssociative]
77 // out = max(a, b) a and b are unsigned ints
78 def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,
79 [SDNPCommutative, SDNPAssociative]
82 // out = min(a, b) a and b are floats, where a nan comparison fails.
83 def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp,
87 // out = min(a, b) a and b are signed ints
88 def AMDGPUsmin : SDNode<"AMDGPUISD::SMIN", SDTIntBinOp,
89 [SDNPCommutative, SDNPAssociative]
92 // out = min(a, b) a and b are unsigned ints
93 def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp,
94 [SDNPCommutative, SDNPAssociative]
97 // FIXME: TableGen doesn't like commutative instructions with more
99 // out = max(a, b, c) a, b and c are floats
100 def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp,
101 [/*SDNPCommutative, SDNPAssociative*/]
104 // out = max(a, b, c) a, b, and c are signed ints
105 def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp,
106 [/*SDNPCommutative, SDNPAssociative*/]
109 // out = max(a, b, c) a, b and c are unsigned ints
110 def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp,
111 [/*SDNPCommutative, SDNPAssociative*/]
114 // out = min(a, b, c) a, b and c are floats
115 def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp,
116 [/*SDNPCommutative, SDNPAssociative*/]
119 // out = min(a, b, c) a, b and c are signed ints
120 def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp,
121 [/*SDNPCommutative, SDNPAssociative*/]
124 // out = min(a, b) a and b are unsigned ints
125 def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp,
126 [/*SDNPCommutative, SDNPAssociative*/]
129 def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
131 def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
133 def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
135 def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
139 // urecip - This operation is a helper for integer division, it returns the
140 // result of 1 / a as a fractional unsigned integer.
141 // out = (2^32 / a) + e
142 // e is rounding error
143 def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
145 // Special case divide preop and flags.
146 def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
148 // Special case divide FMA with scale and flags (src0 = Quotient,
149 // src1 = Denominator, src2 = Numerator).
150 def AMDGPUdiv_fmas : SDNode<"AMDGPUISD::DIV_FMAS", SDTFPTernaryOp>;
152 // Single or double precision division fixup.
153 // Special case divide fixup and flags(src0 = Quotient, src1 =
154 // Denominator, src2 = Numerator).
155 def AMDGPUdiv_fixup : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;
157 // Look Up 2.0 / pi src0 with segment select src1[4:0]
158 def AMDGPUtrig_preop : SDNode<"AMDGPUISD::TRIG_PREOP", AMDGPUTrigPreOp>;
160 def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
161 SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
162 [SDNPHasChain, SDNPMayLoad]>;
164 def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
165 SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
166 [SDNPHasChain, SDNPMayStore]>;
168 // MSKOR instructions are atomic memory instructions used mainly for storing
169 // 8-bit and 16-bit values. The definition is:
171 // MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
173 // src0: vec4(src, 0, 0, mask)
174 // src1: dst - rat offset (aka pointer) in dwords
175 def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
176 SDTypeProfile<0, 2, []>,
177 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
179 def AMDGPUround : SDNode<"ISD::FROUND",
180 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
182 def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
183 def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
184 def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
185 def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
187 def AMDGPUbrev : SDNode<"AMDGPUISD::BREV", SDTIntUnaryOp>;
189 // Signed and unsigned 24-bit mulitply. The highest 8-bits are ignore when
190 // performing the mulitply. The result is a 32-bit value.
191 def AMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
194 def AMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
198 def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
201 def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
205 //===----------------------------------------------------------------------===//
206 // Flow Control Profile Types
207 //===----------------------------------------------------------------------===//
208 // Branch instruction where second and third are basic blocks
209 def SDTIL_BRCond : SDTypeProfile<0, 2, [
213 //===----------------------------------------------------------------------===//
214 // Flow Control DAG Nodes
215 //===----------------------------------------------------------------------===//
216 def IL_brcond : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
218 //===----------------------------------------------------------------------===//
219 // Call/Return DAG Nodes
220 //===----------------------------------------------------------------------===//
221 def IL_retflag : SDNode<"AMDGPUISD::RET_FLAG", SDTNone,
222 [SDNPHasChain, SDNPOptInGlue]>;