1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition of the TargetLowering class that is common
14 //===----------------------------------------------------------------------===//
16 #ifndef AMDGPUISELLOWERING_H
17 #define AMDGPUISELLOWERING_H
19 #include "llvm/Target/TargetLowering.h"
23 class AMDGPUMachineFunction;
24 class AMDGPUSubtarget;
25 class MachineRegisterInfo;
27 class AMDGPUTargetLowering : public TargetLowering {
29 const AMDGPUSubtarget *Subtarget;
32 SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
33 const SDValue &InitPtr,
35 SelectionDAG &DAG) const;
36 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
39 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
40 /// \brief Lower vector stores by merging the vector elements into an integer
41 /// of the same bitwidth.
42 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
43 /// \brief Split a vector store into multiple scalar stores.
44 /// \returns The resulting chain.
46 SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
48 SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
49 SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
51 SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
52 SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
53 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
54 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
56 SDValue ExpandSIGN_EXTEND_INREG(SDValue Op,
58 SelectionDAG &DAG) const;
59 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
62 static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
63 static EVT getEquivalentLoadRegType(LLVMContext &Context, EVT VT);
65 /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
68 /// \returns a RegisterSDNode representing Reg.
69 virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
70 const TargetRegisterClass *RC,
71 unsigned Reg, EVT VT) const;
72 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
73 SelectionDAG &DAG) const;
74 /// \brief Split a vector load into multiple scalar loads.
75 SDValue SplitVectorLoad(const SDValue &Op, SelectionDAG &DAG) const;
76 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
77 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
78 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
79 bool isHWTrueValue(SDValue Op) const;
80 bool isHWFalseValue(SDValue Op) const;
82 /// The SelectionDAGBuilder will automatically promote function arguments
83 /// with illegal types. However, this does not work for the AMDGPU targets
84 /// since the function arguments are stored in memory as these illegal types.
85 /// In order to handle this properly we need to get the origianl types sizes
86 /// from the LLVM IR Function and fixup the ISD:InputArg values before
87 /// passing them to AnalyzeFormalArguments()
88 void getOriginalFunctionArgs(SelectionDAG &DAG,
90 const SmallVectorImpl<ISD::InputArg> &Ins,
91 SmallVectorImpl<ISD::InputArg> &OrigIns) const;
92 void AnalyzeFormalArguments(CCState &State,
93 const SmallVectorImpl<ISD::InputArg> &Ins) const;
96 AMDGPUTargetLowering(TargetMachine &TM);
98 bool isFAbsFree(EVT VT) const override;
99 bool isFNegFree(EVT VT) const override;
100 bool isTruncateFree(EVT Src, EVT Dest) const override;
101 bool isTruncateFree(Type *Src, Type *Dest) const override;
103 bool isZExtFree(Type *Src, Type *Dest) const override;
104 bool isZExtFree(EVT Src, EVT Dest) const override;
106 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
108 MVT getVectorIdxTy() const override;
110 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
111 bool ShouldShrinkFPConstant(EVT VT) const override;
113 bool isLoadBitCastBeneficial(EVT, EVT) const override;
114 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
116 const SmallVectorImpl<ISD::OutputArg> &Outs,
117 const SmallVectorImpl<SDValue> &OutVals,
118 SDLoc DL, SelectionDAG &DAG) const override;
119 SDValue LowerCall(CallLoweringInfo &CLI,
120 SmallVectorImpl<SDValue> &InVals) const override;
122 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
123 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
124 void ReplaceNodeResults(SDNode * N,
125 SmallVectorImpl<SDValue> &Results,
126 SelectionDAG &DAG) const override;
128 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
129 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
130 SDValue CombineMinMax(SDNode *N, SelectionDAG &DAG) const;
131 const char* getTargetNodeName(unsigned Opcode) const override;
133 virtual SDNode *PostISelFolding(MachineSDNode *N,
134 SelectionDAG &DAG) const {
138 /// \brief Determine which of the bits specified in \p Mask are known to be
139 /// either zero or one and return them in the \p KnownZero and \p KnownOne
141 void computeKnownBitsForTargetNode(const SDValue Op,
144 const SelectionDAG &DAG,
145 unsigned Depth = 0) const override;
147 virtual unsigned ComputeNumSignBitsForTargetNode(
149 const SelectionDAG &DAG,
150 unsigned Depth = 0) const override;
153 // Functions defined in AMDILISelLowering.cpp
154 void InitAMDILLowering();
155 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
158 namespace AMDGPUISD {
162 FIRST_NUMBER = ISD::BUILTIN_OP_END,
163 CALL, // Function call based on a single integer
164 UMUL, // 32bit unsigned multiplication
165 DIV_INF, // Divide with infinity returned on zero divisor
168 // End AMDIL ISD Opcodes
182 BFE_U32, // Extract range of bits with zero extension to 32-bits.
183 BFE_I32, // Extract range of bits with sign extension to 32-bits.
184 BFI, // (src0 & src1) | (~src0 & src2)
185 BFM, // Insert a range of bits into a 32-bit word.
201 // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
206 /// This node is for VLIW targets and it is used to represent a vector
207 /// that is stored in consecutive registers with the same channel.
214 BUILD_VERTICAL_VECTOR,
215 FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
218 TBUFFER_STORE_FORMAT,
219 LAST_AMDGPU_ISD_NUMBER
223 } // End namespace AMDGPUISD
225 } // End namespace llvm
227 #endif // AMDGPUISELLOWERING_H