1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPURegisterInfo.h"
19 #include "AMDGPUSubtarget.h"
20 #include "AMDILIntrinsicInfo.h"
21 #include "R600MachineFunctionInfo.h"
22 #include "SIMachineFunctionInfo.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/DataLayout.h"
32 #include "AMDGPUGenCallingConv.inc"
34 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
35 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
37 // Initialize target lowering borrowed from AMDIL
40 // We need to custom lower some of the intrinsics
41 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
43 // Library functions. These default to Expand, but we have instructions
45 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
46 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
47 setOperationAction(ISD::FPOW, MVT::f32, Legal);
48 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
49 setOperationAction(ISD::FABS, MVT::f32, Legal);
50 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
51 setOperationAction(ISD::FRINT, MVT::f32, Legal);
53 // The hardware supports ROTR, but not ROTL
54 setOperationAction(ISD::ROTL, MVT::i32, Expand);
56 // Lower floating point store/load to integer store/load to reduce the number
57 // of patterns in tablegen.
58 setOperationAction(ISD::STORE, MVT::f32, Promote);
59 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
61 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
62 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
64 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
65 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
67 setOperationAction(ISD::STORE, MVT::f64, Promote);
68 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
70 // Custom lowering of vector stores is required for local address space
72 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
73 // XXX: Native v2i32 local address space stores are possible, but not
74 // currently implemented.
75 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
77 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
78 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
79 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
80 // XXX: This can be change to Custom, once ExpandVectorStores can
81 // handle 64-bit stores.
82 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
84 setOperationAction(ISD::LOAD, MVT::f32, Promote);
85 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
87 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
88 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
90 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
91 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
93 setOperationAction(ISD::LOAD, MVT::f64, Promote);
94 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
96 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
97 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
98 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
99 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
101 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
102 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
103 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
104 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
105 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
106 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
107 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
108 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
109 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
110 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
111 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
112 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
114 setOperationAction(ISD::FNEG, MVT::v2f32, Expand);
115 setOperationAction(ISD::FNEG, MVT::v4f32, Expand);
117 setOperationAction(ISD::MUL, MVT::i64, Expand);
119 setOperationAction(ISD::UDIV, MVT::i32, Expand);
120 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
121 setOperationAction(ISD::UREM, MVT::i32, Expand);
122 setOperationAction(ISD::VSELECT, MVT::v2f32, Expand);
123 setOperationAction(ISD::VSELECT, MVT::v4f32, Expand);
125 static const MVT::SimpleValueType IntTypes[] = {
126 MVT::v2i32, MVT::v4i32
128 const size_t NumIntTypes = array_lengthof(IntTypes);
130 for (unsigned int x = 0; x < NumIntTypes; ++x) {
131 MVT::SimpleValueType VT = IntTypes[x];
132 //Expand the following operations for the current type by default
133 setOperationAction(ISD::ADD, VT, Expand);
134 setOperationAction(ISD::AND, VT, Expand);
135 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
136 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
137 setOperationAction(ISD::MUL, VT, Expand);
138 setOperationAction(ISD::OR, VT, Expand);
139 setOperationAction(ISD::SHL, VT, Expand);
140 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
141 setOperationAction(ISD::SRL, VT, Expand);
142 setOperationAction(ISD::SRA, VT, Expand);
143 setOperationAction(ISD::SUB, VT, Expand);
144 setOperationAction(ISD::UDIV, VT, Expand);
145 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
146 setOperationAction(ISD::UREM, VT, Expand);
147 setOperationAction(ISD::VSELECT, VT, Expand);
148 setOperationAction(ISD::XOR, VT, Expand);
151 static const MVT::SimpleValueType FloatTypes[] = {
152 MVT::v2f32, MVT::v4f32
154 const size_t NumFloatTypes = array_lengthof(FloatTypes);
156 for (unsigned int x = 0; x < NumFloatTypes; ++x) {
157 MVT::SimpleValueType VT = FloatTypes[x];
158 setOperationAction(ISD::FADD, VT, Expand);
159 setOperationAction(ISD::FDIV, VT, Expand);
160 setOperationAction(ISD::FFLOOR, VT, Expand);
161 setOperationAction(ISD::FMUL, VT, Expand);
162 setOperationAction(ISD::FRINT, VT, Expand);
163 setOperationAction(ISD::FSUB, VT, Expand);
167 //===----------------------------------------------------------------------===//
168 // Target Information
169 //===----------------------------------------------------------------------===//
171 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
176 //===---------------------------------------------------------------------===//
178 //===---------------------------------------------------------------------===//
180 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
181 assert(VT.isFloatingPoint());
182 return VT == MVT::f32;
185 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
186 assert(VT.isFloatingPoint());
187 return VT == MVT::f32;
190 //===---------------------------------------------------------------------===//
191 // TargetLowering Callbacks
192 //===---------------------------------------------------------------------===//
194 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
195 const SmallVectorImpl<ISD::InputArg> &Ins) const {
197 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
200 SDValue AMDGPUTargetLowering::LowerReturn(
202 CallingConv::ID CallConv,
204 const SmallVectorImpl<ISD::OutputArg> &Outs,
205 const SmallVectorImpl<SDValue> &OutVals,
206 SDLoc DL, SelectionDAG &DAG) const {
207 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
210 //===---------------------------------------------------------------------===//
211 // Target specific lowering
212 //===---------------------------------------------------------------------===//
214 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
216 switch (Op.getOpcode()) {
218 Op.getNode()->dump();
219 assert(0 && "Custom lowering code for this"
220 "instruction is not implemented yet!");
222 // AMDIL DAG lowering
223 case ISD::SDIV: return LowerSDIV(Op, DAG);
224 case ISD::SREM: return LowerSREM(Op, DAG);
225 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
226 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
227 // AMDGPU DAG lowering
228 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
229 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
230 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
231 case ISD::STORE: return LowerSTORE(Op, DAG);
232 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
237 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
239 SelectionDAG &DAG) const {
241 const DataLayout *TD = getTargetMachine().getDataLayout();
242 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
244 assert(G->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS);
245 // XXX: What does the value of G->getOffset() mean?
246 assert(G->getOffset() == 0 &&
247 "Do not know what to do with an non-zero offset");
249 const GlobalValue *GV = G->getGlobal();
252 if (MFI->LocalMemoryObjects.count(GV) == 0) {
253 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
254 Offset = MFI->LDSSize;
255 MFI->LocalMemoryObjects[GV] = Offset;
256 // XXX: Account for alignment?
257 MFI->LDSSize += Size;
259 Offset = MFI->LocalMemoryObjects[GV];
262 return DAG.getConstant(Offset, getPointerTy(G->getAddressSpace()));
265 void AMDGPUTargetLowering::ExtractVectorElements(SDValue Op, SelectionDAG &DAG,
266 SmallVectorImpl<SDValue> &Args,
268 unsigned Count) const {
269 EVT VT = Op.getValueType();
270 for (unsigned i = Start, e = Start + Count; i != e; ++i) {
271 Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
272 VT.getVectorElementType(),
273 Op, DAG.getConstant(i, MVT::i32)));
277 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
278 SelectionDAG &DAG) const {
279 SmallVector<SDValue, 8> Args;
280 SDValue A = Op.getOperand(0);
281 SDValue B = Op.getOperand(1);
283 ExtractVectorElements(A, DAG, Args, 0,
284 A.getValueType().getVectorNumElements());
285 ExtractVectorElements(B, DAG, Args, 0,
286 B.getValueType().getVectorNumElements());
288 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(),
289 &Args[0], Args.size());
292 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
293 SelectionDAG &DAG) const {
295 SmallVector<SDValue, 8> Args;
296 EVT VT = Op.getValueType();
297 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
298 ExtractVectorElements(Op.getOperand(0), DAG, Args, Start,
299 VT.getVectorNumElements());
301 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(),
302 &Args[0], Args.size());
306 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
307 SelectionDAG &DAG) const {
308 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
310 EVT VT = Op.getValueType();
312 switch (IntrinsicID) {
314 case AMDGPUIntrinsic::AMDIL_abs:
315 return LowerIntrinsicIABS(Op, DAG);
316 case AMDGPUIntrinsic::AMDIL_exp:
317 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
318 case AMDGPUIntrinsic::AMDGPU_lrp:
319 return LowerIntrinsicLRP(Op, DAG);
320 case AMDGPUIntrinsic::AMDIL_fraction:
321 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
322 case AMDGPUIntrinsic::AMDIL_max:
323 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
325 case AMDGPUIntrinsic::AMDGPU_imax:
326 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
328 case AMDGPUIntrinsic::AMDGPU_umax:
329 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
331 case AMDGPUIntrinsic::AMDIL_min:
332 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
334 case AMDGPUIntrinsic::AMDGPU_imin:
335 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
337 case AMDGPUIntrinsic::AMDGPU_umin:
338 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
340 case AMDGPUIntrinsic::AMDIL_round_nearest:
341 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
345 ///IABS(a) = SMAX(sub(0, a), a)
346 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
347 SelectionDAG &DAG) const {
350 EVT VT = Op.getValueType();
351 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
354 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
357 /// Linear Interpolation
358 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
359 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
360 SelectionDAG &DAG) const {
362 EVT VT = Op.getValueType();
363 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
364 DAG.getConstantFP(1.0f, MVT::f32),
366 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
368 return DAG.getNode(ISD::FADD, DL, VT,
369 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
373 /// \brief Generate Min/Max node
374 SDValue AMDGPUTargetLowering::LowerMinMax(SDValue Op,
375 SelectionDAG &DAG) const {
377 EVT VT = Op.getValueType();
379 SDValue LHS = Op.getOperand(0);
380 SDValue RHS = Op.getOperand(1);
381 SDValue True = Op.getOperand(2);
382 SDValue False = Op.getOperand(3);
383 SDValue CC = Op.getOperand(4);
385 if (VT != MVT::f32 ||
386 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
390 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
404 assert(0 && "Operation should already be optimised !");
412 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
414 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
423 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
425 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
427 case ISD::SETCC_INVALID:
428 assert(0 && "Invalid setcc condcode !");
433 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue &Op,
434 SelectionDAG &DAG) const {
435 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op);
436 EVT MemEltVT = Load->getMemoryVT().getVectorElementType();
437 EVT EltVT = Op.getValueType().getVectorElementType();
438 EVT PtrVT = Load->getBasePtr().getValueType();
439 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
440 SmallVector<SDValue, 8> Loads;
443 for (unsigned i = 0, e = NumElts; i != e; ++i) {
444 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
445 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8), PtrVT));
446 Loads.push_back(DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
447 Load->getChain(), Ptr,
448 MachinePointerInfo(Load->getMemOperand()->getValue()),
449 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
450 Load->getAlignment()));
452 return DAG.getNode(ISD::BUILD_VECTOR, SL, Op.getValueType(), &Loads[0],
456 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
457 SelectionDAG &DAG) const {
458 StoreSDNode *Store = dyn_cast<StoreSDNode>(Op);
459 EVT MemVT = Store->getMemoryVT();
460 unsigned MemBits = MemVT.getSizeInBits();
462 // Byte stores are really expensive, so if possible, try to pack
463 // 32-bit vector truncatating store into an i32 store.
464 // XXX: We could also handle optimize other vector bitwidths
465 if (!MemVT.isVector() || MemBits > 32) {
470 const SDValue &Value = Store->getValue();
471 EVT VT = Value.getValueType();
472 const SDValue &Ptr = Store->getBasePtr();
473 EVT MemEltVT = MemVT.getVectorElementType();
474 unsigned MemEltBits = MemEltVT.getSizeInBits();
475 unsigned MemNumElements = MemVT.getVectorNumElements();
476 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits());
480 Mask = DAG.getConstant(0xFF, PackedVT);
483 Mask = DAG.getConstant(0xFFFF, PackedVT);
486 llvm_unreachable("Cannot lower this vector store");
489 for (unsigned i = 0; i < MemNumElements; ++i) {
490 EVT ElemVT = VT.getVectorElementType();
491 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
492 DAG.getConstant(i, MVT::i32));
493 Elt = DAG.getZExtOrTrunc(Elt, DL, PackedVT);
494 Elt = DAG.getNode(ISD::AND, DL, PackedVT, Elt, Mask);
495 SDValue Shift = DAG.getConstant(MemEltBits * i, PackedVT);
496 Elt = DAG.getNode(ISD::SHL, DL, PackedVT, Elt, Shift);
500 PackedValue = DAG.getNode(ISD::OR, DL, PackedVT, PackedValue, Elt);
503 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
504 MachinePointerInfo(Store->getMemOperand()->getValue()),
505 Store->isVolatile(), Store->isNonTemporal(),
506 Store->getAlignment());
509 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
510 SelectionDAG &DAG) const {
511 StoreSDNode *Store = cast<StoreSDNode>(Op);
512 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
513 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
514 EVT PtrVT = Store->getBasePtr().getValueType();
515 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
518 SmallVector<SDValue, 8> Chains;
520 for (unsigned i = 0, e = NumElts; i != e; ++i) {
521 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
522 Store->getValue(), DAG.getConstant(i, MVT::i32));
523 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT,
525 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8),
527 Chains.push_back(DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
528 MachinePointerInfo(Store->getMemOperand()->getValue()),
529 MemEltVT, Store->isVolatile(), Store->isNonTemporal(),
530 Store->getAlignment()));
532 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, &Chains[0], NumElts);
535 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
536 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
537 if (Result.getNode()) {
541 StoreSDNode *Store = cast<StoreSDNode>(Op);
542 if (Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
543 Store->getValue().getValueType().isVector()) {
544 return SplitVectorStore(Op, DAG);
549 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
550 SelectionDAG &DAG) const {
552 EVT VT = Op.getValueType();
554 SDValue Num = Op.getOperand(0);
555 SDValue Den = Op.getOperand(1);
557 SmallVector<SDValue, 8> Results;
559 // RCP = URECIP(Den) = 2^32 / Den + e
560 // e is rounding error.
561 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
563 // RCP_LO = umulo(RCP, Den) */
564 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
566 // RCP_HI = mulhu (RCP, Den) */
567 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
569 // NEG_RCP_LO = -RCP_LO
570 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
573 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
574 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
577 // Calculate the rounding error from the URECIP instruction
578 // E = mulhu(ABS_RCP_LO, RCP)
579 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
582 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
585 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
587 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
588 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
591 // Quotient = mulhu(Tmp0, Num)
592 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
594 // Num_S_Remainder = Quotient * Den
595 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
597 // Remainder = Num - Num_S_Remainder
598 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
600 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
601 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
602 DAG.getConstant(-1, VT),
603 DAG.getConstant(0, VT),
605 // Remainder_GE_Zero = (Remainder >= 0 ? -1 : 0)
606 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Remainder,
607 DAG.getConstant(0, VT),
608 DAG.getConstant(-1, VT),
609 DAG.getConstant(0, VT),
611 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
612 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
615 // Calculate Division result:
617 // Quotient_A_One = Quotient + 1
618 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
619 DAG.getConstant(1, VT));
621 // Quotient_S_One = Quotient - 1
622 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
623 DAG.getConstant(1, VT));
625 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
626 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
627 Quotient, Quotient_A_One, ISD::SETEQ);
629 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
630 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
631 Quotient_S_One, Div, ISD::SETEQ);
633 // Calculate Rem result:
635 // Remainder_S_Den = Remainder - Den
636 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
638 // Remainder_A_Den = Remainder + Den
639 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
641 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
642 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
643 Remainder, Remainder_S_Den, ISD::SETEQ);
645 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
646 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
647 Remainder_A_Den, Rem, ISD::SETEQ);
651 return DAG.getMergeValues(Ops, 2, DL);
655 //===----------------------------------------------------------------------===//
657 //===----------------------------------------------------------------------===//
659 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
660 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
661 return CFP->isExactlyValue(1.0);
663 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
664 return C->isAllOnesValue();
669 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
670 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
671 return CFP->getValueAPF().isZero();
673 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
674 return C->isNullValue();
679 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
680 const TargetRegisterClass *RC,
681 unsigned Reg, EVT VT) const {
682 MachineFunction &MF = DAG.getMachineFunction();
683 MachineRegisterInfo &MRI = MF.getRegInfo();
684 unsigned VirtualRegister;
685 if (!MRI.isLiveIn(Reg)) {
686 VirtualRegister = MRI.createVirtualRegister(RC);
687 MRI.addLiveIn(Reg, VirtualRegister);
689 VirtualRegister = MRI.getLiveInVirtReg(Reg);
691 return DAG.getRegister(VirtualRegister, VT);
694 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
696 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
700 NODE_NAME_CASE(CALL);
701 NODE_NAME_CASE(UMUL);
702 NODE_NAME_CASE(DIV_INF);
703 NODE_NAME_CASE(RET_FLAG);
704 NODE_NAME_CASE(BRANCH_COND);
707 NODE_NAME_CASE(DWORDADDR)
708 NODE_NAME_CASE(FRACT)
715 NODE_NAME_CASE(URECIP)
716 NODE_NAME_CASE(EXPORT)
717 NODE_NAME_CASE(CONST_ADDRESS)
718 NODE_NAME_CASE(REGISTER_LOAD)
719 NODE_NAME_CASE(REGISTER_STORE)
720 NODE_NAME_CASE(LOAD_CONSTANT)
721 NODE_NAME_CASE(LOAD_INPUT)
722 NODE_NAME_CASE(SAMPLE)
723 NODE_NAME_CASE(SAMPLEB)
724 NODE_NAME_CASE(SAMPLED)
725 NODE_NAME_CASE(SAMPLEL)
726 NODE_NAME_CASE(STORE_MSKOR)