1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
17 #include "AMDGPURegisterInfo.h"
18 #include "AMDILIntrinsicInfo.h"
19 #include "AMDGPUSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "AMDGPUGenCallingConv.inc"
30 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
31 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
33 // Initialize target lowering borrowed from AMDIL
36 // We need to custom lower some of the intrinsics
37 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
39 // Library functions. These default to Expand, but we have instructions
41 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
42 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
43 setOperationAction(ISD::FPOW, MVT::f32, Legal);
44 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
45 setOperationAction(ISD::FABS, MVT::f32, Legal);
46 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
47 setOperationAction(ISD::FRINT, MVT::f32, Legal);
49 // The hardware supports ROTR, but not ROTL
50 setOperationAction(ISD::ROTL, MVT::i32, Expand);
52 // Lower floating point store/load to integer store/load to reduce the number
53 // of patterns in tablegen.
54 setOperationAction(ISD::STORE, MVT::f32, Promote);
55 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
57 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
58 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
60 setOperationAction(ISD::LOAD, MVT::f32, Promote);
61 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
63 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
64 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
66 setOperationAction(ISD::MUL, MVT::i64, Expand);
68 setOperationAction(ISD::UDIV, MVT::i32, Expand);
69 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
70 setOperationAction(ISD::UREM, MVT::i32, Expand);
73 //===---------------------------------------------------------------------===//
74 // TargetLowering Callbacks
75 //===---------------------------------------------------------------------===//
77 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
78 const SmallVectorImpl<ISD::InputArg> &Ins) const {
80 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
83 SDValue AMDGPUTargetLowering::LowerReturn(
85 CallingConv::ID CallConv,
87 const SmallVectorImpl<ISD::OutputArg> &Outs,
88 const SmallVectorImpl<SDValue> &OutVals,
89 DebugLoc DL, SelectionDAG &DAG) const {
90 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
93 //===---------------------------------------------------------------------===//
94 // Target specific lowering
95 //===---------------------------------------------------------------------===//
97 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
99 switch (Op.getOpcode()) {
101 Op.getNode()->dump();
102 assert(0 && "Custom lowering code for this"
103 "instruction is not implemented yet!");
105 // AMDIL DAG lowering
106 case ISD::SDIV: return LowerSDIV(Op, DAG);
107 case ISD::SREM: return LowerSREM(Op, DAG);
108 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
109 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
110 // AMDGPU DAG lowering
111 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
112 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
117 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
118 SelectionDAG &DAG) const {
119 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
120 DebugLoc DL = Op.getDebugLoc();
121 EVT VT = Op.getValueType();
123 switch (IntrinsicID) {
125 case AMDGPUIntrinsic::AMDIL_abs:
126 return LowerIntrinsicIABS(Op, DAG);
127 case AMDGPUIntrinsic::AMDIL_exp:
128 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
129 case AMDGPUIntrinsic::AMDGPU_lrp:
130 return LowerIntrinsicLRP(Op, DAG);
131 case AMDGPUIntrinsic::AMDIL_fraction:
132 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
133 case AMDGPUIntrinsic::AMDIL_max:
134 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
136 case AMDGPUIntrinsic::AMDGPU_imax:
137 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
139 case AMDGPUIntrinsic::AMDGPU_umax:
140 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
142 case AMDGPUIntrinsic::AMDIL_min:
143 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
145 case AMDGPUIntrinsic::AMDGPU_imin:
146 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
148 case AMDGPUIntrinsic::AMDGPU_umin:
149 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
151 case AMDGPUIntrinsic::AMDIL_round_nearest:
152 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
156 ///IABS(a) = SMAX(sub(0, a), a)
157 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
158 SelectionDAG &DAG) const {
160 DebugLoc DL = Op.getDebugLoc();
161 EVT VT = Op.getValueType();
162 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
165 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
168 /// Linear Interpolation
169 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
170 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
171 SelectionDAG &DAG) const {
172 DebugLoc DL = Op.getDebugLoc();
173 EVT VT = Op.getValueType();
174 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
175 DAG.getConstantFP(1.0f, MVT::f32),
177 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
179 return DAG.getNode(ISD::FADD, DL, VT,
180 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
184 /// \brief Generate Min/Max node
185 SDValue AMDGPUTargetLowering::LowerMinMax(SDValue Op,
186 SelectionDAG &DAG) const {
187 DebugLoc DL = Op.getDebugLoc();
188 EVT VT = Op.getValueType();
190 SDValue LHS = Op.getOperand(0);
191 SDValue RHS = Op.getOperand(1);
192 SDValue True = Op.getOperand(2);
193 SDValue False = Op.getOperand(3);
194 SDValue CC = Op.getOperand(4);
196 if (VT != MVT::f32 ||
197 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
201 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
215 assert(0 && "Operation should already be optimised !");
223 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
225 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
234 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
236 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
238 case ISD::SETCC_INVALID:
239 assert(0 && "Invalid setcc condcode !");
246 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
247 SelectionDAG &DAG) const {
248 DebugLoc DL = Op.getDebugLoc();
249 EVT VT = Op.getValueType();
251 SDValue Num = Op.getOperand(0);
252 SDValue Den = Op.getOperand(1);
254 SmallVector<SDValue, 8> Results;
256 // RCP = URECIP(Den) = 2^32 / Den + e
257 // e is rounding error.
258 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
260 // RCP_LO = umulo(RCP, Den) */
261 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
263 // RCP_HI = mulhu (RCP, Den) */
264 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
266 // NEG_RCP_LO = -RCP_LO
267 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
270 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
271 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
274 // Calculate the rounding error from the URECIP instruction
275 // E = mulhu(ABS_RCP_LO, RCP)
276 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
279 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
282 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
284 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
285 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
288 // Quotient = mulhu(Tmp0, Num)
289 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
291 // Num_S_Remainder = Quotient * Den
292 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
294 // Remainder = Num - Num_S_Remainder
295 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
297 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
298 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
299 DAG.getConstant(-1, VT),
300 DAG.getConstant(0, VT),
302 // Remainder_GE_Zero = (Remainder >= 0 ? -1 : 0)
303 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Remainder,
304 DAG.getConstant(0, VT),
305 DAG.getConstant(-1, VT),
306 DAG.getConstant(0, VT),
308 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
309 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
312 // Calculate Division result:
314 // Quotient_A_One = Quotient + 1
315 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
316 DAG.getConstant(1, VT));
318 // Quotient_S_One = Quotient - 1
319 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
320 DAG.getConstant(1, VT));
322 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
323 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
324 Quotient, Quotient_A_One, ISD::SETEQ);
326 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
327 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
328 Quotient_S_One, Div, ISD::SETEQ);
330 // Calculate Rem result:
332 // Remainder_S_Den = Remainder - Den
333 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
335 // Remainder_A_Den = Remainder + Den
336 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
338 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
339 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
340 Remainder, Remainder_S_Den, ISD::SETEQ);
342 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
343 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
344 Remainder_A_Den, Rem, ISD::SETEQ);
348 return DAG.getMergeValues(Ops, 2, DL);
351 //===----------------------------------------------------------------------===//
353 //===----------------------------------------------------------------------===//
355 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
356 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
357 return CFP->isExactlyValue(1.0);
359 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
360 return C->isAllOnesValue();
365 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
366 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
367 return CFP->getValueAPF().isZero();
369 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
370 return C->isNullValue();
375 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
376 const TargetRegisterClass *RC,
377 unsigned Reg, EVT VT) const {
378 MachineFunction &MF = DAG.getMachineFunction();
379 MachineRegisterInfo &MRI = MF.getRegInfo();
380 unsigned VirtualRegister;
381 if (!MRI.isLiveIn(Reg)) {
382 VirtualRegister = MRI.createVirtualRegister(RC);
383 MRI.addLiveIn(Reg, VirtualRegister);
385 VirtualRegister = MRI.getLiveInVirtReg(Reg);
387 return DAG.getRegister(VirtualRegister, VT);
390 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
392 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
396 NODE_NAME_CASE(CALL);
397 NODE_NAME_CASE(UMUL);
398 NODE_NAME_CASE(DIV_INF);
399 NODE_NAME_CASE(RET_FLAG);
400 NODE_NAME_CASE(BRANCH_COND);
403 NODE_NAME_CASE(DWORDADDR)
404 NODE_NAME_CASE(FRACT)
411 NODE_NAME_CASE(URECIP)
412 NODE_NAME_CASE(EXPORT)
413 NODE_NAME_CASE(CONST_ADDRESS)
414 NODE_NAME_CASE(REGISTER_LOAD)
415 NODE_NAME_CASE(REGISTER_STORE)