1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DiagnosticInfo.h"
31 #include "llvm/IR/DiagnosticPrinter.h"
37 /// Diagnostic information for unimplemented or unsupported feature reporting.
38 class DiagnosticInfoUnsupported : public DiagnosticInfo {
40 const Twine &Description;
45 static int getKindID() {
47 KindID = llvm::getNextAvailablePluginDiagnosticKind();
52 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
53 DiagnosticSeverity Severity = DS_Error)
54 : DiagnosticInfo(getKindID(), Severity),
58 const Function &getFunction() const { return Fn; }
59 const Twine &getDescription() const { return Description; }
61 void print(DiagnosticPrinter &DP) const override {
62 DP << "unsupported " << getDescription() << " in " << Fn.getName();
65 static bool classof(const DiagnosticInfo *DI) {
66 return DI->getKind() == getKindID();
70 int DiagnosticInfoUnsupported::KindID = 0;
74 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
75 CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, CCState &State) {
77 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
78 ArgFlags.getOrigAlign());
79 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
84 #include "AMDGPUGenCallingConv.inc"
86 // Find a larger type to do a load / store of a vector with.
87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
88 unsigned StoreSize = VT.getStoreSizeInBits();
90 return EVT::getIntegerVT(Ctx, StoreSize);
92 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
93 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
96 // Type for a vector that will be loaded to.
97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
98 unsigned StoreSize = VT.getStoreSizeInBits();
100 return EVT::getIntegerVT(Ctx, 32);
102 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
105 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
106 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
108 Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
110 setOperationAction(ISD::Constant, MVT::i32, Legal);
111 setOperationAction(ISD::Constant, MVT::i64, Legal);
112 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
113 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
115 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
116 setOperationAction(ISD::BRIND, MVT::Other, Expand);
118 // We need to custom lower some of the intrinsics
119 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
121 // Library functions. These default to Expand, but we have instructions
123 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
124 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
125 setOperationAction(ISD::FPOW, MVT::f32, Legal);
126 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
127 setOperationAction(ISD::FABS, MVT::f32, Legal);
128 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
129 setOperationAction(ISD::FRINT, MVT::f32, Legal);
130 setOperationAction(ISD::FROUND, MVT::f32, Legal);
131 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
133 // Lower floating point store/load to integer store/load to reduce the number
134 // of patterns in tablegen.
135 setOperationAction(ISD::STORE, MVT::f32, Promote);
136 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
138 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
139 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
141 setOperationAction(ISD::STORE, MVT::i64, Promote);
142 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
144 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
145 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
147 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
148 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
150 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
151 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
153 setOperationAction(ISD::STORE, MVT::f64, Promote);
154 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
156 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
157 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
159 // Custom lowering of vector stores is required for local address space
161 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
162 // XXX: Native v2i32 local address space stores are possible, but not
163 // currently implemented.
164 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
166 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
167 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
168 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
170 // XXX: This can be change to Custom, once ExpandVectorStores can
171 // handle 64-bit stores.
172 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
174 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
175 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
176 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
177 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
178 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
181 setOperationAction(ISD::LOAD, MVT::f32, Promote);
182 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
184 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
185 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
187 setOperationAction(ISD::LOAD, MVT::i64, Promote);
188 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
190 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
191 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
193 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
194 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
196 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
197 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
199 setOperationAction(ISD::LOAD, MVT::f64, Promote);
200 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
202 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
203 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
205 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
206 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
207 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
208 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
209 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
210 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
211 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
212 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
213 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
214 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
216 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
217 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
218 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
219 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
220 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
221 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
222 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
223 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
224 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
225 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
226 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
227 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
229 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
231 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
232 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
233 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
234 setOperationAction(ISD::FRINT, MVT::f64, Custom);
235 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
238 if (!Subtarget->hasBFI()) {
239 // fcopysign can be done in a single instruction with BFI.
240 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
241 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
244 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
246 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
247 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
248 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
250 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
251 for (MVT VT : ScalarIntVTs) {
252 setOperationAction(ISD::SREM, VT, Expand);
253 setOperationAction(ISD::SDIV, VT, Custom);
255 // GPU does not have divrem function for signed or unsigned.
256 setOperationAction(ISD::SDIVREM, VT, Custom);
257 setOperationAction(ISD::UDIVREM, VT, Custom);
259 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
260 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
261 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
263 setOperationAction(ISD::BSWAP, VT, Expand);
264 setOperationAction(ISD::CTTZ, VT, Expand);
265 setOperationAction(ISD::CTLZ, VT, Expand);
268 if (!Subtarget->hasBCNT(32))
269 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
271 if (!Subtarget->hasBCNT(64))
272 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
274 // The hardware supports 32-bit ROTR, but not ROTL.
275 setOperationAction(ISD::ROTL, MVT::i32, Expand);
276 setOperationAction(ISD::ROTL, MVT::i64, Expand);
277 setOperationAction(ISD::ROTR, MVT::i64, Expand);
279 setOperationAction(ISD::MUL, MVT::i64, Expand);
280 setOperationAction(ISD::MULHU, MVT::i64, Expand);
281 setOperationAction(ISD::MULHS, MVT::i64, Expand);
282 setOperationAction(ISD::UDIV, MVT::i32, Expand);
283 setOperationAction(ISD::UREM, MVT::i32, Expand);
284 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
285 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
287 if (!Subtarget->hasFFBH())
288 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
290 if (!Subtarget->hasFFBL())
291 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
293 static const MVT::SimpleValueType VectorIntTypes[] = {
294 MVT::v2i32, MVT::v4i32
297 for (MVT VT : VectorIntTypes) {
298 // Expand the following operations for the current type by default.
299 setOperationAction(ISD::ADD, VT, Expand);
300 setOperationAction(ISD::AND, VT, Expand);
301 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
302 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
303 setOperationAction(ISD::MUL, VT, Expand);
304 setOperationAction(ISD::OR, VT, Expand);
305 setOperationAction(ISD::SHL, VT, Expand);
306 setOperationAction(ISD::SRA, VT, Expand);
307 setOperationAction(ISD::SRL, VT, Expand);
308 setOperationAction(ISD::ROTL, VT, Expand);
309 setOperationAction(ISD::ROTR, VT, Expand);
310 setOperationAction(ISD::SUB, VT, Expand);
311 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
312 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
313 // TODO: Implement custom UREM / SREM routines.
314 setOperationAction(ISD::SDIV, VT, Expand);
315 setOperationAction(ISD::UDIV, VT, Expand);
316 setOperationAction(ISD::SREM, VT, Expand);
317 setOperationAction(ISD::UREM, VT, Expand);
318 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
319 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
320 setOperationAction(ISD::SDIVREM, VT, Custom);
321 setOperationAction(ISD::UDIVREM, VT, Custom);
322 setOperationAction(ISD::ADDC, VT, Expand);
323 setOperationAction(ISD::SUBC, VT, Expand);
324 setOperationAction(ISD::ADDE, VT, Expand);
325 setOperationAction(ISD::SUBE, VT, Expand);
326 setOperationAction(ISD::SELECT, VT, Expand);
327 setOperationAction(ISD::VSELECT, VT, Expand);
328 setOperationAction(ISD::SELECT_CC, VT, Expand);
329 setOperationAction(ISD::XOR, VT, Expand);
330 setOperationAction(ISD::BSWAP, VT, Expand);
331 setOperationAction(ISD::CTPOP, VT, Expand);
332 setOperationAction(ISD::CTTZ, VT, Expand);
333 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
334 setOperationAction(ISD::CTLZ, VT, Expand);
335 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
339 static const MVT::SimpleValueType FloatVectorTypes[] = {
340 MVT::v2f32, MVT::v4f32
343 for (MVT VT : FloatVectorTypes) {
344 setOperationAction(ISD::FABS, VT, Expand);
345 setOperationAction(ISD::FADD, VT, Expand);
346 setOperationAction(ISD::FCEIL, VT, Expand);
347 setOperationAction(ISD::FCOS, VT, Expand);
348 setOperationAction(ISD::FDIV, VT, Expand);
349 setOperationAction(ISD::FEXP2, VT, Expand);
350 setOperationAction(ISD::FLOG2, VT, Expand);
351 setOperationAction(ISD::FPOW, VT, Expand);
352 setOperationAction(ISD::FFLOOR, VT, Expand);
353 setOperationAction(ISD::FTRUNC, VT, Expand);
354 setOperationAction(ISD::FMUL, VT, Expand);
355 setOperationAction(ISD::FMA, VT, Expand);
356 setOperationAction(ISD::FRINT, VT, Expand);
357 setOperationAction(ISD::FNEARBYINT, VT, Expand);
358 setOperationAction(ISD::FSQRT, VT, Expand);
359 setOperationAction(ISD::FSIN, VT, Expand);
360 setOperationAction(ISD::FSUB, VT, Expand);
361 setOperationAction(ISD::FNEG, VT, Expand);
362 setOperationAction(ISD::SELECT, VT, Expand);
363 setOperationAction(ISD::VSELECT, VT, Expand);
364 setOperationAction(ISD::SELECT_CC, VT, Expand);
365 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
366 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
369 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
370 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
372 setTargetDAGCombine(ISD::MUL);
373 setTargetDAGCombine(ISD::SELECT_CC);
374 setTargetDAGCombine(ISD::STORE);
376 setSchedulingPreference(Sched::RegPressure);
377 setJumpIsExpensive(true);
379 setSelectIsExpensive(false);
380 PredictableSelectIsExpensive = false;
382 // There are no integer divide instructions, and these expand to a pretty
383 // large sequence of instructions.
384 setIntDivIsCheap(false);
385 setPow2DivIsCheap(false);
387 // TODO: Investigate this when 64-bit divides are implemented.
388 addBypassSlowDiv(64, 32);
390 // FIXME: Need to really handle these.
391 MaxStoresPerMemcpy = 4096;
392 MaxStoresPerMemmove = 4096;
393 MaxStoresPerMemset = 4096;
396 //===----------------------------------------------------------------------===//
397 // Target Information
398 //===----------------------------------------------------------------------===//
400 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
404 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
408 // The backend supports 32 and 64 bit floating point immediates.
409 // FIXME: Why are we reporting vectors of FP immediates as legal?
410 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
411 EVT ScalarVT = VT.getScalarType();
412 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
415 // We don't want to shrink f64 / f32 constants.
416 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
417 EVT ScalarVT = VT.getScalarType();
418 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
421 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
423 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
426 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
427 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
429 return ((LScalarSize <= CastScalarSize) ||
430 (CastScalarSize >= 32) ||
434 //===---------------------------------------------------------------------===//
436 //===---------------------------------------------------------------------===//
438 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
439 assert(VT.isFloatingPoint());
440 return VT == MVT::f32;
443 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
444 assert(VT.isFloatingPoint());
445 return VT == MVT::f32;
448 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
449 // Truncate is just accessing a subregister.
450 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
453 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
454 // Truncate is just accessing a subregister.
455 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
456 (Dest->getPrimitiveSizeInBits() % 32 == 0);
459 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
460 const DataLayout *DL = getDataLayout();
461 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
462 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
464 return SrcSize == 32 && DestSize == 64;
467 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
468 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
469 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
470 // this will enable reducing 64-bit operations the 32-bit, which is always
472 return Src == MVT::i32 && Dest == MVT::i64;
475 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
476 return isZExtFree(Val.getValueType(), VT2);
479 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
480 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
481 // limited number of native 64-bit operations. Shrinking an operation to fit
482 // in a single 32-bit register should always be helpful. As currently used,
483 // this is much less general than the name suggests, and is only used in
484 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
485 // not profitable, and may actually be harmful.
486 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
489 //===---------------------------------------------------------------------===//
490 // TargetLowering Callbacks
491 //===---------------------------------------------------------------------===//
493 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
494 const SmallVectorImpl<ISD::InputArg> &Ins) const {
496 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
499 SDValue AMDGPUTargetLowering::LowerReturn(
501 CallingConv::ID CallConv,
503 const SmallVectorImpl<ISD::OutputArg> &Outs,
504 const SmallVectorImpl<SDValue> &OutVals,
505 SDLoc DL, SelectionDAG &DAG) const {
506 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
509 //===---------------------------------------------------------------------===//
510 // Target specific lowering
511 //===---------------------------------------------------------------------===//
513 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
514 SmallVectorImpl<SDValue> &InVals) const {
515 SDValue Callee = CLI.Callee;
516 SelectionDAG &DAG = CLI.DAG;
518 const Function &Fn = *DAG.getMachineFunction().getFunction();
520 StringRef FuncName("<unknown>");
522 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
523 FuncName = G->getSymbol();
524 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
525 FuncName = G->getGlobal()->getName();
527 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
528 DAG.getContext()->diagnose(NoCalls);
532 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
533 SelectionDAG &DAG) const {
534 switch (Op.getOpcode()) {
536 Op.getNode()->dump();
537 llvm_unreachable("Custom lowering code for this"
538 "instruction is not implemented yet!");
540 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
541 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
542 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
543 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
544 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
545 case ISD::SDIV: return LowerSDIV(Op, DAG);
546 case ISD::SREM: return LowerSREM(Op, DAG);
547 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
548 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
549 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
550 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
551 case ISD::FRINT: return LowerFRINT(Op, DAG);
552 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
553 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
554 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
559 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
560 SmallVectorImpl<SDValue> &Results,
561 SelectionDAG &DAG) const {
562 switch (N->getOpcode()) {
563 case ISD::SIGN_EXTEND_INREG:
564 // Different parts of legalization seem to interpret which type of
565 // sign_extend_inreg is the one to check for custom lowering. The extended
566 // from type is what really matters, but some places check for custom
567 // lowering of the result type. This results in trying to use
568 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
569 // nothing here and let the illegal result integer be handled normally.
572 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
576 Results.push_back(SDValue(Node, 0));
577 Results.push_back(SDValue(Node, 1));
578 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
580 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
584 SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
585 if (Lowered.getNode())
586 Results.push_back(Lowered);
594 // FIXME: This implements accesses to initialized globals in the constant
595 // address space by copying them to private and accessing that. It does not
596 // properly handle illegal types or vectors. The private vector loads are not
597 // scalarized, and the illegal scalars hit an assertion. This technique will not
598 // work well with large initializers, and this should eventually be
599 // removed. Initialized globals should be placed into a data section that the
600 // runtime will load into a buffer before the kernel is executed. Uses of the
601 // global need to be replaced with a pointer loaded from an implicit kernel
602 // argument into this buffer holding the copy of the data, which will remove the
603 // need for any of this.
604 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
605 const GlobalValue *GV,
606 const SDValue &InitPtr,
608 SelectionDAG &DAG) const {
609 const DataLayout *TD = getTargetMachine().getDataLayout();
611 Type *InitTy = Init->getType();
613 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
614 EVT VT = EVT::getEVT(InitTy);
615 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
616 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
617 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
618 TD->getPrefTypeAlignment(InitTy));
621 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
622 EVT VT = EVT::getEVT(CFP->getType());
623 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
624 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
625 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
626 TD->getPrefTypeAlignment(CFP->getType()));
629 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
630 const StructLayout *SL = TD->getStructLayout(ST);
632 EVT PtrVT = InitPtr.getValueType();
633 SmallVector<SDValue, 8> Chains;
635 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
636 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), PtrVT);
637 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
639 Constant *Elt = Init->getAggregateElement(I);
640 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
643 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
646 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
647 EVT PtrVT = InitPtr.getValueType();
649 unsigned NumElements;
650 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
651 NumElements = AT->getNumElements();
652 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
653 NumElements = VT->getNumElements();
655 llvm_unreachable("Unexpected type");
657 unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType());
658 SmallVector<SDValue, 8> Chains;
659 for (unsigned i = 0; i < NumElements; ++i) {
660 SDValue Offset = DAG.getConstant(i * EltSize, PtrVT);
661 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
663 Constant *Elt = Init->getAggregateElement(i);
664 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
667 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
670 if (isa<UndefValue>(Init)) {
671 EVT VT = EVT::getEVT(InitTy);
672 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
673 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
674 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
675 TD->getPrefTypeAlignment(InitTy));
679 llvm_unreachable("Unhandled constant initializer");
682 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
684 SelectionDAG &DAG) const {
686 const DataLayout *TD = getTargetMachine().getDataLayout();
687 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
688 const GlobalValue *GV = G->getGlobal();
690 switch (G->getAddressSpace()) {
691 default: llvm_unreachable("Global Address lowering not implemented for this "
693 case AMDGPUAS::LOCAL_ADDRESS: {
694 // XXX: What does the value of G->getOffset() mean?
695 assert(G->getOffset() == 0 &&
696 "Do not know what to do with an non-zero offset");
699 if (MFI->LocalMemoryObjects.count(GV) == 0) {
700 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
701 Offset = MFI->LDSSize;
702 MFI->LocalMemoryObjects[GV] = Offset;
703 // XXX: Account for alignment?
704 MFI->LDSSize += Size;
706 Offset = MFI->LocalMemoryObjects[GV];
709 return DAG.getConstant(Offset, getPointerTy(G->getAddressSpace()));
711 case AMDGPUAS::CONSTANT_ADDRESS: {
712 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
713 Type *EltType = GV->getType()->getElementType();
714 unsigned Size = TD->getTypeAllocSize(EltType);
715 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
717 MVT PrivPtrVT = getPointerTy(AMDGPUAS::PRIVATE_ADDRESS);
718 MVT ConstPtrVT = getPointerTy(AMDGPUAS::CONSTANT_ADDRESS);
720 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
721 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
723 const GlobalVariable *Var = cast<GlobalVariable>(GV);
724 if (!Var->hasInitializer()) {
725 // This has no use, but bugpoint will hit it.
726 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
729 const Constant *Init = Var->getInitializer();
730 SmallVector<SDNode*, 8> WorkList;
732 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
733 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
734 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
736 WorkList.push_back(*I);
738 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
739 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
740 E = WorkList.end(); I != E; ++I) {
741 SmallVector<SDValue, 8> Ops;
742 Ops.push_back(Chain);
743 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
744 Ops.push_back((*I)->getOperand(i));
746 DAG.UpdateNodeOperands(*I, Ops);
748 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
753 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
754 SelectionDAG &DAG) const {
755 SmallVector<SDValue, 8> Args;
756 SDValue A = Op.getOperand(0);
757 SDValue B = Op.getOperand(1);
759 DAG.ExtractVectorElements(A, Args);
760 DAG.ExtractVectorElements(B, Args);
762 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
765 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
766 SelectionDAG &DAG) const {
768 SmallVector<SDValue, 8> Args;
769 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
770 EVT VT = Op.getValueType();
771 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
772 VT.getVectorNumElements());
774 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
777 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
778 SelectionDAG &DAG) const {
780 MachineFunction &MF = DAG.getMachineFunction();
781 const AMDGPUFrameLowering *TFL =
782 static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering());
784 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
786 unsigned FrameIndex = FIN->getIndex();
787 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
788 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
792 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
793 SelectionDAG &DAG) const {
794 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
796 EVT VT = Op.getValueType();
798 switch (IntrinsicID) {
800 case AMDGPUIntrinsic::AMDGPU_abs:
801 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
802 return LowerIntrinsicIABS(Op, DAG);
803 case AMDGPUIntrinsic::AMDGPU_lrp:
804 return LowerIntrinsicLRP(Op, DAG);
805 case AMDGPUIntrinsic::AMDGPU_fract:
806 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
807 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
809 case AMDGPUIntrinsic::AMDGPU_clamp:
810 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
811 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
812 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
814 case Intrinsic::AMDGPU_div_scale: {
815 // 3rd parameter required to be a constant.
816 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
818 return DAG.getUNDEF(VT);
820 // Translate to the operands expected by the machine instruction. The
821 // first parameter must be the same as the first instruction.
822 SDValue Numerator = Op.getOperand(1);
823 SDValue Denominator = Op.getOperand(2);
824 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
826 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, VT,
827 Src0, Denominator, Numerator);
830 case Intrinsic::AMDGPU_div_fmas:
831 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
832 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
834 case Intrinsic::AMDGPU_div_fixup:
835 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
836 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
838 case Intrinsic::AMDGPU_trig_preop:
839 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
840 Op.getOperand(1), Op.getOperand(2));
842 case Intrinsic::AMDGPU_rcp:
843 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
845 case Intrinsic::AMDGPU_rsq:
846 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
848 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
849 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
851 case Intrinsic::AMDGPU_rsq_clamped:
852 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
854 case AMDGPUIntrinsic::AMDGPU_imax:
855 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
857 case AMDGPUIntrinsic::AMDGPU_umax:
858 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
860 case AMDGPUIntrinsic::AMDGPU_imin:
861 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
863 case AMDGPUIntrinsic::AMDGPU_umin:
864 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
867 case AMDGPUIntrinsic::AMDGPU_umul24:
868 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
869 Op.getOperand(1), Op.getOperand(2));
871 case AMDGPUIntrinsic::AMDGPU_imul24:
872 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
873 Op.getOperand(1), Op.getOperand(2));
875 case AMDGPUIntrinsic::AMDGPU_umad24:
876 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
877 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
879 case AMDGPUIntrinsic::AMDGPU_imad24:
880 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
881 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
883 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
884 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
886 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
887 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
889 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
890 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
892 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
893 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
895 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
896 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
901 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
902 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
907 case AMDGPUIntrinsic::AMDGPU_bfi:
908 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
913 case AMDGPUIntrinsic::AMDGPU_bfm:
914 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
918 case AMDGPUIntrinsic::AMDGPU_brev:
919 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
921 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
922 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
924 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
925 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
926 case AMDGPUIntrinsic::AMDGPU_trunc: // Legacy name.
927 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
931 ///IABS(a) = SMAX(sub(0, a), a)
932 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
933 SelectionDAG &DAG) const {
935 EVT VT = Op.getValueType();
936 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
939 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
942 /// Linear Interpolation
943 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
944 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
945 SelectionDAG &DAG) const {
947 EVT VT = Op.getValueType();
948 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
949 DAG.getConstantFP(1.0f, MVT::f32),
951 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
953 return DAG.getNode(ISD::FADD, DL, VT,
954 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
958 /// \brief Generate Min/Max node
959 SDValue AMDGPUTargetLowering::CombineMinMax(SDNode *N,
960 SelectionDAG &DAG) const {
962 EVT VT = N->getValueType(0);
964 SDValue LHS = N->getOperand(0);
965 SDValue RHS = N->getOperand(1);
966 SDValue True = N->getOperand(2);
967 SDValue False = N->getOperand(3);
968 SDValue CC = N->getOperand(4);
970 if (VT != MVT::f32 ||
971 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
975 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
989 llvm_unreachable("Operation should already be optimised!");
996 unsigned Opc = (LHS == True) ? AMDGPUISD::FMIN : AMDGPUISD::FMAX;
997 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1005 unsigned Opc = (LHS == True) ? AMDGPUISD::FMAX : AMDGPUISD::FMIN;
1006 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1008 case ISD::SETCC_INVALID:
1009 llvm_unreachable("Invalid setcc condcode!");
1014 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue &Op,
1015 SelectionDAG &DAG) const {
1016 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op);
1017 EVT MemEltVT = Load->getMemoryVT().getVectorElementType();
1018 EVT LoadVT = Op.getValueType();
1019 EVT EltVT = Op.getValueType().getVectorElementType();
1020 EVT PtrVT = Load->getBasePtr().getValueType();
1022 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1023 SmallVector<SDValue, 8> Loads;
1024 SmallVector<SDValue, 8> Chains;
1028 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1029 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1030 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8), PtrVT));
1033 = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1034 Load->getChain(), Ptr,
1035 MachinePointerInfo(Load->getMemOperand()->getValue()),
1036 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1037 Load->getAlignment());
1038 Loads.push_back(NewLoad.getValue(0));
1039 Chains.push_back(NewLoad.getValue(1));
1043 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads),
1044 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains)
1047 return DAG.getMergeValues(Ops, SL);
1050 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1051 SelectionDAG &DAG) const {
1052 StoreSDNode *Store = cast<StoreSDNode>(Op);
1053 EVT MemVT = Store->getMemoryVT();
1054 unsigned MemBits = MemVT.getSizeInBits();
1056 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1057 // truncating store into an i32 store.
1058 // XXX: We could also handle optimize other vector bitwidths.
1059 if (!MemVT.isVector() || MemBits > 32) {
1064 SDValue Value = Store->getValue();
1065 EVT VT = Value.getValueType();
1066 EVT ElemVT = VT.getVectorElementType();
1067 SDValue Ptr = Store->getBasePtr();
1068 EVT MemEltVT = MemVT.getVectorElementType();
1069 unsigned MemEltBits = MemEltVT.getSizeInBits();
1070 unsigned MemNumElements = MemVT.getVectorNumElements();
1071 unsigned PackedSize = MemVT.getStoreSizeInBits();
1072 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
1074 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1076 SDValue PackedValue;
1077 for (unsigned i = 0; i < MemNumElements; ++i) {
1078 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1079 DAG.getConstant(i, MVT::i32));
1080 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1081 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1083 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
1084 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1089 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1093 if (PackedSize < 32) {
1094 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1095 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1096 Store->getMemOperand()->getPointerInfo(),
1098 Store->isNonTemporal(), Store->isVolatile(),
1099 Store->getAlignment());
1102 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1103 Store->getMemOperand()->getPointerInfo(),
1104 Store->isVolatile(), Store->isNonTemporal(),
1105 Store->getAlignment());
1108 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1109 SelectionDAG &DAG) const {
1110 StoreSDNode *Store = cast<StoreSDNode>(Op);
1111 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1112 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1113 EVT PtrVT = Store->getBasePtr().getValueType();
1114 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1117 SmallVector<SDValue, 8> Chains;
1119 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1120 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1121 Store->getValue(), DAG.getConstant(i, MVT::i32));
1122 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT,
1123 Store->getBasePtr(),
1124 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8),
1126 Chains.push_back(DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1127 MachinePointerInfo(Store->getMemOperand()->getValue()),
1128 MemEltVT, Store->isVolatile(), Store->isNonTemporal(),
1129 Store->getAlignment()));
1131 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1134 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1136 LoadSDNode *Load = cast<LoadSDNode>(Op);
1137 ISD::LoadExtType ExtType = Load->getExtensionType();
1138 EVT VT = Op.getValueType();
1139 EVT MemVT = Load->getMemoryVT();
1141 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) {
1142 // We can do the extload to 32-bits, and then need to separately extend to
1145 SDValue ExtLoad32 = DAG.getExtLoad(ExtType, DL, MVT::i32,
1149 Load->getMemOperand());
1152 DAG.getNode(ISD::getExtForLoadExtType(ExtType), DL, VT, ExtLoad32),
1153 ExtLoad32.getValue(1)
1156 return DAG.getMergeValues(Ops, DL);
1159 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1160 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1161 // FIXME: Copied from PPC
1162 // First, load into 32 bits, then truncate to 1 bit.
1164 SDValue Chain = Load->getChain();
1165 SDValue BasePtr = Load->getBasePtr();
1166 MachineMemOperand *MMO = Load->getMemOperand();
1168 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1169 BasePtr, MVT::i8, MMO);
1172 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1176 return DAG.getMergeValues(Ops, DL);
1179 if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1180 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1184 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1185 DAG.getConstant(2, MVT::i32));
1186 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1187 Load->getChain(), Ptr,
1188 DAG.getTargetConstant(0, MVT::i32),
1190 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1192 DAG.getConstant(0x3, MVT::i32));
1193 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1194 DAG.getConstant(3, MVT::i32));
1196 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1198 EVT MemEltVT = MemVT.getScalarType();
1199 if (ExtType == ISD::SEXTLOAD) {
1200 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1203 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1207 return DAG.getMergeValues(Ops, DL);
1211 DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1215 return DAG.getMergeValues(Ops, DL);
1218 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1220 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1221 if (Result.getNode()) {
1225 StoreSDNode *Store = cast<StoreSDNode>(Op);
1226 SDValue Chain = Store->getChain();
1227 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1228 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1229 Store->getValue().getValueType().isVector()) {
1230 return SplitVectorStore(Op, DAG);
1233 EVT MemVT = Store->getMemoryVT();
1234 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1235 MemVT.bitsLT(MVT::i32)) {
1237 if (Store->getMemoryVT() == MVT::i8) {
1239 } else if (Store->getMemoryVT() == MVT::i16) {
1242 SDValue BasePtr = Store->getBasePtr();
1243 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1244 DAG.getConstant(2, MVT::i32));
1245 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1246 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
1248 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1249 DAG.getConstant(0x3, MVT::i32));
1251 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1252 DAG.getConstant(3, MVT::i32));
1254 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1257 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1259 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1260 MaskedValue, ShiftAmt);
1262 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
1264 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1265 DAG.getConstant(0xffffffff, MVT::i32));
1266 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1268 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1269 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1270 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
1275 // This is a shortcut for integer division because we have fast i32<->f32
1276 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1277 // float is enough to accurately represent up to a 24-bit integer.
1278 SDValue AMDGPUTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const {
1280 EVT VT = Op.getValueType();
1281 SDValue LHS = Op.getOperand(0);
1282 SDValue RHS = Op.getOperand(1);
1283 MVT IntVT = MVT::i32;
1284 MVT FltVT = MVT::f32;
1286 if (VT.isVector()) {
1287 unsigned NElts = VT.getVectorNumElements();
1288 IntVT = MVT::getVectorVT(MVT::i32, NElts);
1289 FltVT = MVT::getVectorVT(MVT::f32, NElts);
1292 unsigned BitSize = VT.getScalarType().getSizeInBits();
1294 // char|short jq = ia ^ ib;
1295 SDValue jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1297 // jq = jq >> (bitsize - 2)
1298 jq = DAG.getNode(ISD::SRA, DL, VT, jq, DAG.getConstant(BitSize - 2, VT));
1301 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, VT));
1304 jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
1306 // int ia = (int)LHS;
1307 SDValue ia = DAG.getSExtOrTrunc(LHS, DL, IntVT);
1309 // int ib, (int)RHS;
1310 SDValue ib = DAG.getSExtOrTrunc(RHS, DL, IntVT);
1312 // float fa = (float)ia;
1313 SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FltVT, ia);
1315 // float fb = (float)ib;
1316 SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FltVT, ib);
1318 // float fq = native_divide(fa, fb);
1319 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1320 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1323 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1325 // float fqneg = -fq;
1326 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1328 // float fr = mad(fqneg, fb, fa);
1329 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
1330 DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
1332 // int iq = (int)fq;
1333 SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, IntVT, fq);
1336 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1339 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1341 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), VT);
1343 // int cv = fr >= fb;
1344 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1346 // jq = (cv ? jq : 0);
1347 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, VT));
1350 iq = DAG.getSExtOrTrunc(iq, DL, VT);
1351 return DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1354 SDValue AMDGPUTargetLowering::LowerSDIV32(SDValue Op, SelectionDAG &DAG) const {
1356 EVT OVT = Op.getValueType();
1357 SDValue LHS = Op.getOperand(0);
1358 SDValue RHS = Op.getOperand(1);
1359 // The LowerSDIV32 function generates equivalent to the following IL.
1369 // ixor r10, r10, r11
1371 // ixor DST, r0, r10
1380 SDValue r10 = DAG.getSelectCC(DL,
1381 r0, DAG.getConstant(0, OVT),
1382 DAG.getConstant(-1, OVT),
1383 DAG.getConstant(0, OVT),
1387 SDValue r11 = DAG.getSelectCC(DL,
1388 r1, DAG.getConstant(0, OVT),
1389 DAG.getConstant(-1, OVT),
1390 DAG.getConstant(0, OVT),
1394 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1397 r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);
1400 r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1403 r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);
1406 r0 = DAG.getNode(ISD::UDIV, DL, OVT, r0, r1);
1408 // ixor r10, r10, r11
1409 r10 = DAG.getNode(ISD::XOR, DL, OVT, r10, r11);
1412 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1414 // ixor DST, r0, r10
1415 SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1419 SDValue AMDGPUTargetLowering::LowerSDIV64(SDValue Op, SelectionDAG &DAG) const {
1420 return SDValue(Op.getNode(), 0);
1423 SDValue AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {
1424 EVT OVT = Op.getValueType().getScalarType();
1426 if (OVT == MVT::i32) {
1427 if (DAG.ComputeNumSignBits(Op.getOperand(0)) > 8 &&
1428 DAG.ComputeNumSignBits(Op.getOperand(1)) > 8) {
1429 // TODO: We technically could do this for i64, but shouldn't that just be
1430 // handled by something generally reducing 64-bit division on 32-bit
1431 // values to 32-bit?
1432 return LowerSDIV24(Op, DAG);
1435 return LowerSDIV32(Op, DAG);
1438 assert(OVT == MVT::i64);
1439 return LowerSDIV64(Op, DAG);
1442 SDValue AMDGPUTargetLowering::LowerSREM32(SDValue Op, SelectionDAG &DAG) const {
1444 EVT OVT = Op.getValueType();
1445 SDValue LHS = Op.getOperand(0);
1446 SDValue RHS = Op.getOperand(1);
1447 // The LowerSREM32 function generates equivalent to the following IL.
1457 // umul r20, r20, r1
1460 // ixor DST, r0, r10
1469 SDValue r10 = DAG.getSetCC(DL, OVT, r0, DAG.getConstant(0, OVT), ISD::SETLT);
1472 SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT);
1475 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1478 r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);
1481 r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1484 r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);
1487 SDValue r20 = DAG.getNode(ISD::UREM, DL, OVT, r0, r1);
1489 // umul r20, r20, r1
1490 r20 = DAG.getNode(AMDGPUISD::UMUL, DL, OVT, r20, r1);
1493 r0 = DAG.getNode(ISD::SUB, DL, OVT, r0, r20);
1496 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1498 // ixor DST, r0, r10
1499 SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1503 SDValue AMDGPUTargetLowering::LowerSREM64(SDValue Op, SelectionDAG &DAG) const {
1504 return SDValue(Op.getNode(), 0);
1507 SDValue AMDGPUTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const {
1508 EVT OVT = Op.getValueType();
1510 if (OVT.getScalarType() == MVT::i64)
1511 return LowerSREM64(Op, DAG);
1513 if (OVT.getScalarType() == MVT::i32)
1514 return LowerSREM32(Op, DAG);
1516 return SDValue(Op.getNode(), 0);
1519 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1520 SelectionDAG &DAG) const {
1522 EVT VT = Op.getValueType();
1524 SDValue Num = Op.getOperand(0);
1525 SDValue Den = Op.getOperand(1);
1527 // RCP = URECIP(Den) = 2^32 / Den + e
1528 // e is rounding error.
1529 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1531 // RCP_LO = umulo(RCP, Den) */
1532 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
1534 // RCP_HI = mulhu (RCP, Den) */
1535 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1537 // NEG_RCP_LO = -RCP_LO
1538 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1541 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1542 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1545 // Calculate the rounding error from the URECIP instruction
1546 // E = mulhu(ABS_RCP_LO, RCP)
1547 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1549 // RCP_A_E = RCP + E
1550 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1552 // RCP_S_E = RCP - E
1553 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1555 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1556 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1559 // Quotient = mulhu(Tmp0, Num)
1560 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1562 // Num_S_Remainder = Quotient * Den
1563 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
1565 // Remainder = Num - Num_S_Remainder
1566 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1568 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1569 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1570 DAG.getConstant(-1, VT),
1571 DAG.getConstant(0, VT),
1573 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1574 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1576 DAG.getConstant(-1, VT),
1577 DAG.getConstant(0, VT),
1579 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1580 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1583 // Calculate Division result:
1585 // Quotient_A_One = Quotient + 1
1586 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1587 DAG.getConstant(1, VT));
1589 // Quotient_S_One = Quotient - 1
1590 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1591 DAG.getConstant(1, VT));
1593 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1594 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1595 Quotient, Quotient_A_One, ISD::SETEQ);
1597 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1598 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1599 Quotient_S_One, Div, ISD::SETEQ);
1601 // Calculate Rem result:
1603 // Remainder_S_Den = Remainder - Den
1604 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1606 // Remainder_A_Den = Remainder + Den
1607 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1609 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1610 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1611 Remainder, Remainder_S_Den, ISD::SETEQ);
1613 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1614 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1615 Remainder_A_Den, Rem, ISD::SETEQ);
1620 return DAG.getMergeValues(Ops, DL);
1623 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1624 SelectionDAG &DAG) const {
1626 EVT VT = Op.getValueType();
1628 SDValue Zero = DAG.getConstant(0, VT);
1629 SDValue NegOne = DAG.getConstant(-1, VT);
1631 SDValue LHS = Op.getOperand(0);
1632 SDValue RHS = Op.getOperand(1);
1634 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1635 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1636 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1637 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1639 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1640 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1642 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1643 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1645 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1646 SDValue Rem = Div.getValue(1);
1648 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1649 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1651 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1652 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1658 return DAG.getMergeValues(Res, DL);
1661 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1663 SDValue Src = Op.getOperand(0);
1665 // result = trunc(src)
1666 // if (src > 0.0 && src != result)
1669 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1671 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1672 const SDValue One = DAG.getConstantFP(1.0, MVT::f64);
1674 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1676 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1677 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1678 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1680 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1681 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1684 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1686 SDValue Src = Op.getOperand(0);
1688 assert(Op.getValueType() == MVT::f64);
1690 const SDValue Zero = DAG.getConstant(0, MVT::i32);
1691 const SDValue One = DAG.getConstant(1, MVT::i32);
1693 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1695 // Extract the upper half, since this is where we will find the sign and
1697 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1699 const unsigned FractBits = 52;
1700 const unsigned ExpBits = 11;
1702 // Extract the exponent.
1703 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_I32, SL, MVT::i32,
1705 DAG.getConstant(FractBits - 32, MVT::i32),
1706 DAG.getConstant(ExpBits, MVT::i32));
1707 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1708 DAG.getConstant(1023, MVT::i32));
1710 // Extract the sign bit.
1711 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, MVT::i32);
1712 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1714 // Extend back to to 64-bits.
1715 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1717 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1719 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1720 const SDValue FractMask
1721 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, MVT::i64);
1723 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1724 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1725 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1727 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32);
1729 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, MVT::i32);
1731 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1732 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1734 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1735 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1737 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1740 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1742 SDValue Src = Op.getOperand(0);
1744 assert(Op.getValueType() == MVT::f64);
1746 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
1747 SDValue C1 = DAG.getConstantFP(C1Val, MVT::f64);
1748 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
1750 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
1751 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
1753 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
1755 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
1756 SDValue C2 = DAG.getConstantFP(C2Val, MVT::f64);
1758 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1759 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
1761 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
1764 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
1765 // FNEARBYINT and FRINT are the same, except in their handling of FP
1766 // exceptions. Those aren't really meaningful for us, and OpenCL only has
1767 // rint, so just treat them as equivalent.
1768 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
1771 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
1773 SDValue Src = Op.getOperand(0);
1775 // result = trunc(src);
1776 // if (src < 0.0 && src != result)
1779 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1781 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1782 const SDValue NegOne = DAG.getConstantFP(-1.0, MVT::f64);
1784 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1786 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
1787 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1788 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1790 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
1791 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1794 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
1795 SelectionDAG &DAG) const {
1796 SDValue S0 = Op.getOperand(0);
1798 if (Op.getValueType() != MVT::f32 || S0.getValueType() != MVT::i64)
1801 // f32 uint_to_fp i64
1802 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1803 DAG.getConstant(0, MVT::i32));
1804 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
1805 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1806 DAG.getConstant(1, MVT::i32));
1807 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
1808 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
1809 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
1810 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
1813 SDValue AMDGPUTargetLowering::ExpandSIGN_EXTEND_INREG(SDValue Op,
1815 SelectionDAG &DAG) const {
1816 MVT VT = Op.getSimpleValueType();
1818 SDValue Shift = DAG.getConstant(BitsDiff, VT);
1819 // Shift left by 'Shift' bits.
1820 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Op.getOperand(0), Shift);
1821 // Signed shift Right by 'Shift' bits.
1822 return DAG.getNode(ISD::SRA, DL, VT, Shl, Shift);
1825 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
1826 SelectionDAG &DAG) const {
1827 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1828 MVT VT = Op.getSimpleValueType();
1829 MVT ScalarVT = VT.getScalarType();
1834 SDValue Src = Op.getOperand(0);
1837 // TODO: Don't scalarize on Evergreen?
1838 unsigned NElts = VT.getVectorNumElements();
1839 SmallVector<SDValue, 8> Args;
1840 DAG.ExtractVectorElements(Src, Args, 0, NElts);
1842 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
1843 for (unsigned I = 0; I < NElts; ++I)
1844 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
1846 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
1849 //===----------------------------------------------------------------------===//
1850 // Custom DAG optimizations
1851 //===----------------------------------------------------------------------===//
1853 static bool isU24(SDValue Op, SelectionDAG &DAG) {
1854 APInt KnownZero, KnownOne;
1855 EVT VT = Op.getValueType();
1856 DAG.computeKnownBits(Op, KnownZero, KnownOne);
1858 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
1861 static bool isI24(SDValue Op, SelectionDAG &DAG) {
1862 EVT VT = Op.getValueType();
1864 // In order for this to be a signed 24-bit value, bit 23, must
1866 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
1867 // as unsigned 24-bit values.
1868 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
1871 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
1873 SelectionDAG &DAG = DCI.DAG;
1874 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1875 EVT VT = Op.getValueType();
1877 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
1878 APInt KnownZero, KnownOne;
1879 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
1880 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
1881 DCI.CommitTargetLoweringOpt(TLO);
1884 template <typename IntTy>
1885 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
1886 uint32_t Offset, uint32_t Width) {
1887 if (Width + Offset < 32) {
1888 IntTy Result = (Src0 << (32 - Offset - Width)) >> (32 - Width);
1889 return DAG.getConstant(Result, MVT::i32);
1892 return DAG.getConstant(Src0 >> Offset, MVT::i32);
1895 static bool usesAllNormalStores(SDNode *LoadVal) {
1896 for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
1897 if (!ISD::isNormalStore(*I))
1904 // If we have a copy of an illegal type, replace it with a load / store of an
1905 // equivalently sized legal type. This avoids intermediate bit pack / unpack
1906 // instructions emitted when handling extloads and truncstores. Ideally we could
1907 // recognize the pack / unpack pattern to eliminate it.
1908 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
1909 DAGCombinerInfo &DCI) const {
1910 if (!DCI.isBeforeLegalize())
1913 StoreSDNode *SN = cast<StoreSDNode>(N);
1914 SDValue Value = SN->getValue();
1915 EVT VT = Value.getValueType();
1917 if (isTypeLegal(VT) || SN->isVolatile() || !ISD::isNormalLoad(Value.getNode()))
1920 LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
1921 if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
1924 EVT MemVT = LoadVal->getMemoryVT();
1927 SelectionDAG &DAG = DCI.DAG;
1928 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
1930 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
1932 LoadVal->getChain(),
1933 LoadVal->getBasePtr(),
1934 LoadVal->getOffset(),
1936 LoadVal->getMemOperand());
1938 SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
1939 DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
1941 return DAG.getStore(SN->getChain(), SL, NewLoad,
1942 SN->getBasePtr(), SN->getMemOperand());
1945 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
1946 DAGCombinerInfo &DCI) const {
1947 EVT VT = N->getValueType(0);
1949 if (VT.isVector() || VT.getSizeInBits() > 32)
1952 SelectionDAG &DAG = DCI.DAG;
1955 SDValue N0 = N->getOperand(0);
1956 SDValue N1 = N->getOperand(1);
1959 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
1960 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
1961 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
1962 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
1963 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
1964 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
1965 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
1966 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
1971 // We need to use sext even for MUL_U24, because MUL_U24 is used
1972 // for signed multiply of 8 and 16-bit types.
1973 return DAG.getSExtOrTrunc(Mul, DL, VT);
1976 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
1977 DAGCombinerInfo &DCI) const {
1978 SelectionDAG &DAG = DCI.DAG;
1981 switch(N->getOpcode()) {
1984 return performMulCombine(N, DCI);
1985 case AMDGPUISD::MUL_I24:
1986 case AMDGPUISD::MUL_U24: {
1987 SDValue N0 = N->getOperand(0);
1988 SDValue N1 = N->getOperand(1);
1989 simplifyI24(N0, DCI);
1990 simplifyI24(N1, DCI);
1993 case ISD::SELECT_CC: {
1994 return CombineMinMax(N, DAG);
1996 case AMDGPUISD::BFE_I32:
1997 case AMDGPUISD::BFE_U32: {
1998 assert(!N->getValueType(0).isVector() &&
1999 "Vector handling of BFE not implemented");
2000 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2004 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2006 return DAG.getConstant(0, MVT::i32);
2008 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2012 SDValue BitsFrom = N->getOperand(0);
2013 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2015 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2017 if (OffsetVal == 0) {
2018 // This is already sign / zero extended, so try to fold away extra BFEs.
2019 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2021 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2022 if (OpSignBits >= SignBits)
2025 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2027 // This is a sign_extend_inreg. Replace it to take advantage of existing
2028 // DAG Combines. If not eliminated, we will match back to BFE during
2031 // TODO: The sext_inreg of extended types ends, although we can could
2032 // handle them in a single BFE.
2033 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2034 DAG.getValueType(SmallVT));
2037 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2040 if (ConstantSDNode *Val = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
2042 return constantFoldBFE<int32_t>(DAG,
2043 Val->getSExtValue(),
2048 return constantFoldBFE<uint32_t>(DAG,
2049 Val->getZExtValue(),
2054 APInt Demanded = APInt::getBitsSet(32,
2056 OffsetVal + WidthVal);
2058 if ((OffsetVal + WidthVal) >= 32) {
2059 SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32);
2060 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2061 BitsFrom, ShiftVal);
2064 APInt KnownZero, KnownOne;
2065 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2066 !DCI.isBeforeLegalizeOps());
2067 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2068 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2069 TLI.SimplifyDemandedBits(BitsFrom, Demanded, KnownZero, KnownOne, TLO)) {
2070 DCI.CommitTargetLoweringOpt(TLO);
2077 return performStoreCombine(N, DCI);
2082 //===----------------------------------------------------------------------===//
2084 //===----------------------------------------------------------------------===//
2086 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2089 const SmallVectorImpl<ISD::InputArg> &Ins,
2090 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2092 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2093 if (Ins[i].ArgVT == Ins[i].VT) {
2094 OrigIns.push_back(Ins[i]);
2099 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2100 // Vector has been split into scalars.
2101 VT = Ins[i].ArgVT.getVectorElementType();
2102 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2103 Ins[i].ArgVT.getVectorElementType() !=
2104 Ins[i].VT.getVectorElementType()) {
2105 // Vector elements have been promoted
2108 // Vector has been spilt into smaller vectors.
2112 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2113 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2114 OrigIns.push_back(Arg);
2118 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2119 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2120 return CFP->isExactlyValue(1.0);
2122 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2123 return C->isAllOnesValue();
2128 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2129 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2130 return CFP->getValueAPF().isZero();
2132 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2133 return C->isNullValue();
2138 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2139 const TargetRegisterClass *RC,
2140 unsigned Reg, EVT VT) const {
2141 MachineFunction &MF = DAG.getMachineFunction();
2142 MachineRegisterInfo &MRI = MF.getRegInfo();
2143 unsigned VirtualRegister;
2144 if (!MRI.isLiveIn(Reg)) {
2145 VirtualRegister = MRI.createVirtualRegister(RC);
2146 MRI.addLiveIn(Reg, VirtualRegister);
2148 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2150 return DAG.getRegister(VirtualRegister, VT);
2153 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2155 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2157 default: return nullptr;
2159 NODE_NAME_CASE(CALL);
2160 NODE_NAME_CASE(UMUL);
2161 NODE_NAME_CASE(RET_FLAG);
2162 NODE_NAME_CASE(BRANCH_COND);
2165 NODE_NAME_CASE(DWORDADDR)
2166 NODE_NAME_CASE(FRACT)
2167 NODE_NAME_CASE(CLAMP)
2168 NODE_NAME_CASE(FMAX)
2169 NODE_NAME_CASE(SMAX)
2170 NODE_NAME_CASE(UMAX)
2171 NODE_NAME_CASE(FMIN)
2172 NODE_NAME_CASE(SMIN)
2173 NODE_NAME_CASE(UMIN)
2174 NODE_NAME_CASE(URECIP)
2175 NODE_NAME_CASE(DIV_SCALE)
2176 NODE_NAME_CASE(DIV_FMAS)
2177 NODE_NAME_CASE(DIV_FIXUP)
2178 NODE_NAME_CASE(TRIG_PREOP)
2181 NODE_NAME_CASE(RSQ_LEGACY)
2182 NODE_NAME_CASE(RSQ_CLAMPED)
2183 NODE_NAME_CASE(DOT4)
2184 NODE_NAME_CASE(BFE_U32)
2185 NODE_NAME_CASE(BFE_I32)
2188 NODE_NAME_CASE(BREV)
2189 NODE_NAME_CASE(MUL_U24)
2190 NODE_NAME_CASE(MUL_I24)
2191 NODE_NAME_CASE(MAD_U24)
2192 NODE_NAME_CASE(MAD_I24)
2193 NODE_NAME_CASE(EXPORT)
2194 NODE_NAME_CASE(CONST_ADDRESS)
2195 NODE_NAME_CASE(REGISTER_LOAD)
2196 NODE_NAME_CASE(REGISTER_STORE)
2197 NODE_NAME_CASE(LOAD_CONSTANT)
2198 NODE_NAME_CASE(LOAD_INPUT)
2199 NODE_NAME_CASE(SAMPLE)
2200 NODE_NAME_CASE(SAMPLEB)
2201 NODE_NAME_CASE(SAMPLED)
2202 NODE_NAME_CASE(SAMPLEL)
2203 NODE_NAME_CASE(CVT_F32_UBYTE0)
2204 NODE_NAME_CASE(CVT_F32_UBYTE1)
2205 NODE_NAME_CASE(CVT_F32_UBYTE2)
2206 NODE_NAME_CASE(CVT_F32_UBYTE3)
2207 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2208 NODE_NAME_CASE(CONST_DATA_PTR)
2209 NODE_NAME_CASE(STORE_MSKOR)
2210 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2214 static void computeKnownBitsForMinMax(const SDValue Op0,
2218 const SelectionDAG &DAG,
2220 APInt Op0Zero, Op0One;
2221 APInt Op1Zero, Op1One;
2222 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2223 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2225 KnownZero = Op0Zero & Op1Zero;
2226 KnownOne = Op0One & Op1One;
2229 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2233 const SelectionDAG &DAG,
2234 unsigned Depth) const {
2236 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2240 unsigned Opc = Op.getOpcode();
2245 case ISD::INTRINSIC_WO_CHAIN: {
2246 // FIXME: The intrinsic should just use the node.
2247 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2248 case AMDGPUIntrinsic::AMDGPU_imax:
2249 case AMDGPUIntrinsic::AMDGPU_umax:
2250 case AMDGPUIntrinsic::AMDGPU_imin:
2251 case AMDGPUIntrinsic::AMDGPU_umin:
2252 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2253 KnownZero, KnownOne, DAG, Depth);
2261 case AMDGPUISD::SMAX:
2262 case AMDGPUISD::UMAX:
2263 case AMDGPUISD::SMIN:
2264 case AMDGPUISD::UMIN:
2265 computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
2266 KnownZero, KnownOne, DAG, Depth);
2269 case AMDGPUISD::BFE_I32:
2270 case AMDGPUISD::BFE_U32: {
2271 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2275 unsigned BitWidth = 32;
2276 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2278 KnownZero = APInt::getAllOnesValue(BitWidth);
2279 KnownOne = APInt::getNullValue(BitWidth);
2283 // FIXME: This could do a lot more. If offset is 0, should be the same as
2284 // sign_extend_inreg implementation, but that involves duplicating it.
2285 if (Opc == AMDGPUISD::BFE_I32)
2286 KnownOne = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2288 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2295 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2297 const SelectionDAG &DAG,
2298 unsigned Depth) const {
2299 switch (Op.getOpcode()) {
2300 case AMDGPUISD::BFE_I32: {
2301 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2305 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2306 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2307 if (!Offset || !Offset->isNullValue())
2310 // TODO: Could probably figure something out with non-0 offsets.
2311 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2312 return std::max(SignBits, Op0SignBits);
2315 case AMDGPUISD::BFE_U32: {
2316 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2317 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;