1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPURegisterInfo.h"
20 #include "AMDGPUSubtarget.h"
21 #include "AMDILIntrinsicInfo.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/DiagnosticInfo.h"
32 #include "llvm/IR/DiagnosticPrinter.h"
38 /// Diagnostic information for unimplemented or unsupported feature reporting.
39 class DiagnosticInfoUnsupported : public DiagnosticInfo {
41 const Twine &Description;
46 static int getKindID() {
48 KindID = llvm::getNextAvailablePluginDiagnosticKind();
53 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
54 DiagnosticSeverity Severity = DS_Error)
55 : DiagnosticInfo(getKindID(), Severity),
59 const Function &getFunction() const { return Fn; }
60 const Twine &getDescription() const { return Description; }
62 void print(DiagnosticPrinter &DP) const override {
63 DP << "unsupported " << getDescription() << " in " << Fn.getName();
66 static bool classof(const DiagnosticInfo *DI) {
67 return DI->getKind() == getKindID();
71 int DiagnosticInfoUnsupported::KindID = 0;
75 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
76 CCValAssign::LocInfo LocInfo,
77 ISD::ArgFlagsTy ArgFlags, CCState &State) {
78 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
79 ArgFlags.getOrigAlign());
80 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
85 #include "AMDGPUGenCallingConv.inc"
87 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
88 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
90 Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
92 // Initialize target lowering borrowed from AMDIL
95 // We need to custom lower some of the intrinsics
96 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
98 // Library functions. These default to Expand, but we have instructions
100 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
101 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
102 setOperationAction(ISD::FPOW, MVT::f32, Legal);
103 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
104 setOperationAction(ISD::FABS, MVT::f32, Legal);
105 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
106 setOperationAction(ISD::FRINT, MVT::f32, Legal);
107 setOperationAction(ISD::FROUND, MVT::f32, Legal);
108 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
110 // The hardware supports ROTR, but not ROTL
111 setOperationAction(ISD::ROTL, MVT::i32, Expand);
113 // Lower floating point store/load to integer store/load to reduce the number
114 // of patterns in tablegen.
115 setOperationAction(ISD::STORE, MVT::f32, Promote);
116 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
118 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
119 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
121 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
122 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
124 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
125 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
127 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
128 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
130 setOperationAction(ISD::STORE, MVT::f64, Promote);
131 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
133 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
134 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
136 // Custom lowering of vector stores is required for local address space
138 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
139 // XXX: Native v2i32 local address space stores are possible, but not
140 // currently implemented.
141 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
143 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
144 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
145 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
147 // XXX: This can be change to Custom, once ExpandVectorStores can
148 // handle 64-bit stores.
149 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
151 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
152 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
153 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
154 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
155 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
158 setOperationAction(ISD::LOAD, MVT::f32, Promote);
159 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
161 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
162 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
164 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
165 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
167 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
168 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
170 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
171 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
173 setOperationAction(ISD::LOAD, MVT::f64, Promote);
174 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
176 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
177 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
179 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
180 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
181 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
182 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
183 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
184 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
185 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
186 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
187 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
188 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
190 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
191 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
192 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
193 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
194 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
195 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
196 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
197 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
198 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
199 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
200 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
201 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
203 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
205 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
207 setOperationAction(ISD::FNEG, MVT::v2f32, Expand);
208 setOperationAction(ISD::FNEG, MVT::v4f32, Expand);
210 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
212 setOperationAction(ISD::MUL, MVT::i64, Expand);
213 setOperationAction(ISD::SUB, MVT::i64, Expand);
215 setOperationAction(ISD::UDIV, MVT::i32, Expand);
216 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
217 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
218 setOperationAction(ISD::UREM, MVT::i32, Expand);
219 setOperationAction(ISD::VSELECT, MVT::v2f32, Expand);
220 setOperationAction(ISD::VSELECT, MVT::v4f32, Expand);
222 static const MVT::SimpleValueType IntTypes[] = {
223 MVT::v2i32, MVT::v4i32
225 const size_t NumIntTypes = array_lengthof(IntTypes);
227 for (unsigned int x = 0; x < NumIntTypes; ++x) {
228 MVT::SimpleValueType VT = IntTypes[x];
229 //Expand the following operations for the current type by default
230 setOperationAction(ISD::ADD, VT, Expand);
231 setOperationAction(ISD::AND, VT, Expand);
232 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
233 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
234 setOperationAction(ISD::MUL, VT, Expand);
235 setOperationAction(ISD::OR, VT, Expand);
236 setOperationAction(ISD::SHL, VT, Expand);
237 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
238 setOperationAction(ISD::SRL, VT, Expand);
239 setOperationAction(ISD::SRA, VT, Expand);
240 setOperationAction(ISD::SUB, VT, Expand);
241 setOperationAction(ISD::UDIV, VT, Expand);
242 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
243 setOperationAction(ISD::UREM, VT, Expand);
244 setOperationAction(ISD::SELECT, VT, Expand);
245 setOperationAction(ISD::VSELECT, VT, Expand);
246 setOperationAction(ISD::XOR, VT, Expand);
249 static const MVT::SimpleValueType FloatTypes[] = {
250 MVT::v2f32, MVT::v4f32
252 const size_t NumFloatTypes = array_lengthof(FloatTypes);
254 for (unsigned int x = 0; x < NumFloatTypes; ++x) {
255 MVT::SimpleValueType VT = FloatTypes[x];
256 setOperationAction(ISD::FABS, VT, Expand);
257 setOperationAction(ISD::FADD, VT, Expand);
258 setOperationAction(ISD::FCOS, VT, Expand);
259 setOperationAction(ISD::FDIV, VT, Expand);
260 setOperationAction(ISD::FPOW, VT, Expand);
261 setOperationAction(ISD::FFLOOR, VT, Expand);
262 setOperationAction(ISD::FTRUNC, VT, Expand);
263 setOperationAction(ISD::FMUL, VT, Expand);
264 setOperationAction(ISD::FRINT, VT, Expand);
265 setOperationAction(ISD::FSQRT, VT, Expand);
266 setOperationAction(ISD::FSIN, VT, Expand);
267 setOperationAction(ISD::FSUB, VT, Expand);
268 setOperationAction(ISD::SELECT, VT, Expand);
271 setTargetDAGCombine(ISD::MUL);
272 setTargetDAGCombine(ISD::SELECT_CC);
275 //===----------------------------------------------------------------------===//
276 // Target Information
277 //===----------------------------------------------------------------------===//
279 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
283 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
285 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
288 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
289 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
291 return ((LScalarSize <= CastScalarSize) ||
292 (CastScalarSize >= 32) ||
296 //===---------------------------------------------------------------------===//
298 //===---------------------------------------------------------------------===//
300 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
301 assert(VT.isFloatingPoint());
302 return VT == MVT::f32;
305 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
306 assert(VT.isFloatingPoint());
307 return VT == MVT::f32;
310 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
311 // Truncate is just accessing a subregister.
312 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
315 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
316 // Truncate is just accessing a subregister.
317 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
318 (Dest->getPrimitiveSizeInBits() % 32 == 0);
321 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
322 const DataLayout *DL = getDataLayout();
323 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
324 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
326 return SrcSize == 32 && DestSize == 64;
329 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
330 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
331 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
332 // this will enable reducing 64-bit operations the 32-bit, which is always
334 return Src == MVT::i32 && Dest == MVT::i64;
337 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
338 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
339 // limited number of native 64-bit operations. Shrinking an operation to fit
340 // in a single 32-bit register should always be helpful. As currently used,
341 // this is much less general than the name suggests, and is only used in
342 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
343 // not profitable, and may actually be harmful.
344 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
347 //===---------------------------------------------------------------------===//
348 // TargetLowering Callbacks
349 //===---------------------------------------------------------------------===//
351 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
352 const SmallVectorImpl<ISD::InputArg> &Ins) const {
354 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
357 SDValue AMDGPUTargetLowering::LowerReturn(
359 CallingConv::ID CallConv,
361 const SmallVectorImpl<ISD::OutputArg> &Outs,
362 const SmallVectorImpl<SDValue> &OutVals,
363 SDLoc DL, SelectionDAG &DAG) const {
364 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
367 //===---------------------------------------------------------------------===//
368 // Target specific lowering
369 //===---------------------------------------------------------------------===//
371 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
372 SmallVectorImpl<SDValue> &InVals) const {
373 SDValue Callee = CLI.Callee;
374 SelectionDAG &DAG = CLI.DAG;
376 const Function &Fn = *DAG.getMachineFunction().getFunction();
378 StringRef FuncName("<unknown>");
380 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
381 FuncName = G->getSymbol();
382 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
383 FuncName = G->getGlobal()->getName();
385 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
386 DAG.getContext()->diagnose(NoCalls);
390 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
392 switch (Op.getOpcode()) {
394 Op.getNode()->dump();
395 llvm_unreachable("Custom lowering code for this"
396 "instruction is not implemented yet!");
398 // AMDIL DAG lowering
399 case ISD::SDIV: return LowerSDIV(Op, DAG);
400 case ISD::SREM: return LowerSREM(Op, DAG);
401 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
402 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
403 // AMDGPU DAG lowering
404 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
405 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
406 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
407 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
408 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
409 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
414 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
415 SmallVectorImpl<SDValue> &Results,
416 SelectionDAG &DAG) const {
417 switch (N->getOpcode()) {
418 case ISD::SIGN_EXTEND_INREG:
419 // Different parts of legalization seem to interpret which type of
420 // sign_extend_inreg is the one to check for custom lowering. The extended
421 // from type is what really matters, but some places check for custom
422 // lowering of the result type. This results in trying to use
423 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
424 // nothing here and let the illegal result integer be handled normally.
427 SDValue Op = SDValue(N, 0);
429 EVT VT = Op.getValueType();
430 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
431 N->getOperand(0), N->getOperand(1));
432 Results.push_back(UDIVREM);
436 SDValue Op = SDValue(N, 0);
438 EVT VT = Op.getValueType();
439 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
440 N->getOperand(0), N->getOperand(1));
441 Results.push_back(UDIVREM.getValue(1));
445 SDValue Op = SDValue(N, 0);
447 EVT VT = Op.getValueType();
448 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
450 SDValue one = DAG.getConstant(1, HalfVT);
451 SDValue zero = DAG.getConstant(0, HalfVT);
454 SDValue LHS = N->getOperand(0);
455 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
456 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
458 SDValue RHS = N->getOperand(1);
459 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
460 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
462 // Get Speculative values
463 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
464 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
466 SDValue REM_Hi = zero;
467 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
469 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
470 SDValue DIV_Lo = zero;
472 const unsigned halfBitWidth = HalfVT.getSizeInBits();
474 for (unsigned i = 0; i < halfBitWidth; ++i) {
475 SDValue POS = DAG.getConstant(halfBitWidth - i - 1, HalfVT);
476 // Get Value of high bit
478 if (halfBitWidth == 32 && Subtarget->hasBFE()) {
479 HBit = DAG.getNode(AMDGPUISD::BFE_U32, DL, HalfVT, LHS_Lo, POS, one);
481 HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
482 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
485 SDValue Carry = DAG.getNode(ISD::SRL, DL, HalfVT, REM_Lo,
486 DAG.getConstant(halfBitWidth - 1, HalfVT));
487 REM_Hi = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Hi, one);
488 REM_Hi = DAG.getNode(ISD::OR, DL, HalfVT, REM_Hi, Carry);
490 REM_Lo = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Lo, one);
491 REM_Lo = DAG.getNode(ISD::OR, DL, HalfVT, REM_Lo, HBit);
494 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
496 SDValue BIT = DAG.getConstant(1 << (halfBitWidth - i - 1), HalfVT);
497 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETGE);
499 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
503 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
505 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETGE);
506 REM_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, zero);
507 REM_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, one);
510 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
511 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
512 Results.push_back(DIV);
513 Results.push_back(REM);
521 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
522 const GlobalValue *GV,
523 const SDValue &InitPtr,
525 SelectionDAG &DAG) const {
526 const DataLayout *TD = getTargetMachine().getDataLayout();
528 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
529 EVT VT = EVT::getEVT(CI->getType());
530 PointerType *PtrTy = PointerType::get(CI->getType(), 0);
531 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
532 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
533 TD->getPrefTypeAlignment(CI->getType()));
536 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
537 EVT VT = EVT::getEVT(CFP->getType());
538 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
539 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
540 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
541 TD->getPrefTypeAlignment(CFP->getType()));
544 if (Init->getType()->isAggregateType()) {
545 EVT PtrVT = InitPtr.getValueType();
546 unsigned NumElements = Init->getType()->getArrayNumElements();
547 SmallVector<SDValue, 8> Chains;
548 for (unsigned i = 0; i < NumElements; ++i) {
549 SDValue Offset = DAG.getConstant(i * TD->getTypeAllocSize(
550 Init->getType()->getArrayElementType()), PtrVT);
551 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
552 Chains.push_back(LowerConstantInitializer(Init->getAggregateElement(i),
553 GV, Ptr, Chain, DAG));
556 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
560 llvm_unreachable("Unhandled constant initializer");
563 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
565 SelectionDAG &DAG) const {
567 const DataLayout *TD = getTargetMachine().getDataLayout();
568 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
569 const GlobalValue *GV = G->getGlobal();
571 switch (G->getAddressSpace()) {
572 default: llvm_unreachable("Global Address lowering not implemented for this "
574 case AMDGPUAS::LOCAL_ADDRESS: {
575 // XXX: What does the value of G->getOffset() mean?
576 assert(G->getOffset() == 0 &&
577 "Do not know what to do with an non-zero offset");
580 if (MFI->LocalMemoryObjects.count(GV) == 0) {
581 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
582 Offset = MFI->LDSSize;
583 MFI->LocalMemoryObjects[GV] = Offset;
584 // XXX: Account for alignment?
585 MFI->LDSSize += Size;
587 Offset = MFI->LocalMemoryObjects[GV];
590 return DAG.getConstant(Offset, getPointerTy(G->getAddressSpace()));
592 case AMDGPUAS::CONSTANT_ADDRESS: {
593 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
594 Type *EltType = GV->getType()->getElementType();
595 unsigned Size = TD->getTypeAllocSize(EltType);
596 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
598 const GlobalVariable *Var = dyn_cast<GlobalVariable>(GV);
599 const Constant *Init = Var->getInitializer();
600 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
601 SDValue InitPtr = DAG.getFrameIndex(FI,
602 getPointerTy(AMDGPUAS::PRIVATE_ADDRESS));
603 SmallVector<SDNode*, 8> WorkList;
605 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
606 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
607 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
609 WorkList.push_back(*I);
611 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
612 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
613 E = WorkList.end(); I != E; ++I) {
614 SmallVector<SDValue, 8> Ops;
615 Ops.push_back(Chain);
616 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
617 Ops.push_back((*I)->getOperand(i));
619 DAG.UpdateNodeOperands(*I, Ops);
621 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op),
622 getPointerTy(AMDGPUAS::CONSTANT_ADDRESS));
627 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
628 SelectionDAG &DAG) const {
629 SmallVector<SDValue, 8> Args;
630 SDValue A = Op.getOperand(0);
631 SDValue B = Op.getOperand(1);
633 DAG.ExtractVectorElements(A, Args);
634 DAG.ExtractVectorElements(B, Args);
636 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
639 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
640 SelectionDAG &DAG) const {
642 SmallVector<SDValue, 8> Args;
643 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
644 EVT VT = Op.getValueType();
645 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
646 VT.getVectorNumElements());
648 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
651 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
652 SelectionDAG &DAG) const {
654 MachineFunction &MF = DAG.getMachineFunction();
655 const AMDGPUFrameLowering *TFL =
656 static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering());
658 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op);
661 unsigned FrameIndex = FIN->getIndex();
662 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
663 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
667 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
668 SelectionDAG &DAG) const {
669 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
671 EVT VT = Op.getValueType();
673 switch (IntrinsicID) {
675 case AMDGPUIntrinsic::AMDIL_abs:
676 return LowerIntrinsicIABS(Op, DAG);
677 case AMDGPUIntrinsic::AMDIL_exp:
678 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
679 case AMDGPUIntrinsic::AMDGPU_lrp:
680 return LowerIntrinsicLRP(Op, DAG);
681 case AMDGPUIntrinsic::AMDIL_fraction:
682 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
683 case AMDGPUIntrinsic::AMDIL_max:
684 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
686 case AMDGPUIntrinsic::AMDGPU_imax:
687 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
689 case AMDGPUIntrinsic::AMDGPU_umax:
690 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
692 case AMDGPUIntrinsic::AMDIL_min:
693 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
695 case AMDGPUIntrinsic::AMDGPU_imin:
696 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
698 case AMDGPUIntrinsic::AMDGPU_umin:
699 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
702 case AMDGPUIntrinsic::AMDGPU_umul24:
703 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
704 Op.getOperand(1), Op.getOperand(2));
706 case AMDGPUIntrinsic::AMDGPU_imul24:
707 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
708 Op.getOperand(1), Op.getOperand(2));
710 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
711 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
716 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
717 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
722 case AMDGPUIntrinsic::AMDGPU_bfi:
723 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
728 case AMDGPUIntrinsic::AMDGPU_bfm:
729 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
733 case AMDGPUIntrinsic::AMDIL_round_nearest:
734 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
738 ///IABS(a) = SMAX(sub(0, a), a)
739 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
740 SelectionDAG &DAG) const {
742 EVT VT = Op.getValueType();
743 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
746 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
749 /// Linear Interpolation
750 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
751 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
752 SelectionDAG &DAG) const {
754 EVT VT = Op.getValueType();
755 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
756 DAG.getConstantFP(1.0f, MVT::f32),
758 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
760 return DAG.getNode(ISD::FADD, DL, VT,
761 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
765 /// \brief Generate Min/Max node
766 SDValue AMDGPUTargetLowering::CombineMinMax(SDNode *N,
767 SelectionDAG &DAG) const {
769 EVT VT = N->getValueType(0);
771 SDValue LHS = N->getOperand(0);
772 SDValue RHS = N->getOperand(1);
773 SDValue True = N->getOperand(2);
774 SDValue False = N->getOperand(3);
775 SDValue CC = N->getOperand(4);
777 if (VT != MVT::f32 ||
778 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
782 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
796 llvm_unreachable("Operation should already be optimised!");
803 unsigned Opc = (LHS == True) ? AMDGPUISD::FMIN : AMDGPUISD::FMAX;
804 return DAG.getNode(Opc, DL, VT, LHS, RHS);
812 unsigned Opc = (LHS == True) ? AMDGPUISD::FMAX : AMDGPUISD::FMIN;
813 return DAG.getNode(Opc, DL, VT, LHS, RHS);
815 case ISD::SETCC_INVALID:
816 llvm_unreachable("Invalid setcc condcode!");
821 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue &Op,
822 SelectionDAG &DAG) const {
823 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op);
824 EVT MemEltVT = Load->getMemoryVT().getVectorElementType();
825 EVT EltVT = Op.getValueType().getVectorElementType();
826 EVT PtrVT = Load->getBasePtr().getValueType();
827 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
828 SmallVector<SDValue, 8> Loads;
831 for (unsigned i = 0, e = NumElts; i != e; ++i) {
832 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
833 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8), PtrVT));
834 Loads.push_back(DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
835 Load->getChain(), Ptr,
836 MachinePointerInfo(Load->getMemOperand()->getValue()),
837 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
838 Load->getAlignment()));
840 return DAG.getNode(ISD::BUILD_VECTOR, SL, Op.getValueType(), Loads);
843 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
844 SelectionDAG &DAG) const {
845 StoreSDNode *Store = dyn_cast<StoreSDNode>(Op);
846 EVT MemVT = Store->getMemoryVT();
847 unsigned MemBits = MemVT.getSizeInBits();
849 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
850 // truncating store into an i32 store.
851 // XXX: We could also handle optimize other vector bitwidths.
852 if (!MemVT.isVector() || MemBits > 32) {
857 SDValue Value = Store->getValue();
858 EVT VT = Value.getValueType();
859 EVT ElemVT = VT.getVectorElementType();
860 SDValue Ptr = Store->getBasePtr();
861 EVT MemEltVT = MemVT.getVectorElementType();
862 unsigned MemEltBits = MemEltVT.getSizeInBits();
863 unsigned MemNumElements = MemVT.getVectorNumElements();
864 unsigned PackedSize = MemVT.getStoreSizeInBits();
865 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
867 assert(Value.getValueType().getScalarSizeInBits() >= 32);
870 for (unsigned i = 0; i < MemNumElements; ++i) {
871 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
872 DAG.getConstant(i, MVT::i32));
873 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
874 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
876 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
877 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
882 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
886 if (PackedSize < 32) {
887 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
888 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
889 Store->getMemOperand()->getPointerInfo(),
891 Store->isNonTemporal(), Store->isVolatile(),
892 Store->getAlignment());
895 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
896 Store->getMemOperand()->getPointerInfo(),
897 Store->isVolatile(), Store->isNonTemporal(),
898 Store->getAlignment());
901 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
902 SelectionDAG &DAG) const {
903 StoreSDNode *Store = cast<StoreSDNode>(Op);
904 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
905 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
906 EVT PtrVT = Store->getBasePtr().getValueType();
907 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
910 SmallVector<SDValue, 8> Chains;
912 for (unsigned i = 0, e = NumElts; i != e; ++i) {
913 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
914 Store->getValue(), DAG.getConstant(i, MVT::i32));
915 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT,
917 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8),
919 Chains.push_back(DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
920 MachinePointerInfo(Store->getMemOperand()->getValue()),
921 MemEltVT, Store->isVolatile(), Store->isNonTemporal(),
922 Store->getAlignment()));
924 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
927 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
929 LoadSDNode *Load = cast<LoadSDNode>(Op);
930 ISD::LoadExtType ExtType = Load->getExtensionType();
931 EVT VT = Op.getValueType();
932 EVT MemVT = Load->getMemoryVT();
934 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) {
935 // We can do the extload to 32-bits, and then need to separately extend to
938 SDValue ExtLoad32 = DAG.getExtLoad(ExtType, DL, MVT::i32,
942 Load->getMemOperand());
943 return DAG.getNode(ISD::getExtForLoadExtType(ExtType), DL, VT, ExtLoad32);
946 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
947 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
948 // FIXME: Copied from PPC
949 // First, load into 32 bits, then truncate to 1 bit.
951 SDValue Chain = Load->getChain();
952 SDValue BasePtr = Load->getBasePtr();
953 MachineMemOperand *MMO = Load->getMemOperand();
955 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
956 BasePtr, MVT::i8, MMO);
957 return DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD);
960 // Lower loads constant address space global variable loads
961 if (Load->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
963 GetUnderlyingObject(Load->getMemOperand()->getValue()))) {
965 SDValue Ptr = DAG.getZExtOrTrunc(Load->getBasePtr(), DL,
966 getPointerTy(AMDGPUAS::PRIVATE_ADDRESS));
967 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
968 DAG.getConstant(2, MVT::i32));
969 return DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
970 Load->getChain(), Ptr,
971 DAG.getTargetConstant(0, MVT::i32), Op.getOperand(2));
974 if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
975 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
979 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
980 DAG.getConstant(2, MVT::i32));
981 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
982 Load->getChain(), Ptr,
983 DAG.getTargetConstant(0, MVT::i32),
985 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
987 DAG.getConstant(0x3, MVT::i32));
988 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
989 DAG.getConstant(3, MVT::i32));
991 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
993 EVT MemEltVT = MemVT.getScalarType();
994 if (ExtType == ISD::SEXTLOAD) {
995 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
996 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode);
999 return DAG.getZeroExtendInReg(Ret, DL, MemEltVT);
1002 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1004 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1005 if (Result.getNode()) {
1009 StoreSDNode *Store = cast<StoreSDNode>(Op);
1010 SDValue Chain = Store->getChain();
1011 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1012 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1013 Store->getValue().getValueType().isVector()) {
1014 return SplitVectorStore(Op, DAG);
1017 EVT MemVT = Store->getMemoryVT();
1018 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1019 MemVT.bitsLT(MVT::i32)) {
1021 if (Store->getMemoryVT() == MVT::i8) {
1023 } else if (Store->getMemoryVT() == MVT::i16) {
1026 SDValue BasePtr = Store->getBasePtr();
1027 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1028 DAG.getConstant(2, MVT::i32));
1029 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1030 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
1032 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1033 DAG.getConstant(0x3, MVT::i32));
1035 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1036 DAG.getConstant(3, MVT::i32));
1038 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1041 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1043 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1044 MaskedValue, ShiftAmt);
1046 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
1048 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1049 DAG.getConstant(0xffffffff, MVT::i32));
1050 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1052 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1053 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1054 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
1059 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1060 SelectionDAG &DAG) const {
1062 EVT VT = Op.getValueType();
1064 SDValue Num = Op.getOperand(0);
1065 SDValue Den = Op.getOperand(1);
1067 // RCP = URECIP(Den) = 2^32 / Den + e
1068 // e is rounding error.
1069 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1071 // RCP_LO = umulo(RCP, Den) */
1072 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
1074 // RCP_HI = mulhu (RCP, Den) */
1075 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1077 // NEG_RCP_LO = -RCP_LO
1078 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1081 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1082 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1085 // Calculate the rounding error from the URECIP instruction
1086 // E = mulhu(ABS_RCP_LO, RCP)
1087 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1089 // RCP_A_E = RCP + E
1090 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1092 // RCP_S_E = RCP - E
1093 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1095 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1096 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1099 // Quotient = mulhu(Tmp0, Num)
1100 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1102 // Num_S_Remainder = Quotient * Den
1103 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
1105 // Remainder = Num - Num_S_Remainder
1106 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1108 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1109 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1110 DAG.getConstant(-1, VT),
1111 DAG.getConstant(0, VT),
1113 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1114 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1116 DAG.getConstant(-1, VT),
1117 DAG.getConstant(0, VT),
1119 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1120 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1123 // Calculate Division result:
1125 // Quotient_A_One = Quotient + 1
1126 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1127 DAG.getConstant(1, VT));
1129 // Quotient_S_One = Quotient - 1
1130 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1131 DAG.getConstant(1, VT));
1133 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1134 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1135 Quotient, Quotient_A_One, ISD::SETEQ);
1137 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1138 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1139 Quotient_S_One, Div, ISD::SETEQ);
1141 // Calculate Rem result:
1143 // Remainder_S_Den = Remainder - Den
1144 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1146 // Remainder_A_Den = Remainder + Den
1147 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1149 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1150 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1151 Remainder, Remainder_S_Den, ISD::SETEQ);
1153 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1154 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1155 Remainder_A_Den, Rem, ISD::SETEQ);
1160 return DAG.getMergeValues(Ops, DL);
1163 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
1164 SelectionDAG &DAG) const {
1165 SDValue S0 = Op.getOperand(0);
1167 if (Op.getValueType() != MVT::f32 || S0.getValueType() != MVT::i64)
1170 // f32 uint_to_fp i64
1171 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1172 DAG.getConstant(0, MVT::i32));
1173 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
1174 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1175 DAG.getConstant(1, MVT::i32));
1176 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
1177 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
1178 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
1179 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
1183 SDValue AMDGPUTargetLowering::ExpandSIGN_EXTEND_INREG(SDValue Op,
1185 SelectionDAG &DAG) const {
1186 MVT VT = Op.getSimpleValueType();
1188 SDValue Shift = DAG.getConstant(BitsDiff, VT);
1189 // Shift left by 'Shift' bits.
1190 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Op.getOperand(0), Shift);
1191 // Signed shift Right by 'Shift' bits.
1192 return DAG.getNode(ISD::SRA, DL, VT, Shl, Shift);
1195 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
1196 SelectionDAG &DAG) const {
1197 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1198 MVT VT = Op.getSimpleValueType();
1199 MVT ScalarVT = VT.getScalarType();
1204 SDValue Src = Op.getOperand(0);
1207 // TODO: Don't scalarize on Evergreen?
1208 unsigned NElts = VT.getVectorNumElements();
1209 SmallVector<SDValue, 8> Args;
1210 DAG.ExtractVectorElements(Src, Args, 0, NElts);
1212 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
1213 for (unsigned I = 0; I < NElts; ++I)
1214 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
1216 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
1219 //===----------------------------------------------------------------------===//
1220 // Custom DAG optimizations
1221 //===----------------------------------------------------------------------===//
1223 static bool isU24(SDValue Op, SelectionDAG &DAG) {
1224 APInt KnownZero, KnownOne;
1225 EVT VT = Op.getValueType();
1226 DAG.computeKnownBits(Op, KnownZero, KnownOne);
1228 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
1231 static bool isI24(SDValue Op, SelectionDAG &DAG) {
1232 EVT VT = Op.getValueType();
1234 // In order for this to be a signed 24-bit value, bit 23, must
1236 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
1237 // as unsigned 24-bit values.
1238 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
1241 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
1243 SelectionDAG &DAG = DCI.DAG;
1244 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1245 EVT VT = Op.getValueType();
1247 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
1248 APInt KnownZero, KnownOne;
1249 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
1250 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
1251 DCI.CommitTargetLoweringOpt(TLO);
1254 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
1255 DAGCombinerInfo &DCI) const {
1256 SelectionDAG &DAG = DCI.DAG;
1259 switch(N->getOpcode()) {
1262 EVT VT = N->getValueType(0);
1263 SDValue N0 = N->getOperand(0);
1264 SDValue N1 = N->getOperand(1);
1267 // FIXME: Add support for 24-bit multiply with 64-bit output on SI.
1268 if (VT.isVector() || VT.getSizeInBits() > 32)
1271 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
1272 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
1273 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
1274 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
1275 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
1276 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
1277 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
1278 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
1283 // We need to use sext even for MUL_U24, because MUL_U24 is used
1284 // for signed multiply of 8 and 16-bit types.
1285 SDValue Reg = DAG.getSExtOrTrunc(Mul, DL, VT);
1289 case AMDGPUISD::MUL_I24:
1290 case AMDGPUISD::MUL_U24: {
1291 SDValue N0 = N->getOperand(0);
1292 SDValue N1 = N->getOperand(1);
1293 simplifyI24(N0, DCI);
1294 simplifyI24(N1, DCI);
1297 case ISD::SELECT_CC: {
1298 return CombineMinMax(N, DAG);
1304 //===----------------------------------------------------------------------===//
1306 //===----------------------------------------------------------------------===//
1308 void AMDGPUTargetLowering::getOriginalFunctionArgs(
1311 const SmallVectorImpl<ISD::InputArg> &Ins,
1312 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
1314 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1315 if (Ins[i].ArgVT == Ins[i].VT) {
1316 OrigIns.push_back(Ins[i]);
1321 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
1322 // Vector has been split into scalars.
1323 VT = Ins[i].ArgVT.getVectorElementType();
1324 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
1325 Ins[i].ArgVT.getVectorElementType() !=
1326 Ins[i].VT.getVectorElementType()) {
1327 // Vector elements have been promoted
1330 // Vector has been spilt into smaller vectors.
1334 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
1335 Ins[i].OrigArgIndex, Ins[i].PartOffset);
1336 OrigIns.push_back(Arg);
1340 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
1341 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
1342 return CFP->isExactlyValue(1.0);
1344 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
1345 return C->isAllOnesValue();
1350 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
1351 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
1352 return CFP->getValueAPF().isZero();
1354 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
1355 return C->isNullValue();
1360 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
1361 const TargetRegisterClass *RC,
1362 unsigned Reg, EVT VT) const {
1363 MachineFunction &MF = DAG.getMachineFunction();
1364 MachineRegisterInfo &MRI = MF.getRegInfo();
1365 unsigned VirtualRegister;
1366 if (!MRI.isLiveIn(Reg)) {
1367 VirtualRegister = MRI.createVirtualRegister(RC);
1368 MRI.addLiveIn(Reg, VirtualRegister);
1370 VirtualRegister = MRI.getLiveInVirtReg(Reg);
1372 return DAG.getRegister(VirtualRegister, VT);
1375 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
1377 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
1379 default: return nullptr;
1381 NODE_NAME_CASE(CALL);
1382 NODE_NAME_CASE(UMUL);
1383 NODE_NAME_CASE(DIV_INF);
1384 NODE_NAME_CASE(RET_FLAG);
1385 NODE_NAME_CASE(BRANCH_COND);
1388 NODE_NAME_CASE(DWORDADDR)
1389 NODE_NAME_CASE(FRACT)
1390 NODE_NAME_CASE(FMAX)
1391 NODE_NAME_CASE(SMAX)
1392 NODE_NAME_CASE(UMAX)
1393 NODE_NAME_CASE(FMIN)
1394 NODE_NAME_CASE(SMIN)
1395 NODE_NAME_CASE(UMIN)
1396 NODE_NAME_CASE(BFE_U32)
1397 NODE_NAME_CASE(BFE_I32)
1400 NODE_NAME_CASE(MUL_U24)
1401 NODE_NAME_CASE(MUL_I24)
1402 NODE_NAME_CASE(URECIP)
1403 NODE_NAME_CASE(DOT4)
1404 NODE_NAME_CASE(EXPORT)
1405 NODE_NAME_CASE(CONST_ADDRESS)
1406 NODE_NAME_CASE(REGISTER_LOAD)
1407 NODE_NAME_CASE(REGISTER_STORE)
1408 NODE_NAME_CASE(LOAD_CONSTANT)
1409 NODE_NAME_CASE(LOAD_INPUT)
1410 NODE_NAME_CASE(SAMPLE)
1411 NODE_NAME_CASE(SAMPLEB)
1412 NODE_NAME_CASE(SAMPLED)
1413 NODE_NAME_CASE(SAMPLEL)
1414 NODE_NAME_CASE(STORE_MSKOR)
1415 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
1419 static void computeKnownBitsForMinMax(const SDValue Op0,
1423 const SelectionDAG &DAG,
1425 APInt Op0Zero, Op0One;
1426 APInt Op1Zero, Op1One;
1427 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
1428 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
1430 KnownZero = Op0Zero & Op1Zero;
1431 KnownOne = Op0One & Op1One;
1434 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
1438 const SelectionDAG &DAG,
1439 unsigned Depth) const {
1441 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
1442 unsigned Opc = Op.getOpcode();
1444 case ISD::INTRINSIC_WO_CHAIN: {
1445 // FIXME: The intrinsic should just use the node.
1446 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
1447 case AMDGPUIntrinsic::AMDGPU_imax:
1448 case AMDGPUIntrinsic::AMDGPU_umax:
1449 case AMDGPUIntrinsic::AMDGPU_imin:
1450 case AMDGPUIntrinsic::AMDGPU_umin:
1451 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
1452 KnownZero, KnownOne, DAG, Depth);
1460 case AMDGPUISD::SMAX:
1461 case AMDGPUISD::UMAX:
1462 case AMDGPUISD::SMIN:
1463 case AMDGPUISD::UMIN:
1464 computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
1465 KnownZero, KnownOne, DAG, Depth);