1 //===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
14 #include "AMDGPUInstrInfo.h"
15 #include "AMDGPUISelLowering.h" // For AMDGPUISD
16 #include "AMDGPURegisterInfo.h"
17 #include "R600InstrInfo.h"
18 #include "SIISelLowering.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/SelectionDAGISel.h"
25 //===----------------------------------------------------------------------===//
26 // Instruction Selector Implementation
27 //===----------------------------------------------------------------------===//
30 /// AMDGPU specific code to select AMDGPU machine instructions for
31 /// SelectionDAG operations.
32 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
33 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
34 // make the right decision when generating code for different targets.
35 const AMDGPUSubtarget &Subtarget;
37 AMDGPUDAGToDAGISel(TargetMachine &TM);
38 virtual ~AMDGPUDAGToDAGISel();
40 SDNode *Select(SDNode *N);
41 virtual const char *getPassName() const;
42 virtual void PostprocessISelDAG();
45 bool isInlineImmediate(SDNode *N) const;
46 inline SDValue getSmallIPtrImm(unsigned Imm);
47 bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
48 const R600InstrInfo *TII);
49 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
50 bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
52 // Complex pattern selectors
53 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
54 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
55 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
57 static bool checkType(const Value *ptr, unsigned int addrspace);
58 static bool checkPrivateAddress(const MachineMemOperand *Op);
60 static bool isGlobalStore(const StoreSDNode *N);
61 static bool isPrivateStore(const StoreSDNode *N);
62 static bool isLocalStore(const StoreSDNode *N);
63 static bool isRegionStore(const StoreSDNode *N);
65 bool isCPLoad(const LoadSDNode *N) const;
66 bool isConstantLoad(const LoadSDNode *N, int cbID) const;
67 bool isGlobalLoad(const LoadSDNode *N) const;
68 bool isParamLoad(const LoadSDNode *N) const;
69 bool isPrivateLoad(const LoadSDNode *N) const;
70 bool isLocalLoad(const LoadSDNode *N) const;
71 bool isRegionLoad(const LoadSDNode *N) const;
73 const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
74 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
75 bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
77 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
78 bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
80 // Include the pieces autogenerated from the target description.
81 #include "AMDGPUGenDAGISel.inc"
83 } // end anonymous namespace
85 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
86 // DAG, ready for instruction scheduling.
87 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM) {
88 return new AMDGPUDAGToDAGISel(TM);
91 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM)
92 : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>()) {
95 AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
98 bool AMDGPUDAGToDAGISel::isInlineImmediate(SDNode *N) const {
99 const SITargetLowering *TL
100 = static_cast<const SITargetLowering *>(getTargetLowering());
101 return TL->analyzeImmediate(N) == 0;
104 /// \brief Determine the register class for \p OpNo
105 /// \returns The register class of the virtual register that will be used for
106 /// the given operand number \OpNo or NULL if the register class cannot be
108 const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
109 unsigned OpNo) const {
110 if (!N->isMachineOpcode())
113 switch (N->getMachineOpcode()) {
115 const MCInstrDesc &Desc = TM.getInstrInfo()->get(N->getMachineOpcode());
116 unsigned OpIdx = Desc.getNumDefs() + OpNo;
117 if (OpIdx >= Desc.getNumOperands())
119 int RegClass = Desc.OpInfo[OpIdx].RegClass;
123 return TM.getRegisterInfo()->getRegClass(RegClass);
125 case AMDGPU::REG_SEQUENCE: {
126 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
127 const TargetRegisterClass *SuperRC = TM.getRegisterInfo()->getRegClass(RCID);
129 SDValue SubRegOp = N->getOperand(OpNo + 1);
130 unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue();
131 return TM.getRegisterInfo()->getSubClassWithSubReg(SuperRC, SubRegIdx);
136 SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
137 return CurDAG->getTargetConstant(Imm, MVT::i32);
140 bool AMDGPUDAGToDAGISel::SelectADDRParam(
141 SDValue Addr, SDValue& R1, SDValue& R2) {
143 if (Addr.getOpcode() == ISD::FrameIndex) {
144 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
145 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
146 R2 = CurDAG->getTargetConstant(0, MVT::i32);
149 R2 = CurDAG->getTargetConstant(0, MVT::i32);
151 } else if (Addr.getOpcode() == ISD::ADD) {
152 R1 = Addr.getOperand(0);
153 R2 = Addr.getOperand(1);
156 R2 = CurDAG->getTargetConstant(0, MVT::i32);
161 bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
162 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
163 Addr.getOpcode() == ISD::TargetGlobalAddress) {
166 return SelectADDRParam(Addr, R1, R2);
170 bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
171 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
172 Addr.getOpcode() == ISD::TargetGlobalAddress) {
176 if (Addr.getOpcode() == ISD::FrameIndex) {
177 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
178 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
179 R2 = CurDAG->getTargetConstant(0, MVT::i64);
182 R2 = CurDAG->getTargetConstant(0, MVT::i64);
184 } else if (Addr.getOpcode() == ISD::ADD) {
185 R1 = Addr.getOperand(0);
186 R2 = Addr.getOperand(1);
189 R2 = CurDAG->getTargetConstant(0, MVT::i64);
194 SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
195 unsigned int Opc = N->getOpcode();
196 if (N->isMachineOpcode()) {
198 return nullptr; // Already selected.
201 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
204 // We are selecting i64 ADD here instead of custom lower it during
205 // DAG legalization, so we can fold some i64 ADDs used for address
206 // calculation into the LOAD and STORE instructions.
208 if (N->getValueType(0) != MVT::i64 ||
209 ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
213 SDValue LHS = N->getOperand(0);
214 SDValue RHS = N->getOperand(1);
216 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
217 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
219 SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
220 DL, MVT::i32, LHS, Sub0);
221 SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
222 DL, MVT::i32, LHS, Sub1);
224 SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
225 DL, MVT::i32, RHS, Sub0);
226 SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
227 DL, MVT::i32, RHS, Sub1);
229 SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue);
231 SmallVector<SDValue, 8> AddLoArgs;
232 AddLoArgs.push_back(SDValue(Lo0, 0));
233 AddLoArgs.push_back(SDValue(Lo1, 0));
235 SDNode *AddLo = CurDAG->getMachineNode(AMDGPU::S_ADD_I32, DL,
237 SDValue Carry = SDValue(AddLo, 1);
238 SDNode *AddHi = CurDAG->getMachineNode(AMDGPU::S_ADDC_U32, DL,
239 MVT::i32, SDValue(Hi0, 0),
240 SDValue(Hi1, 0), Carry);
243 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),
249 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, MVT::i64, Args);
251 case ISD::BUILD_VECTOR: {
253 const AMDGPURegisterInfo *TRI =
254 static_cast<const AMDGPURegisterInfo*>(TM.getRegisterInfo());
255 const SIRegisterInfo *SIRI =
256 static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
257 EVT VT = N->getValueType(0);
258 unsigned NumVectorElts = VT.getVectorNumElements();
259 assert(VT.getVectorElementType().bitsEq(MVT::i32));
260 if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
262 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
264 if (!U->isMachineOpcode()) {
267 const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
271 if (SIRI->isSGPRClass(RC)) {
275 switch(NumVectorElts) {
276 case 1: RegClassID = UseVReg ? AMDGPU::VReg_32RegClassID :
277 AMDGPU::SReg_32RegClassID;
279 case 2: RegClassID = UseVReg ? AMDGPU::VReg_64RegClassID :
280 AMDGPU::SReg_64RegClassID;
282 case 4: RegClassID = UseVReg ? AMDGPU::VReg_128RegClassID :
283 AMDGPU::SReg_128RegClassID;
285 case 8: RegClassID = UseVReg ? AMDGPU::VReg_256RegClassID :
286 AMDGPU::SReg_256RegClassID;
288 case 16: RegClassID = UseVReg ? AMDGPU::VReg_512RegClassID :
289 AMDGPU::SReg_512RegClassID;
291 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
294 // BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
295 // that adds a 128 bits reg copy when going through TwoAddressInstructions
296 // pass. We want to avoid 128 bits copies as much as possible because they
297 // can't be bundled by our scheduler.
298 switch(NumVectorElts) {
299 case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break;
300 case 4: RegClassID = AMDGPU::R600_Reg128RegClassID; break;
301 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
305 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, MVT::i32);
307 if (NumVectorElts == 1) {
308 return CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS,
309 VT.getVectorElementType(),
310 N->getOperand(0), RegClass);
313 assert(NumVectorElts <= 16 && "Vectors with more than 16 elements not "
315 // 16 = Max Num Vector Elements
316 // 2 = 2 REG_SEQUENCE operands per element (value, subreg index)
317 // 1 = Vector Register Class
318 SmallVector<SDValue, 16 * 2 + 1> RegSeqArgs(N->getNumOperands() * 2 + 1);
320 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, MVT::i32);
321 bool IsRegSeq = true;
322 for (unsigned i = 0; i < N->getNumOperands(); i++) {
323 // XXX: Why is this here?
324 if (dyn_cast<RegisterSDNode>(N->getOperand(i))) {
328 RegSeqArgs[1 + (2 * i)] = N->getOperand(i);
329 RegSeqArgs[1 + (2 * i) + 1] =
330 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32);
334 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
337 case ISD::BUILD_PAIR: {
338 SDValue RC, SubReg0, SubReg1;
339 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
342 if (N->getValueType(0) == MVT::i128) {
343 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32);
344 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32);
345 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32);
346 } else if (N->getValueType(0) == MVT::i64) {
347 RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32);
348 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
349 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
351 llvm_unreachable("Unhandled value type for BUILD_PAIR");
353 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
354 N->getOperand(1), SubReg1 };
355 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
356 SDLoc(N), N->getValueType(0), Ops);
360 case ISD::ConstantFP: {
361 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
362 if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
363 N->getValueType(0).getSizeInBits() != 64 || isInlineImmediate(N))
367 if (ConstantFPSDNode *FP = dyn_cast<ConstantFPSDNode>(N))
368 Imm = FP->getValueAPF().bitcastToAPInt().getZExtValue();
370 ConstantSDNode *C = cast<ConstantSDNode>(N);
371 Imm = C->getZExtValue();
374 SDNode *Lo = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SDLoc(N), MVT::i32,
375 CurDAG->getConstant(Imm & 0xFFFFFFFF, MVT::i32));
376 SDNode *Hi = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SDLoc(N), MVT::i32,
377 CurDAG->getConstant(Imm >> 32, MVT::i32));
378 const SDValue Ops[] = {
379 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),
380 SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
381 SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32)
384 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, SDLoc(N),
385 N->getValueType(0), Ops);
388 case AMDGPUISD::REGISTER_LOAD: {
389 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
391 SDValue Addr, Offset;
393 SelectADDRIndirect(N->getOperand(1), Addr, Offset);
394 const SDValue Ops[] = {
397 CurDAG->getTargetConstant(0, MVT::i32),
400 return CurDAG->getMachineNode(AMDGPU::SI_RegisterLoad, SDLoc(N),
401 CurDAG->getVTList(MVT::i32, MVT::i64, MVT::Other),
404 case AMDGPUISD::REGISTER_STORE: {
405 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
407 SDValue Addr, Offset;
408 SelectADDRIndirect(N->getOperand(2), Addr, Offset);
409 const SDValue Ops[] = {
413 CurDAG->getTargetConstant(0, MVT::i32),
416 return CurDAG->getMachineNode(AMDGPU::SI_RegisterStorePseudo, SDLoc(N),
417 CurDAG->getVTList(MVT::Other),
421 case AMDGPUISD::BFE_I32:
422 case AMDGPUISD::BFE_U32: {
423 if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
426 // There is a scalar version available, but unlike the vector version which
427 // has a separate operand for the offset and width, the scalar version packs
428 // the width and offset into a single operand. Try to move to the scalar
429 // version if the offsets are constant, so that we can try to keep extended
430 // loads of kernel arguments in SGPRs.
432 // TODO: Technically we could try to pattern match scalar bitshifts of
433 // dynamic values, but it's probably not useful.
434 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
438 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
442 bool Signed = Opc == AMDGPUISD::BFE_I32;
444 // Transformation function, pack the offset and width of a BFE into
445 // the format expected by the S_BFE_I32 / S_BFE_U32. In the second
446 // source, bits [5:0] contain the offset and bits [22:16] the width.
448 uint32_t OffsetVal = Offset->getZExtValue();
449 uint32_t WidthVal = Width->getZExtValue();
451 uint32_t PackedVal = OffsetVal | WidthVal << 16;
453 SDValue PackedOffsetWidth = CurDAG->getTargetConstant(PackedVal, MVT::i32);
454 return CurDAG->getMachineNode(Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32,
462 return SelectCode(N);
466 bool AMDGPUDAGToDAGISel::checkType(const Value *Ptr, unsigned AS) {
467 assert(AS != 0 && "Use checkPrivateAddress instead.");
471 return Ptr->getType()->getPointerAddressSpace() == AS;
474 bool AMDGPUDAGToDAGISel::checkPrivateAddress(const MachineMemOperand *Op) {
475 if (Op->getPseudoValue())
478 if (PointerType *PT = dyn_cast<PointerType>(Op->getValue()->getType()))
479 return PT->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
484 bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
485 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
488 bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
489 const Value *MemVal = N->getMemOperand()->getValue();
490 return (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
491 !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
492 !checkType(MemVal, AMDGPUAS::REGION_ADDRESS));
495 bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
496 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
499 bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
500 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
503 bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int CbId) const {
504 const Value *MemVal = N->getMemOperand()->getValue();
506 return checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS);
508 return checkType(MemVal, AMDGPUAS::CONSTANT_BUFFER_0 + CbId);
511 bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) const {
512 if (N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS) {
513 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
514 if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
515 N->getMemoryVT().bitsLT(MVT::i32)) {
519 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
522 bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) const {
523 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::PARAM_I_ADDRESS);
526 bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) const {
527 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
530 bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) const {
531 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
534 bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) const {
535 MachineMemOperand *MMO = N->getMemOperand();
536 if (checkPrivateAddress(N->getMemOperand())) {
538 const PseudoSourceValue *PSV = MMO->getPseudoValue();
539 if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
547 bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) const {
548 if (checkPrivateAddress(N->getMemOperand())) {
549 // Check to make sure we are not a constant pool load or a constant load
550 // that is marked as a private load
551 if (isCPLoad(N) || isConstantLoad(N, -1)) {
556 const Value *MemVal = N->getMemOperand()->getValue();
557 if (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
558 !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
559 !checkType(MemVal, AMDGPUAS::REGION_ADDRESS) &&
560 !checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS) &&
561 !checkType(MemVal, AMDGPUAS::PARAM_D_ADDRESS) &&
562 !checkType(MemVal, AMDGPUAS::PARAM_I_ADDRESS)){
568 const char *AMDGPUDAGToDAGISel::getPassName() const {
569 return "AMDGPU DAG->DAG Pattern Instruction Selection";
577 //===----------------------------------------------------------------------===//
579 //===----------------------------------------------------------------------===//
581 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
583 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
584 IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, true);
590 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
591 SDValue& BaseReg, SDValue &Offset) {
592 if (!isa<ConstantSDNode>(Addr)) {
594 Offset = CurDAG->getIntPtrConstant(0, true);
600 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
602 ConstantSDNode *IMMOffset;
604 if (Addr.getOpcode() == ISD::ADD
605 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
606 && isInt<16>(IMMOffset->getZExtValue())) {
608 Base = Addr.getOperand(0);
609 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
611 // If the pointer address is constant, we can move it to the offset field.
612 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
613 && isInt<16>(IMMOffset->getZExtValue())) {
614 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
615 SDLoc(CurDAG->getEntryNode()),
616 AMDGPU::ZERO, MVT::i32);
617 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
621 // Default case, no offset
623 Offset = CurDAG->getTargetConstant(0, MVT::i32);
627 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
631 if ((C = dyn_cast<ConstantSDNode>(Addr))) {
632 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
633 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
634 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
635 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
636 Base = Addr.getOperand(0);
637 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
640 Offset = CurDAG->getTargetConstant(0, MVT::i32);
646 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
647 const AMDGPUTargetLowering& Lowering =
648 *static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
649 bool IsModified = false;
652 // Go over all selected nodes and try to fold them a bit more
653 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
654 E = CurDAG->allnodes_end(); I != E; ++I) {
658 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
662 SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
663 if (ResNode != Node) {
664 ReplaceUses(Node, ResNode);
668 CurDAG->RemoveDeadNodes();
669 } while (IsModified);