lib/Target/R600/AMDGPUAsmPrinter.cpp

   1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 ///
  12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
  13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
  14 /// an MCObjectStreamer it outputs binary code.
  15 //
  16 //===----------------------------------------------------------------------===//
  17 //
  18
  19
  20 #include "AMDGPUAsmPrinter.h"
  21 #include "AMDGPU.h"
  22 #include "R600Defines.h"
  23 #include "R600MachineFunctionInfo.h"
  24 #include "R600RegisterInfo.h"
  25 #include "SIDefines.h"
  26 #include "SIMachineFunctionInfo.h"
  27 #include "SIRegisterInfo.h"
  28 #include "llvm/MC/MCContext.h"
  29 #include "llvm/MC/MCSectionELF.h"
  30 #include "llvm/MC/MCStreamer.h"
  31 #include "llvm/Support/ELF.h"
  32 #include "llvm/Support/MathExtras.h"
  33 #include "llvm/Support/TargetRegistry.h"
  34 #include "llvm/Target/TargetLoweringObjectFile.h"
  35
  36 using namespace llvm;
  37
  38
  39 static AsmPrinter *createAMDGPUAsmPrinterPass(TargetMachine &tm,
  40                                               MCStreamer &Streamer) {
  41   return new AMDGPUAsmPrinter(tm, Streamer);
  42 }
  43
  44 extern "C" void LLVMInitializeR600AsmPrinter() {
  45   TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
  46 }
  47
  48 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
  49     : AsmPrinter(TM, Streamer) {
  50   DisasmEnabled = TM.getSubtarget<AMDGPUSubtarget>().dumpCode() &&
  51                   ! Streamer.hasRawTextSupport();
  52 }
  53
  54 /// We need to override this function so we can avoid
  55 /// the call to EmitFunctionHeader(), which the MCPureStreamer can't handle.
  56 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
  57   SetupMachineFunction(MF);
  58
  59   if (OutStreamer.hasRawTextSupport()) {
  60     OutStreamer.EmitRawText("@" + MF.getName() + ":");
  61   }
  62
  63   MCContext &Context = getObjFileLowering().getContext();
  64   const MCSectionELF *ConfigSection = Context.getELFSection(".AMDGPU.config",
  65                                               ELF::SHT_PROGBITS, 0,
  66                                               SectionKind::getReadOnly());
  67   OutStreamer.SwitchSection(ConfigSection);
  68
  69   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
  70   SIProgramInfo KernelInfo;
  71   if (STM.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
  72     findNumUsedRegistersSI(MF, KernelInfo.NumSGPR, KernelInfo.NumVGPR);
  73     EmitProgramInfoSI(MF, KernelInfo);
  74   } else {
  75     EmitProgramInfoR600(MF);
  76   }
  77
  78   DisasmLines.clear();
  79   HexLines.clear();
  80   DisasmLineMaxLen = 0;
  81
  82   OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
  83   EmitFunctionBody();
  84
  85   if (isVerbose() && OutStreamer.hasRawTextSupport()) {
  86     const MCSectionELF *CommentSection
  87       = Context.getELFSection(".AMDGPU.csdata",
  88                               ELF::SHT_PROGBITS, 0,
  89                               SectionKind::getReadOnly());
  90     OutStreamer.SwitchSection(CommentSection);
  91
  92     if (STM.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
  93       OutStreamer.EmitRawText(
  94         Twine("; Kernel info:\n") +
  95         "; NumSgprs: " + Twine(KernelInfo.NumSGPR) + "\n" +
  96         "; NumVgprs: " + Twine(KernelInfo.NumVGPR) + "\n");
  97     } else {
  98       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
  99       OutStreamer.EmitRawText(
 100         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
 101     }
 102   }
 103
 104   if (STM.dumpCode()) {
 105 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 106     MF.dump();
 107 #endif
 108
 109     if (DisasmEnabled) {
 110       OutStreamer.SwitchSection(Context.getELFSection(".AMDGPU.disasm",
 111                                                   ELF::SHT_NOTE, 0,
 112                                                   SectionKind::getReadOnly()));
 113
 114       for (size_t i = 0; i < DisasmLines.size(); ++i) {
 115         std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
 116         Comment += " ; " + HexLines[i] + "\n";
 117
 118         OutStreamer.EmitBytes(StringRef(DisasmLines[i]));
 119         OutStreamer.EmitBytes(StringRef(Comment));
 120       }
 121     }
 122   }
 123
 124   return false;
 125 }
 126
 127 void AMDGPUAsmPrinter::EmitProgramInfoR600(MachineFunction &MF) {
 128   unsigned MaxGPR = 0;
 129   bool killPixel = false;
 130   const R600RegisterInfo * RI =
 131                 static_cast<const R600RegisterInfo*>(TM.getRegisterInfo());
 132   R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
 133   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 134
 135   for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
 136                                                   BB != BB_E; ++BB) {
 137     MachineBasicBlock &MBB = *BB;
 138     for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
 139                                                     I != E; ++I) {
 140       MachineInstr &MI = *I;
 141       if (MI.getOpcode() == AMDGPU::KILLGT)
 142         killPixel = true;
 143       unsigned numOperands = MI.getNumOperands();
 144       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 145         MachineOperand & MO = MI.getOperand(op_idx);
 146         if (!MO.isReg())
 147           continue;
 148         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
 149
 150         // Register with value > 127 aren't GPR
 151         if (HWReg > 127)
 152           continue;
 153         MaxGPR = std::max(MaxGPR, HWReg);
 154       }
 155     }
 156   }
 157
 158   unsigned RsrcReg;
 159   if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
 160     // Evergreen / Northern Islands
 161     switch (MFI->ShaderType) {
 162     default: // Fall through
 163     case ShaderType::COMPUTE:  RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
 164     case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
 165     case ShaderType::PIXEL:    RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
 166     case ShaderType::VERTEX:   RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
 167     }
 168   } else {
 169     // R600 / R700
 170     switch (MFI->ShaderType) {
 171     default: // Fall through
 172     case ShaderType::GEOMETRY: // Fall through
 173     case ShaderType::COMPUTE:  // Fall through
 174     case ShaderType::VERTEX:   RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
 175     case ShaderType::PIXEL:    RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
 176     }
 177   }
 178
 179   OutStreamer.EmitIntValue(RsrcReg, 4);
 180   OutStreamer.EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
 181                            S_STACK_SIZE(MFI->StackSize), 4);
 182   OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
 183   OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
 184
 185   if (MFI->ShaderType == ShaderType::COMPUTE) {
 186     OutStreamer.EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
 187     OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
 188   }
 189 }
 190
 191 void AMDGPUAsmPrinter::findNumUsedRegistersSI(MachineFunction &MF,
 192                                               unsigned &NumSGPR,
 193                                               unsigned &NumVGPR) const {
 194   unsigned MaxSGPR = 0;
 195   unsigned MaxVGPR = 0;
 196   bool VCCUsed = false;
 197   const SIRegisterInfo * RI =
 198                 static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
 199
 200   for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
 201                                                   BB != BB_E; ++BB) {
 202     MachineBasicBlock &MBB = *BB;
 203     for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
 204                                                     I != E; ++I) {
 205       MachineInstr &MI = *I;
 206
 207       unsigned numOperands = MI.getNumOperands();
 208       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 209         MachineOperand &MO = MI.getOperand(op_idx);
 210         unsigned width = 0;
 211         bool isSGPR = false;
 212
 213         if (!MO.isReg()) {
 214           continue;
 215         }
 216         unsigned reg = MO.getReg();
 217         if (reg == AMDGPU::VCC) {
 218           VCCUsed = true;
 219           continue;
 220         }
 221
 222         switch (reg) {
 223         default: break;
 224         case AMDGPU::SCC:
 225         case AMDGPU::EXEC:
 226         case AMDGPU::M0:
 227           continue;
 228         }
 229
 230         if (AMDGPU::SReg_32RegClass.contains(reg)) {
 231           isSGPR = true;
 232           width = 1;
 233         } else if (AMDGPU::VReg_32RegClass.contains(reg)) {
 234           isSGPR = false;
 235           width = 1;
 236         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
 237           isSGPR = true;
 238           width = 2;
 239         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
 240           isSGPR = false;
 241           width = 2;
 242         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
 243           isSGPR = false;
 244           width = 3;
 245         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
 246           isSGPR = true;
 247           width = 4;
 248         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
 249           isSGPR = false;
 250           width = 4;
 251         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
 252           isSGPR = true;
 253           width = 8;
 254         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
 255           isSGPR = false;
 256           width = 8;
 257         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
 258           isSGPR = true;
 259           width = 16;
 260         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
 261           isSGPR = false;
 262           width = 16;
 263         } else {
 264           llvm_unreachable("Unknown register class");
 265         }
 266         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
 267         unsigned maxUsed = hwReg + width - 1;
 268         if (isSGPR) {
 269           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
 270         } else {
 271           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
 272         }
 273       }
 274     }
 275   }
 276
 277   if (VCCUsed)
 278     MaxSGPR += 2;
 279
 280   NumSGPR = MaxSGPR;
 281   NumVGPR = MaxVGPR;
 282 }
 283
 284 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &Out,
 285                                         MachineFunction &MF) const {
 286   findNumUsedRegistersSI(MF, Out.NumSGPR, Out.NumVGPR);
 287 }
 288
 289 void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF,
 290                                          const SIProgramInfo &KernelInfo) {
 291   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 292
 293   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 294   unsigned RsrcReg;
 295   switch (MFI->ShaderType) {
 296   default: // Fall through
 297   case ShaderType::COMPUTE:  RsrcReg = R_00B848_COMPUTE_PGM_RSRC1; break;
 298   case ShaderType::GEOMETRY: RsrcReg = R_00B228_SPI_SHADER_PGM_RSRC1_GS; break;
 299   case ShaderType::PIXEL:    RsrcReg = R_00B028_SPI_SHADER_PGM_RSRC1_PS; break;
 300   case ShaderType::VERTEX:   RsrcReg = R_00B128_SPI_SHADER_PGM_RSRC1_VS; break;
 301   }
 302
 303   OutStreamer.EmitIntValue(RsrcReg, 4);
 304   OutStreamer.EmitIntValue(S_00B028_VGPRS(KernelInfo.NumVGPR / 4) |
 305                            S_00B028_SGPRS(KernelInfo.NumSGPR / 8), 4);
 306
 307   unsigned LDSAlignShift;
 308   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
 309     // LDS is allocated in 64 dword blocks
 310     LDSAlignShift = 8;
 311   } else {
 312     // LDS is allocated in 128 dword blocks
 313     LDSAlignShift = 9;
 314   }
 315   unsigned LDSBlocks =
 316           RoundUpToAlignment(MFI->LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
 317
 318   if (MFI->ShaderType == ShaderType::COMPUTE) {
 319     OutStreamer.EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
 320     OutStreamer.EmitIntValue(S_00B84C_LDS_SIZE(LDSBlocks), 4);
 321   }
 322   if (MFI->ShaderType == ShaderType::PIXEL) {
 323     OutStreamer.EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
 324     OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(LDSBlocks), 4);
 325     OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
 326     OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);
 327   }
 328 }