1 //===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
10 // Include AMDIL TD files
11 include "AMDILBase.td"
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
17 def FeatureFP64 : SubtargetFeature<"fp64",
18 "CapsOverride[AMDGPUDeviceInfo::DoubleOps]",
20 "Enable 64bit double precision operations">;
21 def FeatureByteAddress : SubtargetFeature<"byte_addressable_store",
22 "CapsOverride[AMDGPUDeviceInfo::ByteStores]",
24 "Enable byte addressable stores">;
25 def FeatureBarrierDetect : SubtargetFeature<"barrier_detect",
26 "CapsOverride[AMDGPUDeviceInfo::BarrierDetect]",
28 "Enable duplicate barrier detection(HD5XXX or later).">;
29 def FeatureImages : SubtargetFeature<"images",
30 "CapsOverride[AMDGPUDeviceInfo::Images]",
32 "Enable image functions">;
33 def FeatureMultiUAV : SubtargetFeature<"multi_uav",
34 "CapsOverride[AMDGPUDeviceInfo::MultiUAV]",
36 "Generate multiple UAV code(HD5XXX family or later)">;
37 def FeatureMacroDB : SubtargetFeature<"macrodb",
38 "CapsOverride[AMDGPUDeviceInfo::MacroDB]",
40 "Use internal macrodb, instead of macrodb in driver">;
41 def FeatureNoAlias : SubtargetFeature<"noalias",
42 "CapsOverride[AMDGPUDeviceInfo::NoAlias]",
44 "assert that all kernel argument pointers are not aliased">;
45 def FeatureNoInline : SubtargetFeature<"no-inline",
46 "CapsOverride[AMDGPUDeviceInfo::NoInline]",
48 "specify whether to not inline functions">;
50 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
53 "Specify if 64bit addressing should be used.">;
55 def Feature32on64BitPtr : SubtargetFeature<"64on32BitPtr",
58 "Specify if 64bit sized pointers with 32bit addressing should be used.">;
59 def FeatureDebug : SubtargetFeature<"debug",
60 "CapsOverride[AMDGPUDeviceInfo::Debug]",
62 "Debug mode is enabled, so disable hardware accelerated address spaces.">;
63 def FeatureDumpCode : SubtargetFeature <"DumpCode",
66 "Dump MachineInstrs in the CodeEmitter">;
68 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
71 "Older version of ALU instructions encoding.">;
73 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
76 "Specify use of dedicated vertex cache.">;
78 class SubtargetFeatureFetchLimit <string Value> :
79 SubtargetFeature <"fetch"#Value,
82 "Limit the maximum number of fetches in a clause to "#Value>;
84 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
85 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
87 //===----------------------------------------------------------------------===//
89 def AMDGPUInstrInfo : InstrInfo {
90 let guessInstructionProperties = 1;
93 //===----------------------------------------------------------------------===//
94 // Declare the target which we are implementing
95 //===----------------------------------------------------------------------===//
96 def AMDGPUAsmWriter : AsmWriter {
97 string AsmWriterClassName = "InstPrinter";
99 bit isMCAsmWriter = 1;
102 def AMDGPU : Target {
103 // Pull in Instruction Info:
104 let InstructionSet = AMDGPUInstrInfo;
105 let AssemblyWriters = [AMDGPUAsmWriter];
108 // Include AMDGPU TD files
109 include "R600Schedule.td"
110 include "SISchedule.td"
111 include "Processors.td"
112 include "AMDGPUInstrInfo.td"
113 include "AMDGPUIntrinsics.td"
114 include "AMDGPURegisterInfo.td"
115 include "AMDGPUInstructions.td"
116 include "AMDGPUCallingConv.td"