3 * implement do-loop -> bdnz transform
4 * implement powerpc-64 for darwin
5 * use stfiwx in float->int
6 * be able to combine sequences like the following into 2 instructions:
7 lis r2, ha16(l2__ZTV4Cell)
8 la r2, lo16(l2__ZTV4Cell)(r2)
11 * Teach LLVM how to codegen this:
12 unsigned short foo(float a) { return a; }
24 rlwinm r3, r2, 0, 16, 31
28 extern int X, Y; int* test(int C) { return C? &X : &Y; }
29 as one load when using --enable-pic.
31 * Support 'update' load/store instructions. These are cracked on the G5, but
32 are still a codesize win.
34 * should hint to the branch select pass that it doesn't need to print the
35 second unconditional branch, so we don't end up with things like:
36 b .LBBl42__2E_expand_function_8_674 ; loopentry.24
37 b .LBBl42__2E_expand_function_8_42 ; NewDefault
38 b .LBBl42__2E_expand_function_8_42 ; NewDefault
40 ===-------------------------------------------------------------------------===
45 if (X == 0x12345678) bar();
61 ===-------------------------------------------------------------------------===
63 Lump the constant pool for each function into ONE pic object, and reference
64 pieces of it as offsets from the start. For functions like this (contrived
65 to have lots of constants obviously):
67 double X(double Y) { return (Y*1.23 + 4.512)*2.34 + 14.38; }
72 lis r2, ha16(.CPI_X_0)
73 lfd f0, lo16(.CPI_X_0)(r2)
74 lis r2, ha16(.CPI_X_1)
75 lfd f2, lo16(.CPI_X_1)(r2)
77 lis r2, ha16(.CPI_X_2)
78 lfd f1, lo16(.CPI_X_2)(r2)
79 lis r2, ha16(.CPI_X_3)
80 lfd f2, lo16(.CPI_X_3)(r2)
84 It would be better to materialize .CPI_X into a register, then use immediates
85 off of the register to avoid the lis's. This is even more important in PIC
88 ===-------------------------------------------------------------------------===
90 Implement Newton-Rhapson method for improving estimate instructions to the
91 correct accuracy, and implementing divide as multiply by reciprocal when it has
92 more than one use. Itanium will want this too.
94 ===-------------------------------------------------------------------------===
96 int foo(int a, int b) { return a == b ? 16 : 0; }
100 rlwinm r2, r2, 31, 31, 31
104 If we exposed the srl & mask ops after the MFCR that we are doing to select
105 the correct CR bit, then we could fold the slwi into the rlwinm before it.
107 ===-------------------------------------------------------------------------===
109 #define ARRAY_LENGTH 16
114 unsigned int field0 : 6;
115 unsigned int field1 : 6;
116 unsigned int field2 : 6;
117 unsigned int field3 : 6;
118 unsigned int field4 : 3;
119 unsigned int field5 : 4;
120 unsigned int field6 : 1;
122 unsigned int field6 : 1;
123 unsigned int field5 : 4;
124 unsigned int field4 : 3;
125 unsigned int field3 : 6;
126 unsigned int field2 : 6;
127 unsigned int field1 : 6;
128 unsigned int field0 : 6;
137 typedef struct program_t {
138 union bitfield array[ARRAY_LENGTH];
144 void AdjustBitfields(program* prog, unsigned int fmt1)
146 unsigned int shift = 0;
147 unsigned int texCount = 0;
150 for (i = 0; i < 8; i++)
152 prog->array[i].bitfields.field0 = texCount;
153 prog->array[i].bitfields.field1 = texCount + 1;
154 prog->array[i].bitfields.field2 = texCount + 2;
155 prog->array[i].bitfields.field3 = texCount + 3;
157 texCount += (fmt1 >> shift) & 0x7;
162 In the loop above, the bitfield adds get generated as
163 (add (shl bitfield, C1), (shl C2, C1)) where C2 is 1, 2 or 3.
165 Since the input to the (or and, and) is an (add) rather than a (shl), the shift
166 doesn't get folded into the rlwimi instruction. We should ideally see through
167 things like this, rather than forcing llvm to generate the equivalent
169 (shl (add bitfield, C2), C1) with some kind of mask.
171 ===-------------------------------------------------------------------------===
173 Compile this (standard bitfield insert of a constant):
174 void %test(uint* %tmp1) {
175 %tmp2 = load uint* %tmp1 ; <uint> [#uses=1]
176 %tmp5 = or uint %tmp2, 257949696 ; <uint> [#uses=1]
177 %tmp6 = and uint %tmp5, 4018143231 ; <uint> [#uses=1]
178 store uint %tmp6, uint* %tmp1
202 ===-------------------------------------------------------------------------===
206 int %f1(int %a, int %b) {
207 %tmp.1 = and int %a, 15 ; <int> [#uses=1]
208 %tmp.3 = and int %b, 240 ; <int> [#uses=1]
209 %tmp.4 = or int %tmp.3, %tmp.1 ; <int> [#uses=1]
213 without a copy. We make this currently:
216 rlwinm r2, r4, 0, 24, 27
217 rlwimi r2, r3, 0, 28, 31
221 The two-addr pass or RA needs to learn when it is profitable to commute an
222 instruction to avoid a copy AFTER the 2-addr instruction. The 2-addr pass
223 currently only commutes to avoid inserting a copy BEFORE the two addr instr.