1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #include "PPCTargetMachine.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/FormattedStream.h"
22 #include "llvm/Support/TargetRegistry.h"
26 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
27 cl::desc("Disable CTR loops for PPC"));
29 extern "C" void LLVMInitializePowerPCTarget() {
30 // Register the targets
31 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
32 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
35 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
36 StringRef CPU, StringRef FS,
37 const TargetOptions &Options,
38 Reloc::Model RM, CodeModel::Model CM,
41 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
42 Subtarget(TT, CPU, FS, is64Bit),
43 DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
44 FrameLowering(Subtarget), JITInfo(*this, is64Bit),
45 TLInfo(*this), TSInfo(*this),
46 InstrItins(Subtarget.getInstrItineraryData()) {
48 // The binutils for the BG/P are too old for CFI.
49 if (Subtarget.isBGP())
53 void PPC32TargetMachine::anchor() { }
55 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
56 StringRef CPU, StringRef FS,
57 const TargetOptions &Options,
58 Reloc::Model RM, CodeModel::Model CM,
60 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
63 void PPC64TargetMachine::anchor() { }
65 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
66 StringRef CPU, StringRef FS,
67 const TargetOptions &Options,
68 Reloc::Model RM, CodeModel::Model CM,
70 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
74 //===----------------------------------------------------------------------===//
75 // Pass Pipeline Configuration
76 //===----------------------------------------------------------------------===//
79 /// PPC Code Generator Pass Configuration Options.
80 class PPCPassConfig : public TargetPassConfig {
82 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
83 : TargetPassConfig(TM, PM) {}
85 PPCTargetMachine &getPPCTargetMachine() const {
86 return getTM<PPCTargetMachine>();
89 virtual bool addPreRegAlloc();
90 virtual bool addInstSelector();
91 virtual bool addPreEmitPass();
95 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
96 TargetPassConfig *PassConfig = new PPCPassConfig(this, PM);
98 // Override this for PowerPC. Tail merging happily breaks up instruction issue
99 // groups, which typically degrades performance.
100 PassConfig->setEnableTailMerge(false);
105 bool PPCPassConfig::addPreRegAlloc() {
106 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None) {
107 PM->add(createPPCCTRLoops());
113 bool PPCPassConfig::addInstSelector() {
114 // Install an instruction selector.
115 PM->add(createPPCISelDag(getPPCTargetMachine()));
119 bool PPCPassConfig::addPreEmitPass() {
120 // Must run branch selection immediately preceding the asm printer.
121 PM->add(createPPCBranchSelectionPass());
125 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
126 JITCodeEmitter &JCE) {
127 // FIXME: This should be moved to TargetJITInfo!!
128 if (Subtarget.isPPC64())
129 // Temporary workaround for the inability of PPC64 JIT to handle jump
131 Options.DisableJumpTables = true;
133 // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
135 Subtarget.SetJITMode();
137 // Machine code emitter pass for PowerPC.
138 PM.add(createPPCJITCodeEmitterPass(*this, JCE));