1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 #include "PPCTargetMachine.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
26 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
27 cl::desc("Disable CTR loops for PPC"));
29 extern "C" void LLVMInitializePowerPCTarget() {
30 // Register the targets
31 RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
32 RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
33 RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
36 /// Return the datalayout string of a subtarget.
37 static std::string getDataLayoutString(const PPCSubtarget &ST) {
38 const Triple &T = ST.getTargetTriple();
41 std::string Ret = "E";
43 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
45 if (!ST.isPPC64() || T.getOS() == Triple::Lv2)
48 // Note, the alignment values for f64 and i64 on ppc64 in Darwin
49 // documentation are wrong; these are correct (i.e. "what gcc does").
52 // Set support for 128 floats depending on the ABI.
53 if (!ST.isPPC64() || !ST.isSVR4ABI())
54 Ret += "-f128:64:128";
56 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
65 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
66 StringRef CPU, StringRef FS,
67 const TargetOptions &Options,
68 Reloc::Model RM, CodeModel::Model CM,
71 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
72 Subtarget(TT, CPU, FS, is64Bit),
73 DL(getDataLayoutString(Subtarget)), InstrInfo(*this),
74 FrameLowering(Subtarget), JITInfo(*this, is64Bit),
75 TLInfo(*this), TSInfo(*this),
76 InstrItins(Subtarget.getInstrItineraryData()) {
78 // The binutils for the BG/P are too old for CFI.
79 if (Subtarget.isBGP())
84 void PPC32TargetMachine::anchor() { }
86 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
87 StringRef CPU, StringRef FS,
88 const TargetOptions &Options,
89 Reloc::Model RM, CodeModel::Model CM,
91 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
94 void PPC64TargetMachine::anchor() { }
96 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
97 StringRef CPU, StringRef FS,
98 const TargetOptions &Options,
99 Reloc::Model RM, CodeModel::Model CM,
100 CodeGenOpt::Level OL)
101 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
105 //===----------------------------------------------------------------------===//
106 // Pass Pipeline Configuration
107 //===----------------------------------------------------------------------===//
110 /// PPC Code Generator Pass Configuration Options.
111 class PPCPassConfig : public TargetPassConfig {
113 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
114 : TargetPassConfig(TM, PM) {}
116 PPCTargetMachine &getPPCTargetMachine() const {
117 return getTM<PPCTargetMachine>();
120 const PPCSubtarget &getPPCSubtarget() const {
121 return *getPPCTargetMachine().getSubtargetImpl();
124 virtual bool addPreISel();
125 virtual bool addILPOpts();
126 virtual bool addInstSelector();
127 virtual bool addPreSched2();
128 virtual bool addPreEmitPass();
132 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
133 return new PPCPassConfig(this, PM);
136 bool PPCPassConfig::addPreISel() {
137 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
138 addPass(createPPCCTRLoops(getPPCTargetMachine()));
143 bool PPCPassConfig::addILPOpts() {
144 if (getPPCSubtarget().hasISEL()) {
145 addPass(&EarlyIfConverterID);
152 bool PPCPassConfig::addInstSelector() {
153 // Install an instruction selector.
154 addPass(createPPCISelDag(getPPCTargetMachine()));
157 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
158 addPass(createPPCCTRLoopsVerify());
164 bool PPCPassConfig::addPreSched2() {
165 if (getOptLevel() != CodeGenOpt::None)
166 addPass(&IfConverterID);
171 bool PPCPassConfig::addPreEmitPass() {
172 if (getOptLevel() != CodeGenOpt::None)
173 addPass(createPPCEarlyReturnPass());
174 // Must run branch selection immediately preceding the asm printer.
175 addPass(createPPCBranchSelectionPass());
179 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
180 JITCodeEmitter &JCE) {
181 // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
183 Subtarget.SetJITMode();
185 // Machine code emitter pass for PowerPC.
186 PM.add(createPPCJITCodeEmitterPass(*this, JCE));
191 void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
192 // Add first the target-independent BasicTTI pass, then our PPC pass. This
193 // allows the PPC pass to delegate to the target independent layer when
195 PM.add(createBasicTargetTransformInfoPass(this));
196 PM.add(createPPCTargetTransformInfoPass(this));