1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "PPCSubtarget.h"
16 #include "PPCRegisterInfo.h"
17 #include "PPCTargetMachine.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineScheduler.h"
20 #include "llvm/IR/Attributes.h"
21 #include "llvm/IR/Function.h"
22 #include "llvm/IR/GlobalValue.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Host.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Target/TargetMachine.h"
31 #define DEBUG_TYPE "ppc-subtarget"
33 #define GET_SUBTARGETINFO_TARGET_DESC
34 #define GET_SUBTARGETINFO_CTOR
35 #include "PPCGenSubtargetInfo.inc"
37 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
38 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
40 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
42 initializeEnvironment();
43 initSubtargetFeatures(CPU, FS);
47 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
48 const std::string &FS, const PPCTargetMachine &TM)
49 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
50 IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
51 TargetTriple.getArch() == Triple::ppc64le),
52 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
53 InstrInfo(*this), TLInfo(TM, *this), TSInfo(TM.getDataLayout()) {}
55 void PPCSubtarget::initializeEnvironment() {
57 DarwinDirective = PPC::DIR_NONE;
59 Has64BitSupport = false;
88 DeprecatedMFTB = false;
89 DeprecatedDST = false;
90 HasLazyResolverStubs = false;
92 HasInvariantFunctionDescriptors = false;
95 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
96 // Determine default and user specified characteristics
97 std::string CPUName = CPU;
98 if (CPUName.empty()) {
99 // If cross-compiling with -march=ppc64le without -mcpu
100 if (TargetTriple.getArch() == Triple::ppc64le)
105 #if (defined(__APPLE__) || defined(__linux__)) && \
106 (defined(__ppc__) || defined(__powerpc__))
107 if (CPUName == "generic")
108 CPUName = sys::getHostCPUName();
111 // Initialize scheduling itinerary for the specified CPU.
112 InstrItins = getInstrItineraryForCPU(CPUName);
114 // Parse features string.
115 ParseSubtargetFeatures(CPUName, FS);
117 // If the user requested use of 64-bit regs, but the cpu selected doesn't
118 // support it, ignore.
119 if (IsPPC64 && has64BitSupport())
122 // Set up darwin-specific properties.
124 HasLazyResolverStubs = true;
126 // QPX requires a 32-byte aligned stack. Note that we need to do this if
127 // we're compiling for a BG/Q system regardless of whether or not QPX
128 // is enabled because external functions will assume this alignment.
129 if (hasQPX() || isBGQ())
132 // Determine endianness.
133 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
136 /// hasLazyResolverStub - Return true if accesses to the specified global have
137 /// to go through a dyld lazy resolution stub. This means that an extra load
138 /// is required to get the address of the global.
139 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const {
140 // We never have stubs if HasLazyResolverStubs=false or if in static mode.
141 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
143 bool isDecl = GV->isDeclaration();
144 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
146 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
147 GV->hasCommonLinkage() || isDecl;
150 // Embedded cores need aggressive scheduling (and some others also benefit).
151 static bool needsAggressiveScheduling(unsigned Directive) {
153 default: return false;
156 case PPC::DIR_E500mc:
164 bool PPCSubtarget::enableMachineScheduler() const {
165 // Enable MI scheduling for the embedded cores.
166 // FIXME: Enable this for all cores (some additional modeling
167 // may be necessary).
168 return needsAggressiveScheduling(DarwinDirective);
171 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
172 bool PPCSubtarget::enablePostMachineScheduler() const { return true; }
174 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
175 return TargetSubtargetInfo::ANTIDEP_ALL;
178 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
179 CriticalPathRCs.clear();
180 CriticalPathRCs.push_back(isPPC64() ?
181 &PPC::G8RCRegClass : &PPC::GPRCRegClass);
184 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
187 unsigned NumRegionInstrs) const {
188 if (needsAggressiveScheduling(DarwinDirective)) {
189 Policy.OnlyTopDown = false;
190 Policy.OnlyBottomUp = false;
193 // Spilling is generally expensive on all PPC cores, so always enable
194 // register-pressure tracking.
195 Policy.ShouldTrackPressure = true;
198 bool PPCSubtarget::useAA() const {
199 // Use AA during code generation for the embedded cores.
200 return needsAggressiveScheduling(DarwinDirective);
203 bool PPCSubtarget::enableSubRegLiveness() const {
204 return UseSubRegLiveness;
207 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
208 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }