1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PPCInstrBuilder.h"
17 #include "PPCRegisterInfo.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineDebugInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineLocation.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 #include "llvm/Target/TargetFrameInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/ADT/STLExtras.h"
38 /// getRegisterNumbering - Given the enum value for some register, e.g.
39 /// PPC::F14, return the number that it corresponds to (e.g. 14).
40 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
42 case PPC::R0 : case PPC::F0 : case PPC::V0 : case PPC::CR0: return 0;
43 case PPC::R1 : case PPC::F1 : case PPC::V1 : case PPC::CR1: return 1;
44 case PPC::R2 : case PPC::F2 : case PPC::V2 : case PPC::CR2: return 2;
45 case PPC::R3 : case PPC::F3 : case PPC::V3 : case PPC::CR3: return 3;
46 case PPC::R4 : case PPC::F4 : case PPC::V4 : case PPC::CR4: return 4;
47 case PPC::R5 : case PPC::F5 : case PPC::V5 : case PPC::CR5: return 5;
48 case PPC::R6 : case PPC::F6 : case PPC::V6 : case PPC::CR6: return 6;
49 case PPC::R7 : case PPC::F7 : case PPC::V7 : case PPC::CR7: return 7;
50 case PPC::R8 : case PPC::F8 : case PPC::V8 : return 8;
51 case PPC::R9 : case PPC::F9 : case PPC::V9 : return 9;
52 case PPC::R10: case PPC::F10: case PPC::V10: return 10;
53 case PPC::R11: case PPC::F11: case PPC::V11: return 11;
54 case PPC::R12: case PPC::F12: case PPC::V12: return 12;
55 case PPC::R13: case PPC::F13: case PPC::V13: return 13;
56 case PPC::R14: case PPC::F14: case PPC::V14: return 14;
57 case PPC::R15: case PPC::F15: case PPC::V15: return 15;
58 case PPC::R16: case PPC::F16: case PPC::V16: return 16;
59 case PPC::R17: case PPC::F17: case PPC::V17: return 17;
60 case PPC::R18: case PPC::F18: case PPC::V18: return 18;
61 case PPC::R19: case PPC::F19: case PPC::V19: return 19;
62 case PPC::R20: case PPC::F20: case PPC::V20: return 20;
63 case PPC::R21: case PPC::F21: case PPC::V21: return 21;
64 case PPC::R22: case PPC::F22: case PPC::V22: return 22;
65 case PPC::R23: case PPC::F23: case PPC::V23: return 23;
66 case PPC::R24: case PPC::F24: case PPC::V24: return 24;
67 case PPC::R25: case PPC::F25: case PPC::V25: return 25;
68 case PPC::R26: case PPC::F26: case PPC::V26: return 26;
69 case PPC::R27: case PPC::F27: case PPC::V27: return 27;
70 case PPC::R28: case PPC::F28: case PPC::V28: return 28;
71 case PPC::R29: case PPC::F29: case PPC::V29: return 29;
72 case PPC::R30: case PPC::F30: case PPC::V30: return 30;
73 case PPC::R31: case PPC::F31: case PPC::V31: return 31;
75 std::cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
80 PPCRegisterInfo::PPCRegisterInfo()
81 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
82 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
83 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
84 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
85 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
86 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
87 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
88 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
89 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
93 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
94 MachineBasicBlock::iterator MI,
95 unsigned SrcReg, int FrameIdx,
96 const TargetRegisterClass *RC) const {
97 if (SrcReg == PPC::LR) {
98 // FIXME: this spills LR immediately to memory in one step. To do this, we
99 // use R11, which we know cannot be used in the prolog/epilog. This is a
101 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
102 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
103 } else if (RC == PPC::CRRCRegisterClass) {
104 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
105 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
106 } else if (RC == PPC::GPRCRegisterClass) {
107 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
108 } else if (RC == PPC::G8RCRegisterClass) {
109 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx);
110 } else if (RC == PPC::F8RCRegisterClass) {
111 addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
112 } else if (RC == PPC::F4RCRegisterClass) {
113 addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
114 } else if (RC == PPC::VRRCRegisterClass) {
115 // We don't have indexed addressing for vector loads. Emit:
117 // Dest = LVX R0, R11
119 // FIXME: We use R0 here, because it isn't available for RA.
120 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
121 BuildMI(MBB, MI, PPC::STVX, 3)
122 .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
124 assert(0 && "Unknown regclass!");
130 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
131 MachineBasicBlock::iterator MI,
132 unsigned DestReg, int FrameIdx,
133 const TargetRegisterClass *RC) const {
134 if (DestReg == PPC::LR) {
135 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
136 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
137 } else if (RC == PPC::CRRCRegisterClass) {
138 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
139 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
140 } else if (RC == PPC::GPRCRegisterClass) {
141 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
142 } else if (RC == PPC::G8RCRegisterClass) {
143 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx);
144 } else if (RC == PPC::F8RCRegisterClass) {
145 addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
146 } else if (RC == PPC::F4RCRegisterClass) {
147 addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
148 } else if (RC == PPC::VRRCRegisterClass) {
149 // We don't have indexed addressing for vector loads. Emit:
151 // Dest = LVX R0, R11
153 // FIXME: We use R0 here, because it isn't available for RA.
154 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
155 BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
157 assert(0 && "Unknown regclass!");
162 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
163 MachineBasicBlock::iterator MI,
164 unsigned DestReg, unsigned SrcReg,
165 const TargetRegisterClass *RC) const {
166 if (RC == PPC::GPRCRegisterClass) {
167 BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
168 } else if (RC == PPC::G8RCRegisterClass) {
169 BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
170 } else if (RC == PPC::F4RCRegisterClass) {
171 BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg);
172 } else if (RC == PPC::F8RCRegisterClass) {
173 BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg);
174 } else if (RC == PPC::CRRCRegisterClass) {
175 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
176 } else if (RC == PPC::VRRCRegisterClass) {
177 BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
179 std::cerr << "Attempt to copy register that is not GPR or FPR";
184 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
185 /// copy instructions, turning them into load/store instructions.
186 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
188 int FrameIndex) const {
189 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
190 // it takes more than one instruction to store it.
191 unsigned Opc = MI->getOpcode();
193 if ((Opc == PPC::OR4 &&
194 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
195 if (OpNum == 0) { // move -> store
196 unsigned InReg = MI->getOperand(1).getReg();
197 return addFrameReference(BuildMI(PPC::STW,
198 3).addReg(InReg), FrameIndex);
199 } else { // move -> load
200 unsigned OutReg = MI->getOperand(0).getReg();
201 return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex);
203 } else if ((Opc == PPC::OR8 &&
204 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
205 if (OpNum == 0) { // move -> store
206 unsigned InReg = MI->getOperand(1).getReg();
207 return addFrameReference(BuildMI(PPC::STD,
208 3).addReg(InReg), FrameIndex);
209 } else { // move -> load
210 unsigned OutReg = MI->getOperand(0).getReg();
211 return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex);
213 } else if (Opc == PPC::FMRD) {
214 if (OpNum == 0) { // move -> store
215 unsigned InReg = MI->getOperand(1).getReg();
216 return addFrameReference(BuildMI(PPC::STFD,
217 3).addReg(InReg), FrameIndex);
218 } else { // move -> load
219 unsigned OutReg = MI->getOperand(0).getReg();
220 return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex);
222 } else if (Opc == PPC::FMRS) {
223 if (OpNum == 0) { // move -> store
224 unsigned InReg = MI->getOperand(1).getReg();
225 return addFrameReference(BuildMI(PPC::STFS,
226 3).addReg(InReg), FrameIndex);
227 } else { // move -> load
228 unsigned OutReg = MI->getOperand(0).getReg();
229 return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex);
235 //===----------------------------------------------------------------------===//
236 // Stack Frame Processing methods
237 //===----------------------------------------------------------------------===//
239 // hasFP - Return true if the specified function should have a dedicated frame
240 // pointer register. This is true if the function has variable sized allocas or
241 // if frame pointer elimination is disabled.
243 static bool hasFP(const MachineFunction &MF) {
244 const MachineFrameInfo *MFI = MF.getFrameInfo();
245 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
247 // If frame pointers are forced, or if there are variable sized stack objects,
248 // use a frame pointer.
250 return NoFramePointerElim || MFI->hasVarSizedObjects();
253 void PPCRegisterInfo::
254 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
255 MachineBasicBlock::iterator I) const {
257 // If we have a frame pointer, convert as follows:
258 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount
259 // ADJCALLSTACKUP -> addi, r1, r1, amount
260 MachineInstr *Old = I;
261 unsigned Amount = Old->getOperand(0).getImmedValue();
263 // We need to keep the stack aligned properly. To do this, we round the
264 // amount of space needed for the outgoing arguments up to the next
265 // alignment boundary.
266 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
267 Amount = (Amount+Align-1)/Align*Align;
269 // Replace the pseudo instruction with a new instruction...
270 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
271 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(-Amount);
273 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
274 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(Amount);
282 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
284 MachineInstr &MI = *II;
285 MachineBasicBlock &MBB = *MI.getParent();
286 MachineFunction &MF = *MBB.getParent();
288 while (!MI.getOperand(i).isFrameIndex()) {
290 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
293 int FrameIndex = MI.getOperand(i).getFrameIndex();
295 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
296 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
298 // Take into account whether it's an add or mem instruction
299 unsigned OffIdx = (i == 2) ? 1 : 2;
301 // Now add the frame object offset to the offset from r1.
302 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
303 MI.getOperand(OffIdx).getImmedValue();
305 // If we're not using a Frame Pointer that has been set to the value of the
306 // SP before having the stack size subtracted from it, then add the stack size
307 // to Offset to get the correct offset.
308 Offset += MF.getFrameInfo()->getStackSize();
310 if (Offset > 32767 || Offset < -32768) {
311 // Insert a set of r0 with the full offset value before the ld, st, or add
312 MachineBasicBlock *MBB = MI.getParent();
313 BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16);
314 BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset);
316 // convert into indexed form of the instruction
317 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
318 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
319 assert(ImmToIdxMap.count(MI.getOpcode()) &&
320 "No indexed form of load or store available!");
321 unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
322 MI.setOpcode(NewOpcode);
323 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
324 MI.SetMachineOperandReg(2, PPC::R0);
326 switch (MI.getOpcode()) {
331 assert((Offset & 3) == 0 && "Invalid frame offset!");
332 Offset >>= 2; // The actual encoded value has the low two bits zero.
335 MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
340 /// VRRegNo - Map from a numbered VR register to its enum value.
342 static const unsigned short VRRegNo[] = {
343 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
344 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
345 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
346 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
349 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
350 // instruction selector. Based on the vector registers that have been used,
351 // transform this into the appropriate ORI instruction.
352 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) {
353 unsigned UsedRegMask = 0;
354 for (unsigned i = 0; i != 32; ++i)
355 if (UsedRegs[VRRegNo[i]])
356 UsedRegMask |= 1 << (31-i);
358 // Live in and live out values already must be in the mask, so don't bother
360 MachineFunction *MF = MI->getParent()->getParent();
361 for (MachineFunction::livein_iterator I =
362 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) {
363 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
364 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
365 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
367 for (MachineFunction::liveout_iterator I =
368 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) {
369 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
370 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
371 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
374 unsigned SrcReg = MI->getOperand(1).getReg();
375 unsigned DstReg = MI->getOperand(0).getReg();
376 // If no registers are used, turn this into a copy.
377 if (UsedRegMask == 0) {
378 if (SrcReg != DstReg)
379 BuildMI(*MI->getParent(), MI, PPC::OR4, 2, DstReg)
380 .addReg(SrcReg).addReg(SrcReg);
381 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
382 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
383 .addReg(SrcReg).addImm(UsedRegMask);
384 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
385 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
386 .addReg(SrcReg).addImm(UsedRegMask >> 16);
388 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
389 .addReg(SrcReg).addImm(UsedRegMask >> 16);
390 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
391 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
394 // Remove the old UPDATE_VRSAVE instruction.
395 MI->getParent()->erase(MI);
399 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
400 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
401 MachineBasicBlock::iterator MBBI = MBB.begin();
402 MachineFrameInfo *MFI = MF.getFrameInfo();
403 MachineDebugInfo *DebugInfo = MFI->getMachineDebugInfo();
405 // Do we have a frame pointer for this function?
406 bool HasFP = hasFP(MF);
408 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
410 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
411 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
412 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs());
417 // Move MBBI back to the beginning of the function.
420 // Get the number of bytes to allocate from the FrameInfo
421 unsigned NumBytes = MFI->getStackSize();
423 // Get the alignments provided by the target, and the maximum alignment
424 // (if any) of the fixed frame objects.
425 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
426 unsigned MaxAlign = MFI->getMaxAlignment();
428 // If we have calls, we cannot use the red zone to store callee save registers
429 // and we must set up a stack frame, so calculate the necessary size here.
430 if (MFI->hasCalls()) {
431 // We reserve argument space for call sites in the function immediately on
432 // entry to the current function. This eliminates the need for add/sub
433 // brackets around call sites.
434 NumBytes += MFI->getMaxCallFrameSize();
437 // If we are a leaf function, and use up to 224 bytes of stack space,
438 // and don't have a frame pointer, then we do not need to adjust the stack
439 // pointer (we fit in the Red Zone).
440 if ((NumBytes == 0) || (NumBytes <= 224 && !HasFP && !MFI->hasCalls() &&
441 MaxAlign <= TargetAlign)) {
442 MFI->setStackSize(0);
446 // Add the size of R1 to NumBytes size for the store of R1 to the bottom
447 // of the stack and round the size to a multiple of the alignment.
448 unsigned Align = std::max(TargetAlign, MaxAlign);
449 unsigned GPRSize = 4;
450 unsigned Size = HasFP ? GPRSize + GPRSize : GPRSize;
451 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
453 // Update frame info to pretend that this is part of the stack...
454 MFI->setStackSize(NumBytes);
455 int NegNumbytes = -NumBytes;
457 // Adjust stack pointer: r1 -= numbytes.
458 // If there is a preferred stack alignment, align R1 now
459 if (MaxAlign > TargetAlign) {
460 assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!");
461 assert(isInt16(MaxAlign-NumBytes) && "Unhandled stack size and alignment!");
462 BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
463 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
464 BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
465 .addSImm(MaxAlign-NumBytes);
466 BuildMI(MBB, MBBI, PPC::STWUX, 3)
467 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
468 } else if (NumBytes <= 32768) {
469 BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addSImm(NegNumbytes)
472 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
473 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
474 .addImm(NegNumbytes & 0xFFFF);
475 BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
479 if (DebugInfo && DebugInfo->hasInfo()) {
480 std::vector<MachineMove *> &Moves = DebugInfo->getFrameMoves();
481 unsigned LabelID = DebugInfo->NextLabelID();
483 // Show update of SP.
484 MachineLocation Dst(MachineLocation::VirtualFP);
485 MachineLocation Src(MachineLocation::VirtualFP, NegNumbytes);
486 Moves.push_back(new MachineMove(LabelID, Dst, Src));
488 BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addSImm(LabelID);
491 // If there is a frame pointer, copy R1 (SP) into R31 (FP)
493 BuildMI(MBB, MBBI, PPC::STW, 3)
494 .addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
495 BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
499 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
500 MachineBasicBlock &MBB) const {
501 MachineBasicBlock::iterator MBBI = prior(MBB.end());
502 assert(MBBI->getOpcode() == PPC::BLR &&
503 "Can only insert epilog into returning blocks");
505 // Get alignment info so we know how to restore r1
506 const MachineFrameInfo *MFI = MF.getFrameInfo();
507 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
509 // Get the number of bytes allocated from the FrameInfo.
510 unsigned NumBytes = MFI->getStackSize();
511 unsigned GPRSize = 4;
514 // If this function has a frame pointer, load the saved stack pointer from
517 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31)
518 .addSImm(GPRSize).addReg(PPC::R31);
521 // The loaded (or persistent) stack pointer value is offseted by the 'stwu'
522 // on entry to the function. Add this offset back now.
523 if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) {
524 BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
525 .addReg(PPC::R1).addSImm(NumBytes);
527 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
532 unsigned PPCRegisterInfo::getRARegister() const {
536 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
537 return hasFP(MF) ? PPC::R31 : PPC::R1;
540 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove *> &Moves)
542 // Initial state is the frame pointer is R1.
543 MachineLocation Dst(MachineLocation::VirtualFP);
544 MachineLocation Src(PPC::R1, 0);
545 Moves.push_back(new MachineMove(0, Dst, Src));
548 #include "PPCGenRegisterInfo.inc"