1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "reginfo"
16 #include "PPCRegisterInfo.h"
18 #include "PPCFrameLowering.h"
19 #include "PPCInstrBuilder.h"
20 #include "PPCMachineFunctionInfo.h"
21 #include "PPCSubtarget.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/RegisterScavenging.h"
30 #include "llvm/CodeGen/ValueTypes.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetFrameLowering.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
46 #define GET_REGINFO_TARGET_DESC
47 #include "PPCGenRegisterInfo.inc"
51 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
52 const TargetInstrInfo &tii)
53 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
55 ST.isPPC64() ? 0 : 1),
56 Subtarget(ST), TII(tii) {
57 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
58 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
59 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
60 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
61 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
62 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
63 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
64 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
67 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
68 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
69 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
70 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
71 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
74 /// getPointerRegClass - Return the register class to use to hold pointers.
75 /// This is used for addressing modes.
76 const TargetRegisterClass *
77 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
79 if (Subtarget.isPPC64())
80 return &PPC::G8RCRegClass;
81 return &PPC::GPRCRegClass;
85 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
86 if (Subtarget.isDarwinABI())
87 return Subtarget.isPPC64() ? CSR_Darwin64_SaveList :
88 CSR_Darwin32_SaveList;
90 return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList;
94 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
95 if (Subtarget.isDarwinABI())
96 return Subtarget.isPPC64() ? CSR_Darwin64_RegMask :
99 return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask;
102 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
103 BitVector Reserved(getNumRegs());
104 const PPCFrameLowering *PPCFI =
105 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
107 Reserved.set(PPC::R0);
108 Reserved.set(PPC::R1);
109 Reserved.set(PPC::LR);
110 Reserved.set(PPC::LR8);
111 Reserved.set(PPC::RM);
113 // The SVR4 ABI reserves r2 and r13
114 if (Subtarget.isSVR4ABI()) {
115 Reserved.set(PPC::R2); // System-reserved register
116 Reserved.set(PPC::R13); // Small Data Area pointer register
119 // On PPC64, r13 is the thread pointer. Never allocate this register.
120 // Note that this is over conservative, as it also prevents allocation of R31
121 // when the FP is not needed.
122 if (Subtarget.isPPC64()) {
123 Reserved.set(PPC::R13);
124 Reserved.set(PPC::R31);
126 Reserved.set(PPC::X0);
127 Reserved.set(PPC::X1);
128 Reserved.set(PPC::X13);
129 Reserved.set(PPC::X31);
131 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
132 if (Subtarget.isSVR4ABI()) {
133 Reserved.set(PPC::X2);
137 if (PPCFI->needsFP(MF))
138 Reserved.set(PPC::R31);
144 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
145 MachineFunction &MF) const {
146 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
147 const unsigned DefaultSafety = 1;
149 switch (RC->getID()) {
152 case PPC::G8RCRegClassID:
153 case PPC::GPRCRegClassID: {
154 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
155 return 32 - FP - DefaultSafety;
157 case PPC::F8RCRegClassID:
158 case PPC::F4RCRegClassID:
159 case PPC::VRRCRegClassID:
160 return 32 - DefaultSafety;
161 case PPC::CRRCRegClassID:
162 return 8 - DefaultSafety;
167 PPCRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
168 switch (RC->getID()) {
169 case PPC::G8RCRegClassID:
170 case PPC::GPRCRegClassID:
171 case PPC::F8RCRegClassID:
172 case PPC::F4RCRegClassID:
173 case PPC::VRRCRegClassID:
180 //===----------------------------------------------------------------------===//
181 // Stack Frame Processing methods
182 //===----------------------------------------------------------------------===//
184 /// lowerDynamicAlloc - Generate the code for allocating an object in the
185 /// current frame. The sequence of code with be in the general form
187 /// addi R0, SP, \#frameSize ; get the address of the previous frame
188 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
189 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
191 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
192 int SPAdj, RegScavenger *RS) const {
193 // Get the instruction.
194 MachineInstr &MI = *II;
195 // Get the instruction's basic block.
196 MachineBasicBlock &MBB = *MI.getParent();
197 // Get the basic block's function.
198 MachineFunction &MF = *MBB.getParent();
199 // Get the frame info.
200 MachineFrameInfo *MFI = MF.getFrameInfo();
201 // Determine whether 64-bit pointers are used.
202 bool LP64 = Subtarget.isPPC64();
203 DebugLoc dl = MI.getDebugLoc();
205 // Get the maximum call stack size.
206 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
207 // Get the total frame size.
208 unsigned FrameSize = MFI->getStackSize();
210 // Get stack alignments.
211 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
212 unsigned MaxAlign = MFI->getMaxAlignment();
213 if (MaxAlign > TargetAlign)
214 report_fatal_error("Dynamic alloca with large aligns not supported");
216 // Determine the previous frame's address. If FrameSize can't be
217 // represented as 16 bits or we need special alignment, then we load the
218 // previous frame's address from 0(SP). Why not do an addis of the hi?
219 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
220 // Constructing the constant and adding would take 3 instructions.
221 // Fortunately, a frame greater than 32K is rare.
222 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
223 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
224 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
226 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
227 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
231 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
235 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
240 // Grow the stack and update the stack pointer link, then determine the
241 // address of new allocated space.
243 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
244 .addReg(Reg, RegState::Kill)
246 .addReg(MI.getOperand(1).getReg());
247 if (!MI.getOperand(1).isKill())
248 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
250 .addImm(maxCallFrameSize);
252 // Implicitly kill the register.
253 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
255 .addImm(maxCallFrameSize)
256 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
258 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
259 .addReg(Reg, RegState::Kill)
261 .addReg(MI.getOperand(1).getReg());
263 if (!MI.getOperand(1).isKill())
264 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
266 .addImm(maxCallFrameSize);
268 // Implicitly kill the register.
269 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
271 .addImm(maxCallFrameSize)
272 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
275 // Discard the DYNALLOC instruction.
279 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
280 /// reserving a whole register (R0), we scrounge for one here. This generates
283 /// mfcr rA ; Move the conditional register into GPR rA.
284 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
285 /// stw rA, FI ; Store rA to the frame.
287 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
288 unsigned FrameIndex, int SPAdj,
289 RegScavenger *RS) const {
290 // Get the instruction.
291 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
292 // Get the instruction's basic block.
293 MachineBasicBlock &MBB = *MI.getParent();
294 DebugLoc dl = MI.getDebugLoc();
296 // FIXME: Once LLVM supports creating virtual registers here, or the register
297 // scavenger can return multiple registers, stop using reserved registers
302 bool LP64 = Subtarget.isPPC64();
303 unsigned Reg = LP64 ? PPC::X0 : PPC::R0;
304 unsigned SrcReg = MI.getOperand(0).getReg();
306 // We need to store the CR in the low 4-bits of the saved value. First, issue
307 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg.
308 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg)
309 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
311 // If the saved register wasn't CR0, shift the bits left so that they are in
313 if (SrcReg != PPC::CR0)
314 // rlwinm rA, rA, ShiftBits, 0, 31.
315 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
316 .addReg(Reg, RegState::Kill)
317 .addImm(getPPCRegisterNumbering(SrcReg) * 4)
321 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
322 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
325 // Discard the pseudo instruction.
329 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
330 unsigned FrameIndex, int SPAdj,
331 RegScavenger *RS) const {
332 // Get the instruction.
333 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
334 // Get the instruction's basic block.
335 MachineBasicBlock &MBB = *MI.getParent();
336 DebugLoc dl = MI.getDebugLoc();
338 // FIXME: Once LLVM supports creating virtual registers here, or the register
339 // scavenger can return multiple registers, stop using reserved registers
344 bool LP64 = Subtarget.isPPC64();
345 unsigned Reg = LP64 ? PPC::X0 : PPC::R0;
346 unsigned DestReg = MI.getOperand(0).getReg();
347 assert(MI.definesRegister(DestReg) &&
348 "RESTORE_CR does not define its destination");
350 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
353 // If the reloaded register isn't CR0, shift the bits right so that they are
354 // in the right CR's slot.
355 if (DestReg != PPC::CR0) {
356 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4;
357 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
358 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
359 .addReg(Reg).addImm(32-ShiftBits).addImm(0)
363 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg)
366 // Discard the pseudo instruction.
371 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
372 unsigned Reg, int &FrameIdx) const {
374 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
375 // ABI, return true to prevent allocating an additional frame slot.
376 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
377 // is arbitrary and will be subsequently ignored. For 32-bit, we have
378 // previously created the stack slot if needed, so return its FrameIdx.
379 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
380 if (Subtarget.isPPC64())
383 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
384 FrameIdx = FI->getCRSpillFrameIndex();
392 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
393 int SPAdj, unsigned FIOperandNum,
394 RegScavenger *RS) const {
395 assert(SPAdj == 0 && "Unexpected");
397 // Get the instruction.
398 MachineInstr &MI = *II;
399 // Get the instruction's basic block.
400 MachineBasicBlock &MBB = *MI.getParent();
401 // Get the basic block's function.
402 MachineFunction &MF = *MBB.getParent();
403 // Get the frame info.
404 MachineFrameInfo *MFI = MF.getFrameInfo();
405 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
406 DebugLoc dl = MI.getDebugLoc();
408 // Take into account whether it's an add or mem instruction
409 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
410 if (MI.isInlineAsm())
411 OffsetOperandNo = FIOperandNum-1;
413 // Get the frame index.
414 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
416 // Get the frame pointer save index. Users of this index are primarily
417 // DYNALLOC instructions.
418 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
419 int FPSI = FI->getFramePointerSaveIndex();
420 // Get the instruction opcode.
421 unsigned OpC = MI.getOpcode();
423 // Special case for dynamic alloca.
424 if (FPSI && FrameIndex == FPSI &&
425 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
426 lowerDynamicAlloc(II, SPAdj, RS);
430 // Special case for pseudo-ops SPILL_CR and RESTORE_CR.
431 if (OpC == PPC::SPILL_CR) {
432 lowerCRSpilling(II, FrameIndex, SPAdj, RS);
434 } else if (OpC == PPC::RESTORE_CR) {
435 lowerCRRestore(II, FrameIndex, SPAdj, RS);
439 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
441 bool is64Bit = Subtarget.isPPC64();
442 MI.getOperand(FIOperandNum).ChangeToRegister(TFI->hasFP(MF) ?
443 (is64Bit ? PPC::X31 : PPC::R31) :
444 (is64Bit ? PPC::X1 : PPC::R1),
447 // Figure out if the offset in the instruction is shifted right two bits. This
448 // is true for instructions like "STD", which the machine implicitly adds two
450 bool isIXAddr = false;
460 // Now add the frame object offset to the offset from r1.
461 int Offset = MFI->getObjectOffset(FrameIndex);
463 Offset += MI.getOperand(OffsetOperandNo).getImm();
465 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
467 // If we're not using a Frame Pointer that has been set to the value of the
468 // SP before having the stack size subtracted from it, then add the stack size
469 // to Offset to get the correct offset.
470 // Naked functions have stack size 0, although getStackSize may not reflect that
471 // because we didn't call all the pieces that compute it for naked functions.
472 if (!MF.getFunction()->getAttributes().
473 hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked))
474 Offset += MFI->getStackSize();
476 // If we can, encode the offset directly into the instruction. If this is a
477 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
478 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
479 // clear can be encoded. This is extremely uncommon, because normally you
480 // only "std" to a stack slot that is at least 4-byte aligned, but it can
481 // happen in invalid code.
482 if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
483 (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) {
485 Offset >>= 2; // The actual encoded value has the low two bits zero.
486 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
490 // The offset doesn't fit into a single register, scavenge one to build the
493 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
494 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
495 unsigned SReg = MF.getRegInfo().createVirtualRegister(is64Bit ? G8RC : GPRC);
497 // Insert a set of rA with the full offset value before the ld, st, or add
498 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg)
499 .addImm(Offset >> 16);
500 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
501 .addReg(SReg, RegState::Kill)
504 // Convert into indexed form of the instruction:
506 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
507 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
508 unsigned OperandBase;
510 if (OpC != TargetOpcode::INLINEASM) {
511 assert(ImmToIdxMap.count(OpC) &&
512 "No indexed form of load or store available!");
513 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
514 MI.setDesc(TII.get(NewOpcode));
517 OperandBase = OffsetOperandNo;
520 unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
521 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
522 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
525 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
526 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
528 if (!Subtarget.isPPC64())
529 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
531 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
534 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
535 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
538 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
539 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;