1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PPCInstrBuilder.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCRegisterInfo.h"
19 #include "PPCFrameInfo.h"
20 #include "PPCSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Type.h"
23 #include "llvm/CodeGen/ValueTypes.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineLocation.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/Target/TargetFrameInfo.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
42 /// getRegisterNumbering - Given the enum value for some register, e.g.
43 /// PPC::F14, return the number that it corresponds to (e.g. 14).
44 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
47 case R0 : case X0 : case F0 : case V0 : case CR0: return 0;
48 case R1 : case X1 : case F1 : case V1 : case CR1: return 1;
49 case R2 : case X2 : case F2 : case V2 : case CR2: return 2;
50 case R3 : case X3 : case F3 : case V3 : case CR3: return 3;
51 case R4 : case X4 : case F4 : case V4 : case CR4: return 4;
52 case R5 : case X5 : case F5 : case V5 : case CR5: return 5;
53 case R6 : case X6 : case F6 : case V6 : case CR6: return 6;
54 case R7 : case X7 : case F7 : case V7 : case CR7: return 7;
55 case R8 : case X8 : case F8 : case V8 : return 8;
56 case R9 : case X9 : case F9 : case V9 : return 9;
57 case R10: case X10: case F10: case V10: return 10;
58 case R11: case X11: case F11: case V11: return 11;
59 case R12: case X12: case F12: case V12: return 12;
60 case R13: case X13: case F13: case V13: return 13;
61 case R14: case X14: case F14: case V14: return 14;
62 case R15: case X15: case F15: case V15: return 15;
63 case R16: case X16: case F16: case V16: return 16;
64 case R17: case X17: case F17: case V17: return 17;
65 case R18: case X18: case F18: case V18: return 18;
66 case R19: case X19: case F19: case V19: return 19;
67 case R20: case X20: case F20: case V20: return 20;
68 case R21: case X21: case F21: case V21: return 21;
69 case R22: case X22: case F22: case V22: return 22;
70 case R23: case X23: case F23: case V23: return 23;
71 case R24: case X24: case F24: case V24: return 24;
72 case R25: case X25: case F25: case V25: return 25;
73 case R26: case X26: case F26: case V26: return 26;
74 case R27: case X27: case F27: case V27: return 27;
75 case R28: case X28: case F28: case V28: return 28;
76 case R29: case X29: case F29: case V29: return 29;
77 case R30: case X30: case F30: case V30: return 30;
78 case R31: case X31: case F31: case V31: return 31;
80 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
85 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
86 const TargetInstrInfo &tii)
87 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
88 Subtarget(ST), TII(tii) {
89 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
90 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
91 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
92 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
93 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
94 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
95 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
96 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
97 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
101 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
102 MachineBasicBlock::iterator MI,
103 unsigned SrcReg, int FrameIdx,
104 const TargetRegisterClass *RC) const {
105 if (RC == PPC::GPRCRegisterClass) {
106 if (SrcReg != PPC::LR) {
107 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(SrcReg),
110 // FIXME: this spills LR immediately to memory in one step. To do this,
111 // we use R11, which we know cannot be used in the prolog/epilog. This is
113 BuildMI(MBB, MI, TII.get(PPC::MFLR), PPC::R11);
114 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(PPC::R11),
117 } else if (RC == PPC::G8RCRegisterClass) {
118 if (SrcReg != PPC::LR8) {
119 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)).addReg(SrcReg),
122 // FIXME: this spills LR immediately to memory in one step. To do this,
123 // we use R11, which we know cannot be used in the prolog/epilog. This is
125 BuildMI(MBB, MI, TII.get(PPC::MFLR8), PPC::X11);
126 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)).addReg(PPC::X11),
129 } else if (RC == PPC::F8RCRegisterClass) {
130 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD)).addReg(SrcReg),
132 } else if (RC == PPC::F4RCRegisterClass) {
133 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS)).addReg(SrcReg),
135 } else if (RC == PPC::CRRCRegisterClass) {
136 // FIXME: We use R0 here, because it isn't available for RA.
137 // We need to store the CR in the low 4-bits of the saved value. First,
138 // issue a MFCR to save all of the CRBits.
139 BuildMI(MBB, MI, TII.get(PPC::MFCR), PPC::R0);
141 // If the saved register wasn't CR0, shift the bits left so that they are in
143 if (SrcReg != PPC::CR0) {
144 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
145 // rlwinm r0, r0, ShiftBits, 0, 31.
146 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0)
147 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31);
150 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(PPC::R0),
152 } else if (RC == PPC::VRRCRegisterClass) {
153 // We don't have indexed addressing for vector loads. Emit:
155 // Dest = LVX R0, R11
157 // FIXME: We use R0 here, because it isn't available for RA.
158 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
160 BuildMI(MBB, MI, TII.get(PPC::STVX))
161 .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
163 assert(0 && "Unknown regclass!");
169 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
170 MachineBasicBlock::iterator MI,
171 unsigned DestReg, int FrameIdx,
172 const TargetRegisterClass *RC) const {
173 if (RC == PPC::GPRCRegisterClass) {
174 if (DestReg != PPC::LR) {
175 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), DestReg), FrameIdx);
177 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R11),FrameIdx);
178 BuildMI(MBB, MI, TII.get(PPC::MTLR)).addReg(PPC::R11);
180 } else if (RC == PPC::G8RCRegisterClass) {
181 if (DestReg != PPC::LR8) {
182 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), DestReg), FrameIdx);
184 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), PPC::R11), FrameIdx);
185 BuildMI(MBB, MI, TII.get(PPC::MTLR8)).addReg(PPC::R11);
187 } else if (RC == PPC::F8RCRegisterClass) {
188 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFD), DestReg), FrameIdx);
189 } else if (RC == PPC::F4RCRegisterClass) {
190 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFS), DestReg), FrameIdx);
191 } else if (RC == PPC::CRRCRegisterClass) {
192 // FIXME: We use R0 here, because it isn't available for RA.
193 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R0), FrameIdx);
195 // If the reloaded register isn't CR0, shift the bits right so that they are
196 // in the right CR's slot.
197 if (DestReg != PPC::CR0) {
198 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
199 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
200 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0)
201 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31);
204 BuildMI(MBB, MI, TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0);
205 } else if (RC == PPC::VRRCRegisterClass) {
206 // We don't have indexed addressing for vector loads. Emit:
208 // Dest = LVX R0, R11
210 // FIXME: We use R0 here, because it isn't available for RA.
211 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
213 BuildMI(MBB, MI, TII.get(PPC::LVX),DestReg).addReg(PPC::R0).addReg(PPC::R0);
215 assert(0 && "Unknown regclass!");
220 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
221 MachineBasicBlock::iterator MI,
222 unsigned DestReg, unsigned SrcReg,
223 const TargetRegisterClass *RC) const {
224 if (RC == PPC::GPRCRegisterClass) {
225 BuildMI(MBB, MI, TII.get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
226 } else if (RC == PPC::G8RCRegisterClass) {
227 BuildMI(MBB, MI, TII.get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
228 } else if (RC == PPC::F4RCRegisterClass) {
229 BuildMI(MBB, MI, TII.get(PPC::FMRS), DestReg).addReg(SrcReg);
230 } else if (RC == PPC::F8RCRegisterClass) {
231 BuildMI(MBB, MI, TII.get(PPC::FMRD), DestReg).addReg(SrcReg);
232 } else if (RC == PPC::CRRCRegisterClass) {
233 BuildMI(MBB, MI, TII.get(PPC::MCRF), DestReg).addReg(SrcReg);
234 } else if (RC == PPC::VRRCRegisterClass) {
235 BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
237 cerr << "Attempt to copy register that is not GPR or FPR";
242 const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const {
243 // 32-bit Darwin calling convention.
244 static const unsigned Darwin32_CalleeSavedRegs[] = {
245 PPC::R13, PPC::R14, PPC::R15,
246 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
247 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
248 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
249 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
251 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
252 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
253 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
254 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
257 PPC::CR2, PPC::CR3, PPC::CR4,
258 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
259 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
260 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
264 // 64-bit Darwin calling convention.
265 static const unsigned Darwin64_CalleeSavedRegs[] = {
267 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
268 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
269 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
270 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
272 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
273 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
274 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
275 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
278 PPC::CR2, PPC::CR3, PPC::CR4,
279 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
280 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
281 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
286 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs :
287 Darwin32_CalleeSavedRegs;
290 const TargetRegisterClass* const*
291 PPCRegisterInfo::getCalleeSavedRegClasses() const {
292 // 32-bit Darwin calling convention.
293 static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = {
294 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
295 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
296 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
297 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
298 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
300 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
301 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
302 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
303 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
304 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
306 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
308 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
309 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
310 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
312 &PPC::GPRCRegClass, 0
315 // 64-bit Darwin calling convention.
316 static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = {
317 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
318 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
319 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
320 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
321 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
323 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
324 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
325 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
326 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
327 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
329 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
331 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
332 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
333 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
335 &PPC::G8RCRegClass, 0
338 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses :
339 Darwin32_CalleeSavedRegClasses;
342 // needsFP - Return true if the specified function should have a dedicated frame
343 // pointer register. This is true if the function has variable sized allocas or
344 // if frame pointer elimination is disabled.
346 static bool needsFP(const MachineFunction &MF) {
347 const MachineFrameInfo *MFI = MF.getFrameInfo();
348 return NoFramePointerElim || MFI->hasVarSizedObjects();
351 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
352 BitVector Reserved(getNumRegs());
353 Reserved.set(PPC::R0);
354 Reserved.set(PPC::R1);
355 Reserved.set(PPC::LR);
356 // In Linux, r2 is reserved for the OS.
357 if (!Subtarget.isDarwin())
358 Reserved.set(PPC::R2);
359 // On PPC64, r13 is the thread pointer. Never allocate this register.
360 // Note that this is overconservative, as it also prevents allocation of
361 // R31 when the FP is not needed.
362 if (Subtarget.isPPC64()) {
363 Reserved.set(PPC::R13);
364 Reserved.set(PPC::R31);
367 Reserved.set(PPC::R31);
371 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
372 /// copy instructions, turning them into load/store instructions.
373 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
375 int FrameIndex) const {
376 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
377 // it takes more than one instruction to store it.
378 unsigned Opc = MI->getOpcode();
380 MachineInstr *NewMI = NULL;
381 if ((Opc == PPC::OR &&
382 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
383 if (OpNum == 0) { // move -> store
384 unsigned InReg = MI->getOperand(1).getReg();
385 NewMI = addFrameReference(BuildMI(TII.get(PPC::STW)).addReg(InReg),
387 } else { // move -> load
388 unsigned OutReg = MI->getOperand(0).getReg();
389 NewMI = addFrameReference(BuildMI(TII.get(PPC::LWZ), OutReg),
392 } else if ((Opc == PPC::OR8 &&
393 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
394 if (OpNum == 0) { // move -> store
395 unsigned InReg = MI->getOperand(1).getReg();
396 NewMI = addFrameReference(BuildMI(TII.get(PPC::STD)).addReg(InReg),
398 } else { // move -> load
399 unsigned OutReg = MI->getOperand(0).getReg();
400 NewMI = addFrameReference(BuildMI(TII.get(PPC::LD), OutReg), FrameIndex);
402 } else if (Opc == PPC::FMRD) {
403 if (OpNum == 0) { // move -> store
404 unsigned InReg = MI->getOperand(1).getReg();
405 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFD)).addReg(InReg),
407 } else { // move -> load
408 unsigned OutReg = MI->getOperand(0).getReg();
409 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFD), OutReg), FrameIndex);
411 } else if (Opc == PPC::FMRS) {
412 if (OpNum == 0) { // move -> store
413 unsigned InReg = MI->getOperand(1).getReg();
414 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFS)).addReg(InReg),
416 } else { // move -> load
417 unsigned OutReg = MI->getOperand(0).getReg();
418 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFS), OutReg), FrameIndex);
423 NewMI->copyKillDeadInfo(MI);
427 //===----------------------------------------------------------------------===//
428 // Stack Frame Processing methods
429 //===----------------------------------------------------------------------===//
431 // hasFP - Return true if the specified function actually has a dedicated frame
432 // pointer register. This is true if the function needs a frame pointer and has
433 // a non-zero stack size.
434 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
435 const MachineFrameInfo *MFI = MF.getFrameInfo();
436 return MFI->getStackSize() && needsFP(MF);
439 /// usesLR - Returns if the link registers (LR) has been used in the function.
441 bool PPCRegisterInfo::usesLR(MachineFunction &MF) const {
442 const bool *PhysRegsUsed = MF.getUsedPhysregs();
443 return PhysRegsUsed[getRARegister()];
446 void PPCRegisterInfo::
447 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
448 MachineBasicBlock::iterator I) const {
449 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
453 /// LowerDynamicAlloc - Generate the code for allocating an object in the
454 /// current frame. The sequence of code with be in the general form
456 /// addi R0, SP, #frameSize ; get the address of the previous frame
457 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
458 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation
460 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
461 // Get the instruction.
462 MachineInstr &MI = *II;
463 // Get the instruction's basic block.
464 MachineBasicBlock &MBB = *MI.getParent();
465 // Get the basic block's function.
466 MachineFunction &MF = *MBB.getParent();
467 // Get the frame info.
468 MachineFrameInfo *MFI = MF.getFrameInfo();
469 // Determine whether 64-bit pointers are used.
470 bool LP64 = Subtarget.isPPC64();
472 // Get the maximum call stack size.
473 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
474 // Get the total frame size.
475 unsigned FrameSize = MFI->getStackSize();
477 // Get stack alignments.
478 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
479 unsigned MaxAlign = MFI->getMaxAlignment();
480 assert(MaxAlign <= TargetAlign &&
481 "Dynamic alloca with large aligns not supported");
483 // Determine the previous frame's address. If FrameSize can't be
484 // represented as 16 bits or we need special alignment, then we load the
485 // previous frame's address from 0(SP). Why not do an addis of the hi?
486 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
487 // Constructing the constant and adding would take 3 instructions.
488 // Fortunately, a frame greater than 32K is rare.
489 if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
490 BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0)
494 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
498 BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0)
503 // Grow the stack and update the stack pointer link, then
504 // determine the address of new allocated space.
506 BuildMI(MBB, II, TII.get(PPC::STDUX))
509 .addReg(MI.getOperand(1).getReg());
510 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
512 .addImm(maxCallFrameSize);
514 BuildMI(MBB, II, TII.get(PPC::STWUX))
517 .addReg(MI.getOperand(1).getReg());
518 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
520 .addImm(maxCallFrameSize);
523 // Discard the DYNALLOC instruction.
528 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
529 // Get the instruction.
530 MachineInstr &MI = *II;
531 // Get the instruction's basic block.
532 MachineBasicBlock &MBB = *MI.getParent();
533 // Get the basic block's function.
534 MachineFunction &MF = *MBB.getParent();
535 // Get the frame info.
536 MachineFrameInfo *MFI = MF.getFrameInfo();
538 // Find out which operand is the frame index.
540 while (!MI.getOperand(i).isFrameIndex()) {
542 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
544 // Take into account whether it's an add or mem instruction
545 unsigned OffIdx = (i == 2) ? 1 : 2;
546 if (MI.getOpcode() == TargetInstrInfo::INLINEASM)
549 // Get the frame index.
550 int FrameIndex = MI.getOperand(i).getFrameIndex();
552 // Get the frame pointer save index. Users of this index are primarily
553 // DYNALLOC instructions.
554 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
555 int FPSI = FI->getFramePointerSaveIndex();
556 // Get the instruction opcode.
557 unsigned OpC = MI.getOpcode();
559 // Special case for dynamic alloca.
560 if (FPSI && FrameIndex == FPSI &&
561 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
562 lowerDynamicAlloc(II);
566 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
567 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, false);
569 // Figure out if the offset in the instruction is shifted right two bits. This
570 // is true for instructions like "STD", which the machine implicitly adds two
572 bool isIXAddr = false;
582 // Now add the frame object offset to the offset from r1.
583 int Offset = MFI->getObjectOffset(FrameIndex);
586 Offset += MI.getOperand(OffIdx).getImmedValue();
588 Offset += MI.getOperand(OffIdx).getImmedValue() << 2;
590 // If we're not using a Frame Pointer that has been set to the value of the
591 // SP before having the stack size subtracted from it, then add the stack size
592 // to Offset to get the correct offset.
593 Offset += MFI->getStackSize();
595 if (!isInt16(Offset)) {
596 // Insert a set of r0 with the full offset value before the ld, st, or add
597 BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16);
598 BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset);
600 // convert into indexed form of the instruction
601 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
602 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
603 assert(ImmToIdxMap.count(OpC) &&
604 "No indexed form of load or store available!");
605 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
606 MI.setInstrDescriptor(TII.get(NewOpcode));
607 MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false);
608 MI.getOperand(2).ChangeToRegister(PPC::R0, false);
611 assert((Offset & 3) == 0 && "Invalid frame offset!");
612 Offset >>= 2; // The actual encoded value has the low two bits zero.
614 MI.getOperand(OffIdx).ChangeToImmediate(Offset);
618 /// VRRegNo - Map from a numbered VR register to its enum value.
620 static const unsigned short VRRegNo[] = {
621 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
622 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
623 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
624 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
627 /// RemoveVRSaveCode - We have found that this function does not need any code
628 /// to manipulate the VRSAVE register, even though it uses vector registers.
629 /// This can happen when the only registers used are known to be live in or out
630 /// of the function. Remove all of the VRSAVE related code from the function.
631 static void RemoveVRSaveCode(MachineInstr *MI) {
632 MachineBasicBlock *Entry = MI->getParent();
633 MachineFunction *MF = Entry->getParent();
635 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
636 MachineBasicBlock::iterator MBBI = MI;
638 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
639 MBBI->eraseFromParent();
641 bool RemovedAllMTVRSAVEs = true;
642 // See if we can find and remove the MTVRSAVE instruction from all of the
644 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
645 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
646 // If last instruction is a return instruction, add an epilogue
647 if (!I->empty() && TII.isReturn(I->back().getOpcode())) {
648 bool FoundIt = false;
649 for (MBBI = I->end(); MBBI != I->begin(); ) {
651 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
652 MBBI->eraseFromParent(); // remove it.
657 RemovedAllMTVRSAVEs &= FoundIt;
661 // If we found and removed all MTVRSAVE instructions, remove the read of
663 if (RemovedAllMTVRSAVEs) {
665 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
667 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
668 MBBI->eraseFromParent();
671 // Finally, nuke the UPDATE_VRSAVE.
672 MI->eraseFromParent();
675 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
676 // instruction selector. Based on the vector registers that have been used,
677 // transform this into the appropriate ORI instruction.
678 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs,
679 const TargetInstrInfo &TII) {
680 unsigned UsedRegMask = 0;
681 for (unsigned i = 0; i != 32; ++i)
682 if (UsedRegs[VRRegNo[i]])
683 UsedRegMask |= 1 << (31-i);
685 // Live in and live out values already must be in the mask, so don't bother
687 MachineFunction *MF = MI->getParent()->getParent();
688 for (MachineFunction::livein_iterator I =
689 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) {
690 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
691 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
692 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
694 for (MachineFunction::liveout_iterator I =
695 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) {
696 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
697 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
698 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
701 unsigned SrcReg = MI->getOperand(1).getReg();
702 unsigned DstReg = MI->getOperand(0).getReg();
703 // If no registers are used, turn this into a copy.
704 if (UsedRegMask == 0) {
705 // Remove all VRSAVE code.
706 RemoveVRSaveCode(MI);
708 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
709 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
710 .addReg(SrcReg).addImm(UsedRegMask);
711 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
712 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
713 .addReg(SrcReg).addImm(UsedRegMask >> 16);
715 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
716 .addReg(SrcReg).addImm(UsedRegMask >> 16);
717 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
718 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
721 // Remove the old UPDATE_VRSAVE instruction.
722 MI->eraseFromParent();
725 /// determineFrameLayout - Determine the size of the frame and maximum call
727 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
728 MachineFrameInfo *MFI = MF.getFrameInfo();
730 // Get the number of bytes to allocate from the FrameInfo
731 unsigned FrameSize = MFI->getStackSize();
733 // Get the alignments provided by the target, and the maximum alignment
734 // (if any) of the fixed frame objects.
735 unsigned MaxAlign = MFI->getMaxAlignment();
736 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
737 unsigned AlignMask = TargetAlign - 1; //
739 // If we are a leaf function, and use up to 224 bytes of stack space,
740 // don't have a frame pointer, calls, or dynamic alloca then we do not need
741 // to adjust the stack pointer (we fit in the Red Zone).
742 if (FrameSize <= 224 && // Fits in red zone.
743 !MFI->hasVarSizedObjects() && // No dynamic alloca.
744 !MFI->hasCalls() && // No calls.
745 MaxAlign <= TargetAlign) { // No special alignment.
747 MFI->setStackSize(0);
751 // Get the maximum call frame size of all the calls.
752 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
754 // Maximum call frame needs to be at least big enough for linkage and 8 args.
755 unsigned minCallFrameSize =
756 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64());
757 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
759 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
760 // that allocations will be aligned.
761 if (MFI->hasVarSizedObjects())
762 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
764 // Update maximum call frame size.
765 MFI->setMaxCallFrameSize(maxCallFrameSize);
767 // Include call frame size in total.
768 FrameSize += maxCallFrameSize;
770 // Make sure the frame is aligned.
771 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
773 // Update frame info.
774 MFI->setStackSize(FrameSize);
777 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
778 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
779 MachineBasicBlock::iterator MBBI = MBB.begin();
780 MachineFrameInfo *MFI = MF.getFrameInfo();
781 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
783 // Prepare for frame info.
784 unsigned FrameLabelId = 0;
786 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
788 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
789 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
790 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs(), TII);
795 // Move MBBI back to the beginning of the function.
798 // Work out frame sizes.
799 determineFrameLayout(MF);
800 unsigned FrameSize = MFI->getStackSize();
802 // Skip if a leaf routine.
803 if (!FrameSize) return;
805 int NegFrameSize = -FrameSize;
807 // Get processor type.
808 bool IsPPC64 = Subtarget.isPPC64();
809 // Check if the link register (LR) has been used.
810 bool UsesLR = MFI->hasCalls() || usesLR(MF);
811 // Do we have a frame pointer for this function?
812 bool HasFP = hasFP(MF);
814 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64);
815 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64);
819 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0);
822 BuildMI(MBB, MBBI, TII.get(PPC::STD))
823 .addReg(PPC::X31).addImm(FPOffset/4).addReg(PPC::X1);
826 BuildMI(MBB, MBBI, TII.get(PPC::STD))
827 .addReg(PPC::X0).addImm(LROffset/4).addReg(PPC::X1);
830 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0);
833 BuildMI(MBB, MBBI, TII.get(PPC::STW))
834 .addReg(PPC::R31).addImm(FPOffset).addReg(PPC::R1);
837 BuildMI(MBB, MBBI, TII.get(PPC::STW))
838 .addReg(PPC::R0).addImm(LROffset).addReg(PPC::R1);
841 // Get stack alignments.
842 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
843 unsigned MaxAlign = MFI->getMaxAlignment();
845 if (MMI && MMI->needsFrameInfo()) {
846 // Mark effective beginning of when frame pointer becomes valid.
847 FrameLabelId = MMI->NextLabelID();
848 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId);
851 // Adjust stack pointer: r1 += NegFrameSize.
852 // If there is a preferred stack alignment, align R1 now
855 if (MaxAlign > TargetAlign) {
856 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
857 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
858 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0)
859 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
860 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0)
861 .addImm(NegFrameSize);
862 BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
863 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
864 } else if (isInt16(NegFrameSize)) {
865 BuildMI(MBB, MBBI, TII.get(PPC::STWU),
866 PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1);
868 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0).addImm(NegFrameSize >> 16);
869 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0)
870 .addImm(NegFrameSize & 0xFFFF);
871 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1)
875 if (MaxAlign > TargetAlign) {
876 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
877 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
878 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0)
879 .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign));
880 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0).addReg(PPC::X0)
881 .addImm(NegFrameSize);
882 BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
883 .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0);
884 } else if (isInt16(NegFrameSize)) {
885 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1)
886 .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1);
888 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0).addImm(NegFrameSize >>16);
889 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0)
890 .addImm(NegFrameSize & 0xFFFF);
891 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1)
896 if (MMI && MMI->needsFrameInfo()) {
897 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
900 // Show update of SP.
901 MachineLocation SPDst(MachineLocation::VirtualFP);
902 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
903 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
905 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
906 Moves.push_back(MachineMove(FrameLabelId, SP, SP));
910 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
911 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
912 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
915 // Add callee saved registers to move list.
916 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
917 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
918 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
919 unsigned Reg = CSI[I].getReg();
920 if (Reg == PPC::LR || Reg == PPC::LR8) continue;
921 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
922 MachineLocation CSSrc(Reg);
923 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
926 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
927 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
928 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
930 // Mark effective beginning of when frame pointer is ready.
931 unsigned ReadyLabelId = MMI->NextLabelID();
932 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId);
934 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
935 (IsPPC64 ? PPC::X1 : PPC::R1));
936 MachineLocation FPSrc(MachineLocation::VirtualFP);
937 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
940 // If there is a frame pointer, copy R1 into R31
943 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1)
946 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1)
952 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
953 MachineBasicBlock &MBB) const {
954 MachineBasicBlock::iterator MBBI = prior(MBB.end());
955 assert(MBBI->getOpcode() == PPC::BLR &&
956 "Can only insert epilog into returning blocks");
958 // Get alignment info so we know how to restore r1
959 const MachineFrameInfo *MFI = MF.getFrameInfo();
960 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
961 unsigned MaxAlign = MFI->getMaxAlignment();
963 // Get the number of bytes allocated from the FrameInfo.
964 unsigned FrameSize = MFI->getStackSize();
966 if (!FrameSize) return;
968 // Get processor type.
969 bool IsPPC64 = Subtarget.isPPC64();
970 // Check if the link register (LR) has been used.
971 bool UsesLR = MFI->hasCalls() || usesLR(MF);
972 // Do we have a frame pointer for this function?
973 bool HasFP = hasFP(MF);
975 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
976 // on entry to the function. Add this offset back now.
977 if (!Subtarget.isPPC64()) {
978 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
979 !MFI->hasVarSizedObjects()) {
980 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
981 .addReg(PPC::R1).addImm(FrameSize);
983 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1);
986 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
987 !MFI->hasVarSizedObjects()) {
988 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
989 .addReg(PPC::X1).addImm(FrameSize);
991 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1);
995 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64);
996 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64);
1000 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0)
1001 .addImm(LROffset/4).addReg(PPC::X1);
1004 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31)
1005 .addImm(FPOffset/4).addReg(PPC::X1);
1008 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0);
1011 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0)
1012 .addImm(LROffset).addReg(PPC::R1);
1015 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31)
1016 .addImm(FPOffset).addReg(PPC::R1);
1019 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0);
1023 unsigned PPCRegisterInfo::getRARegister() const {
1024 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
1027 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1028 if (!Subtarget.isPPC64())
1029 return hasFP(MF) ? PPC::R31 : PPC::R1;
1031 return hasFP(MF) ? PPC::X31 : PPC::X1;
1034 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1036 // Initial state of the frame pointer is R1.
1037 MachineLocation Dst(MachineLocation::VirtualFP);
1038 MachineLocation Src(PPC::R1, 0);
1039 Moves.push_back(MachineMove(0, Dst, Src));
1042 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
1043 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
1046 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
1047 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
1050 #include "PPCGenRegisterInfo.inc"