1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "reginfo"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCRegisterInfo.h"
20 #include "PPCFrameInfo.h"
21 #include "PPCSubtarget.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Type.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/CodeGen/SelectionDAGNodes.h"
33 #include "llvm/Target/TargetFrameInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/ADT/BitVector.h"
41 #include "llvm/ADT/STLExtras.h"
45 // FIXME (64-bit): Eventually enable by default.
46 cl::opt<bool> EnablePPCRS("enable-ppc-regscavenger",
48 cl::desc("enable PPC register scavenger"),
51 // FIXME (64-bit): Should be inlined.
53 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const {
57 /// getRegisterNumbering - Given the enum value for some register, e.g.
58 /// PPC::F14, return the number that it corresponds to (e.g. 14).
59 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
63 case R0 : case X0 : case F0 : case V0 : case CR0: return 0;
64 case R1 : case X1 : case F1 : case V1 : case CR1: return 1;
65 case R2 : case X2 : case F2 : case V2 : case CR2: return 2;
66 case R3 : case X3 : case F3 : case V3 : case CR3: return 3;
67 case R4 : case X4 : case F4 : case V4 : case CR4: return 4;
68 case R5 : case X5 : case F5 : case V5 : case CR5: return 5;
69 case R6 : case X6 : case F6 : case V6 : case CR6: return 6;
70 case R7 : case X7 : case F7 : case V7 : case CR7: return 7;
71 case R8 : case X8 : case F8 : case V8 : return 8;
72 case R9 : case X9 : case F9 : case V9 : return 9;
73 case R10: case X10: case F10: case V10: return 10;
74 case R11: case X11: case F11: case V11: return 11;
75 case R12: case X12: case F12: case V12: return 12;
76 case R13: case X13: case F13: case V13: return 13;
77 case R14: case X14: case F14: case V14: return 14;
78 case R15: case X15: case F15: case V15: return 15;
79 case R16: case X16: case F16: case V16: return 16;
80 case R17: case X17: case F17: case V17: return 17;
81 case R18: case X18: case F18: case V18: return 18;
82 case R19: case X19: case F19: case V19: return 19;
83 case R20: case X20: case F20: case V20: return 20;
84 case R21: case X21: case F21: case V21: return 21;
85 case R22: case X22: case F22: case V22: return 22;
86 case R23: case X23: case F23: case V23: return 23;
87 case R24: case X24: case F24: case V24: return 24;
88 case R25: case X25: case F25: case V25: return 25;
89 case R26: case X26: case F26: case V26: return 26;
90 case R27: case X27: case F27: case V27: return 27;
91 case R28: case X28: case F28: case V28: return 28;
92 case R29: case X29: case F29: case V29: return 29;
93 case R30: case X30: case F30: case V30: return 30;
94 case R31: case X31: case F31: case V31: return 31;
96 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
101 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
102 const TargetInstrInfo &tii)
103 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
104 Subtarget(ST), TII(tii) {
105 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
106 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
107 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
108 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
109 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
110 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
111 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
112 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
115 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
116 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
117 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
118 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
119 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
122 void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
123 MachineBasicBlock::iterator I,
125 const MachineInstr *Orig) const {
126 MachineInstr *MI = Orig->clone();
127 MI->getOperand(0).setReg(DestReg);
132 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
133 // 32-bit Darwin calling convention.
134 static const unsigned Macho32_CalleeSavedRegs[] = {
135 PPC::R13, PPC::R14, PPC::R15,
136 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
137 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
138 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
139 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
141 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
142 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
143 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
144 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
147 PPC::CR2, PPC::CR3, PPC::CR4,
148 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
149 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
150 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
155 static const unsigned ELF32_CalleeSavedRegs[] = {
156 PPC::R13, PPC::R14, PPC::R15,
157 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
158 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
159 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
160 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
163 PPC::F10, PPC::F11, PPC::F12, PPC::F13,
164 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
165 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
166 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
167 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
170 PPC::CR2, PPC::CR3, PPC::CR4,
171 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
172 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
173 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
177 // 64-bit Darwin calling convention.
178 static const unsigned Macho64_CalleeSavedRegs[] = {
180 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
181 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
182 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
183 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
185 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
186 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
187 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
188 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
191 PPC::CR2, PPC::CR3, PPC::CR4,
192 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
193 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
194 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
199 if (Subtarget.isMachoABI())
200 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs :
201 Macho32_CalleeSavedRegs;
204 return ELF32_CalleeSavedRegs;
207 const TargetRegisterClass* const*
208 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
209 // 32-bit Macho calling convention.
210 static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = {
211 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
212 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
213 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
214 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
215 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
217 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
218 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
219 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
220 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
221 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
223 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
225 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
226 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
227 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
229 &PPC::GPRCRegClass, 0
232 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = {
233 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
234 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
235 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
236 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
237 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
240 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
241 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
242 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
243 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
244 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
245 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
247 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
249 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
250 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
251 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
253 &PPC::GPRCRegClass, 0
256 // 64-bit Macho calling convention.
257 static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = {
258 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
259 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
260 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
261 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
262 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
264 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
265 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
266 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
267 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
268 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
270 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
272 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
273 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
274 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
276 &PPC::G8RCRegClass, 0
279 if (Subtarget.isMachoABI())
280 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses :
281 Macho32_CalleeSavedRegClasses;
284 return ELF32_CalleeSavedRegClasses;
287 // needsFP - Return true if the specified function should have a dedicated frame
288 // pointer register. This is true if the function has variable sized allocas or
289 // if frame pointer elimination is disabled.
291 static bool needsFP(const MachineFunction &MF) {
292 const MachineFrameInfo *MFI = MF.getFrameInfo();
293 return NoFramePointerElim || MFI->hasVarSizedObjects();
296 static bool spillsCR(const MachineFunction &MF) {
297 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
298 return FuncInfo->isCRSpilled();
301 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
302 BitVector Reserved(getNumRegs());
303 Reserved.set(PPC::R0);
304 Reserved.set(PPC::R1);
305 Reserved.set(PPC::LR);
306 Reserved.set(PPC::LR8);
308 // In Linux, r2 is reserved for the OS.
309 if (!Subtarget.isDarwin())
310 Reserved.set(PPC::R2);
312 // On PPC64, r13 is the thread pointer. Never allocate this register. Note
313 // that this is over conservative, as it also prevents allocation of R31 when
314 // the FP is not needed.
315 if (Subtarget.isPPC64()) {
316 Reserved.set(PPC::R13);
317 Reserved.set(PPC::R31);
320 Reserved.set(PPC::R0); // FIXME (64-bit): Remove
322 Reserved.set(PPC::X0);
323 Reserved.set(PPC::X1);
324 Reserved.set(PPC::X13);
325 Reserved.set(PPC::X31);
329 Reserved.set(PPC::R31);
334 //===----------------------------------------------------------------------===//
335 // Stack Frame Processing methods
336 //===----------------------------------------------------------------------===//
338 // hasFP - Return true if the specified function actually has a dedicated frame
339 // pointer register. This is true if the function needs a frame pointer and has
340 // a non-zero stack size.
341 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
342 const MachineFrameInfo *MFI = MF.getFrameInfo();
343 return MFI->getStackSize() && needsFP(MF);
346 /// MustSaveLR - Return true if this function requires that we save the LR
347 /// register onto the stack in the prolog and restore it in the epilog of the
349 static bool MustSaveLR(const MachineFunction &MF) {
350 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
352 // We need an save/restore of LR if there is any use/def of LR explicitly, or
353 // if there is some use of the LR stack slot (e.g. for builtin_return_address.
354 return MFI->usesLR() || MFI->isLRStoreRequired() ||
355 // FIXME: Anything that has a call should clobber the LR register,
356 // isn't this redundant??
357 MF.getFrameInfo()->hasCalls();
360 void PPCRegisterInfo::
361 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
362 MachineBasicBlock::iterator I) const {
363 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
367 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered
368 /// register first and then a spilled callee-saved register if that fails.
370 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS,
371 const TargetRegisterClass *RC, int SPAdj) {
372 assert(RS && "Register scavenging must be on");
373 unsigned Reg = RS->FindUnusedReg(RC, true);
374 // FIXME: move ARM callee-saved reg scan to target independent code, then
375 // search for already spilled CS register here.
377 Reg = RS->scavengeRegister(RC, II, SPAdj);
381 /// lowerDynamicAlloc - Generate the code for allocating an object in the
382 /// current frame. The sequence of code with be in the general form
384 /// addi R0, SP, #frameSize ; get the address of the previous frame
385 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
386 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation
388 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
389 int SPAdj, RegScavenger *RS) const {
390 // Get the instruction.
391 MachineInstr &MI = *II;
392 // Get the instruction's basic block.
393 MachineBasicBlock &MBB = *MI.getParent();
394 // Get the basic block's function.
395 MachineFunction &MF = *MBB.getParent();
396 // Get the frame info.
397 MachineFrameInfo *MFI = MF.getFrameInfo();
398 // Determine whether 64-bit pointers are used.
399 bool LP64 = Subtarget.isPPC64();
401 // Get the maximum call stack size.
402 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
403 // Get the total frame size.
404 unsigned FrameSize = MFI->getStackSize();
406 // Get stack alignments.
407 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
408 unsigned MaxAlign = MFI->getMaxAlignment();
409 assert(MaxAlign <= TargetAlign &&
410 "Dynamic alloca with large aligns not supported");
412 // Determine the previous frame's address. If FrameSize can't be
413 // represented as 16 bits or we need special alignment, then we load the
414 // previous frame's address from 0(SP). Why not do an addis of the hi?
415 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
416 // Constructing the constant and adding would take 3 instructions.
417 // Fortunately, a frame greater than 32K is rare.
418 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
419 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
420 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC;
422 // FIXME (64-bit): Use "findScratchRegister"
425 Reg = findScratchRegister(II, RS, RC, SPAdj);
429 if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
430 BuildMI(MBB, II, TII.get(PPC::ADDI), Reg)
434 if (EnablePPCRS) // FIXME (64-bit): Use "true" version.
435 BuildMI(MBB, II, TII.get(PPC::LD), Reg)
439 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
443 BuildMI(MBB, II, TII.get(PPC::LWZ), Reg)
448 // Grow the stack and update the stack pointer link, then determine the
449 // address of new allocated space.
451 if (EnablePPCRS) // FIXME (64-bit): Use "true" version.
452 BuildMI(MBB, II, TII.get(PPC::STDUX))
453 .addReg(Reg, false, false, true)
455 .addReg(MI.getOperand(1).getReg());
457 BuildMI(MBB, II, TII.get(PPC::STDUX))
458 .addReg(PPC::X0, false, false, true)
460 .addReg(MI.getOperand(1).getReg());
462 if (!MI.getOperand(1).isKill())
463 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
465 .addImm(maxCallFrameSize);
467 // Implicitly kill the register.
468 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
470 .addImm(maxCallFrameSize)
471 .addReg(MI.getOperand(1).getReg(), false, true, true);
473 BuildMI(MBB, II, TII.get(PPC::STWUX))
474 .addReg(Reg, false, false, true)
476 .addReg(MI.getOperand(1).getReg());
478 if (!MI.getOperand(1).isKill())
479 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
481 .addImm(maxCallFrameSize);
483 // Implicitly kill the register.
484 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
486 .addImm(maxCallFrameSize)
487 .addReg(MI.getOperand(1).getReg(), false, true, true);
490 // Discard the DYNALLOC instruction.
494 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
495 /// reserving a whole register (R0), we scrounge for one here. This generates
498 /// mfcr rA ; Move the conditional register into GPR rA.
499 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
500 /// stw rA, FI ; Store rA to the frame.
502 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
503 unsigned FrameIndex, int SPAdj,
504 RegScavenger *RS) const {
505 // Get the instruction.
506 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI>
507 // Get the instruction's basic block.
508 MachineBasicBlock &MBB = *MI.getParent();
510 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
511 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
512 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
513 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
515 // We need to store the CR in the low 4-bits of the saved value. First, issue
516 // an MFCR to save all of the CRBits. Add an implicit kill of the CR.
517 if (!MI.getOperand(0).isKill())
518 BuildMI(MBB, II, TII.get(PPC::MFCR), Reg);
520 // Implicitly kill the CR register.
521 BuildMI(MBB, II, TII.get(PPC::MFCR), Reg)
522 .addReg(MI.getOperand(0).getReg(), false, true, true);
524 // If the saved register wasn't CR0, shift the bits left so that they are in
526 unsigned SrcReg = MI.getOperand(0).getReg();
527 if (SrcReg != PPC::CR0)
528 // rlwinm rA, rA, ShiftBits, 0, 31.
529 BuildMI(MBB, II, TII.get(PPC::RLWINM), Reg)
530 .addReg(Reg, false, false, true)
531 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4)
535 addFrameReference(BuildMI(MBB, II, TII.get(PPC::STW))
536 .addReg(Reg, false, false, MI.getOperand(1).getImm()),
539 // Discard the pseudo instruction.
543 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
544 int SPAdj, RegScavenger *RS) const {
545 assert(SPAdj == 0 && "Unexpected");
547 // Get the instruction.
548 MachineInstr &MI = *II;
549 // Get the instruction's basic block.
550 MachineBasicBlock &MBB = *MI.getParent();
551 // Get the basic block's function.
552 MachineFunction &MF = *MBB.getParent();
553 // Get the frame info.
554 MachineFrameInfo *MFI = MF.getFrameInfo();
556 // Find out which operand is the frame index.
557 unsigned FIOperandNo = 0;
558 while (!MI.getOperand(FIOperandNo).isFrameIndex()) {
560 assert(FIOperandNo != MI.getNumOperands() &&
561 "Instr doesn't have FrameIndex operand!");
563 // Take into account whether it's an add or mem instruction
564 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
565 if (MI.getOpcode() == TargetInstrInfo::INLINEASM)
566 OffsetOperandNo = FIOperandNo-1;
568 // Get the frame index.
569 int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
571 // Get the frame pointer save index. Users of this index are primarily
572 // DYNALLOC instructions.
573 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
574 int FPSI = FI->getFramePointerSaveIndex();
575 // Get the instruction opcode.
576 unsigned OpC = MI.getOpcode();
578 // Special case for dynamic alloca.
579 if (FPSI && FrameIndex == FPSI &&
580 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
581 lowerDynamicAlloc(II, SPAdj, RS);
585 // Special case for pseudo-op SPILL_CR.
586 if (EnablePPCRS) // FIXME (64-bit): Enable by default
587 if (OpC == PPC::SPILL_CR) {
588 lowerCRSpilling(II, FrameIndex, SPAdj, RS);
592 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
593 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1,
596 // Figure out if the offset in the instruction is shifted right two bits. This
597 // is true for instructions like "STD", which the machine implicitly adds two
599 bool isIXAddr = false;
609 // Now add the frame object offset to the offset from r1.
610 int Offset = MFI->getObjectOffset(FrameIndex);
612 Offset += MI.getOperand(OffsetOperandNo).getImm();
614 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
616 // If we're not using a Frame Pointer that has been set to the value of the
617 // SP before having the stack size subtracted from it, then add the stack size
618 // to Offset to get the correct offset.
619 Offset += MFI->getStackSize();
621 // If we can, encode the offset directly into the instruction. If this is a
622 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
623 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
624 // clear can be encoded. This is extremely uncommon, because normally you
625 // only "std" to a stack slot that is at least 4-byte aligned, but it can
626 // happen in invalid code.
627 if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
629 Offset >>= 2; // The actual encoded value has the low two bits zero.
630 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
634 // The offset doesn't fit into a single register, scavenge one to build the
636 // FIXME: figure out what SPAdj is doing here.
638 // FIXME (64-bit): Use "findScratchRegister".
641 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj);
645 // Insert a set of rA with the full offset value before the ld, st, or add
646 BuildMI(MBB, II, TII.get(PPC::LIS), SReg)
647 .addImm(Offset >> 16);
648 BuildMI(MBB, II, TII.get(PPC::ORI), SReg)
649 .addReg(SReg, false, false, true)
652 // Convert into indexed form of the instruction:
654 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
655 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
656 unsigned OperandBase;
658 if (OpC != TargetInstrInfo::INLINEASM) {
659 assert(ImmToIdxMap.count(OpC) &&
660 "No indexed form of load or store available!");
661 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
662 MI.setDesc(TII.get(NewOpcode));
665 OperandBase = OffsetOperandNo;
668 unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
669 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
670 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
673 /// VRRegNo - Map from a numbered VR register to its enum value.
675 static const unsigned short VRRegNo[] = {
676 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
677 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
678 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
679 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
682 /// RemoveVRSaveCode - We have found that this function does not need any code
683 /// to manipulate the VRSAVE register, even though it uses vector registers.
684 /// This can happen when the only registers used are known to be live in or out
685 /// of the function. Remove all of the VRSAVE related code from the function.
686 static void RemoveVRSaveCode(MachineInstr *MI) {
687 MachineBasicBlock *Entry = MI->getParent();
688 MachineFunction *MF = Entry->getParent();
690 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
691 MachineBasicBlock::iterator MBBI = MI;
693 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
694 MBBI->eraseFromParent();
696 bool RemovedAllMTVRSAVEs = true;
697 // See if we can find and remove the MTVRSAVE instruction from all of the
699 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
700 // If last instruction is a return instruction, add an epilogue
701 if (!I->empty() && I->back().getDesc().isReturn()) {
702 bool FoundIt = false;
703 for (MBBI = I->end(); MBBI != I->begin(); ) {
705 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
706 MBBI->eraseFromParent(); // remove it.
711 RemovedAllMTVRSAVEs &= FoundIt;
715 // If we found and removed all MTVRSAVE instructions, remove the read of
717 if (RemovedAllMTVRSAVEs) {
719 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
721 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
722 MBBI->eraseFromParent();
725 // Finally, nuke the UPDATE_VRSAVE.
726 MI->eraseFromParent();
729 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
730 // instruction selector. Based on the vector registers that have been used,
731 // transform this into the appropriate ORI instruction.
732 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
733 MachineFunction *MF = MI->getParent()->getParent();
735 unsigned UsedRegMask = 0;
736 for (unsigned i = 0; i != 32; ++i)
737 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
738 UsedRegMask |= 1 << (31-i);
740 // Live in and live out values already must be in the mask, so don't bother
742 for (MachineRegisterInfo::livein_iterator
743 I = MF->getRegInfo().livein_begin(),
744 E = MF->getRegInfo().livein_end(); I != E; ++I) {
745 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
746 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
747 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
749 for (MachineRegisterInfo::liveout_iterator
750 I = MF->getRegInfo().liveout_begin(),
751 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
752 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
753 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
754 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
757 // If no registers are used, turn this into a copy.
758 if (UsedRegMask == 0) {
759 // Remove all VRSAVE code.
760 RemoveVRSaveCode(MI);
764 unsigned SrcReg = MI->getOperand(1).getReg();
765 unsigned DstReg = MI->getOperand(0).getReg();
767 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
768 if (DstReg != SrcReg)
769 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
771 .addImm(UsedRegMask);
773 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
774 .addReg(SrcReg, false, false, true)
775 .addImm(UsedRegMask);
776 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
777 if (DstReg != SrcReg)
778 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
780 .addImm(UsedRegMask >> 16);
782 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
783 .addReg(SrcReg, false, false, true)
784 .addImm(UsedRegMask >> 16);
786 if (DstReg != SrcReg)
787 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
789 .addImm(UsedRegMask >> 16);
791 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
792 .addReg(SrcReg, false, false, true)
793 .addImm(UsedRegMask >> 16);
795 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
796 .addReg(DstReg, false, false, true)
797 .addImm(UsedRegMask & 0xFFFF);
800 // Remove the old UPDATE_VRSAVE instruction.
801 MI->eraseFromParent();
804 /// determineFrameLayout - Determine the size of the frame and maximum call
806 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
807 MachineFrameInfo *MFI = MF.getFrameInfo();
809 // Get the number of bytes to allocate from the FrameInfo
810 unsigned FrameSize = MFI->getStackSize();
812 // Get the alignments provided by the target, and the maximum alignment
813 // (if any) of the fixed frame objects.
814 unsigned MaxAlign = MFI->getMaxAlignment();
815 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
816 unsigned AlignMask = TargetAlign - 1; //
818 // If we are a leaf function, and use up to 224 bytes of stack space,
819 // don't have a frame pointer, calls, or dynamic alloca then we do not need
820 // to adjust the stack pointer (we fit in the Red Zone).
821 if (FrameSize <= 224 && // Fits in red zone.
822 !MFI->hasVarSizedObjects() && // No dynamic alloca.
823 !MFI->hasCalls() && // No calls.
824 MaxAlign <= TargetAlign) { // No special alignment.
826 MFI->setStackSize(0);
830 // Get the maximum call frame size of all the calls.
831 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
833 // Maximum call frame needs to be at least big enough for linkage and 8 args.
834 unsigned minCallFrameSize =
835 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
836 Subtarget.isMachoABI());
837 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
839 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
840 // that allocations will be aligned.
841 if (MFI->hasVarSizedObjects())
842 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
844 // Update maximum call frame size.
845 MFI->setMaxCallFrameSize(maxCallFrameSize);
847 // Include call frame size in total.
848 FrameSize += maxCallFrameSize;
850 // Make sure the frame is aligned.
851 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
853 // Update frame info.
854 MFI->setStackSize(FrameSize);
858 PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
859 RegScavenger *RS) const {
860 // Save and clear the LR state.
861 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
862 unsigned LR = getRARegister();
863 FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR));
864 MF.getRegInfo().setPhysRegUnused(LR);
866 // Save R31 if necessary
867 int FPSI = FI->getFramePointerSaveIndex();
868 bool IsPPC64 = Subtarget.isPPC64();
869 bool IsELF32_ABI = Subtarget.isELF32_ABI();
870 bool IsMachoABI = Subtarget.isMachoABI();
871 MachineFrameInfo *MFI = MF.getFrameInfo();
873 // If the frame pointer save index hasn't been defined yet.
874 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) &&
876 // Find out what the fix offset of the frame pointer save area.
877 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
879 // Allocate the frame index for frame pointer save area.
880 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
882 FI->setFramePointerSaveIndex(FPSI);
885 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
886 // a large stack, which will require scavenging a register to materialize a
888 // FIXME: this doesn't actually check stack size, so is a bit pessimistic
889 // FIXME: doesn't detect whether or not we need to spill vXX, which requires
892 if (EnablePPCRS) // FIXME (64-bit): Enable.
893 if (needsFP(MF) || spillsCR(MF)) {
894 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
895 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
896 const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC;
897 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
898 RC->getAlignment()));
903 PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
904 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
905 MachineBasicBlock::iterator MBBI = MBB.begin();
906 MachineFrameInfo *MFI = MF.getFrameInfo();
907 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
909 // Prepare for frame info.
910 unsigned FrameLabelId = 0;
912 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
914 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
915 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
916 HandleVRSaveUpdate(MBBI, TII);
921 // Move MBBI back to the beginning of the function.
924 // Work out frame sizes.
925 determineFrameLayout(MF);
926 unsigned FrameSize = MFI->getStackSize();
928 int NegFrameSize = -FrameSize;
930 // Get processor type.
931 bool IsPPC64 = Subtarget.isPPC64();
932 // Get operating system
933 bool IsMachoABI = Subtarget.isMachoABI();
934 // Check if the link register (LR) has been used.
935 bool UsesLR = MustSaveLR(MF);
936 // Do we have a frame pointer for this function?
937 bool HasFP = hasFP(MF) && FrameSize;
939 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
940 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
944 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0);
947 BuildMI(MBB, MBBI, TII.get(PPC::STD))
953 BuildMI(MBB, MBBI, TII.get(PPC::STD))
955 .addImm(LROffset / 4)
959 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0);
962 BuildMI(MBB, MBBI, TII.get(PPC::STW))
968 BuildMI(MBB, MBBI, TII.get(PPC::STW))
974 // Skip if a leaf routine.
975 if (!FrameSize) return;
977 // Get stack alignments.
978 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
979 unsigned MaxAlign = MFI->getMaxAlignment();
981 if (MMI && MMI->needsFrameInfo()) {
982 // Mark effective beginning of when frame pointer becomes valid.
983 FrameLabelId = MMI->NextLabelID();
984 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId).addImm(0);
987 // Adjust stack pointer: r1 += NegFrameSize.
988 // If there is a preferred stack alignment, align R1 now
991 if (MaxAlign > TargetAlign) {
992 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
993 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
995 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0)
998 .addImm(32 - Log2_32(MaxAlign))
1000 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0)
1001 .addReg(PPC::R0, false, false, true)
1002 .addImm(NegFrameSize);
1003 BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
1007 } else if (isInt16(NegFrameSize)) {
1008 BuildMI(MBB, MBBI, TII.get(PPC::STWU), PPC::R1)
1010 .addImm(NegFrameSize)
1013 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0)
1014 .addImm(NegFrameSize >> 16);
1015 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0)
1016 .addReg(PPC::R0, false, false, true)
1017 .addImm(NegFrameSize & 0xFFFF);
1018 BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
1024 if (MaxAlign > TargetAlign) {
1025 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1026 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1028 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0)
1031 .addImm(64 - Log2_32(MaxAlign));
1032 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0)
1034 .addImm(NegFrameSize);
1035 BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
1039 } else if (isInt16(NegFrameSize)) {
1040 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1)
1042 .addImm(NegFrameSize / 4)
1045 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0)
1046 .addImm(NegFrameSize >> 16);
1047 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0)
1048 .addReg(PPC::X0, false, false, true)
1049 .addImm(NegFrameSize & 0xFFFF);
1050 BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
1057 if (MMI && MMI->needsFrameInfo()) {
1058 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
1061 // Show update of SP.
1062 MachineLocation SPDst(MachineLocation::VirtualFP);
1063 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
1064 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1066 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
1067 Moves.push_back(MachineMove(FrameLabelId, SP, SP));
1071 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
1072 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
1073 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
1076 // Add callee saved registers to move list.
1077 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1078 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1079 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1080 unsigned Reg = CSI[I].getReg();
1081 if (Reg == PPC::LR || Reg == PPC::LR8) continue;
1082 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1083 MachineLocation CSSrc(Reg);
1084 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
1087 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
1088 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
1089 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
1091 // Mark effective beginning of when frame pointer is ready.
1092 unsigned ReadyLabelId = MMI->NextLabelID();
1093 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId).addImm(0);
1095 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
1096 (IsPPC64 ? PPC::X1 : PPC::R1));
1097 MachineLocation FPSrc(MachineLocation::VirtualFP);
1098 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1101 // If there is a frame pointer, copy R1 into R31
1104 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31)
1108 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31)
1115 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
1116 MachineBasicBlock &MBB) const {
1117 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1118 assert(MBBI->getOpcode() == PPC::BLR &&
1119 "Can only insert epilog into returning blocks");
1121 // Get alignment info so we know how to restore r1
1122 const MachineFrameInfo *MFI = MF.getFrameInfo();
1123 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1124 unsigned MaxAlign = MFI->getMaxAlignment();
1126 // Get the number of bytes allocated from the FrameInfo.
1127 unsigned FrameSize = MFI->getStackSize();
1129 // Get processor type.
1130 bool IsPPC64 = Subtarget.isPPC64();
1131 // Get operating system
1132 bool IsMachoABI = Subtarget.isMachoABI();
1133 // Check if the link register (LR) has been used.
1134 bool UsesLR = MustSaveLR(MF);
1135 // Do we have a frame pointer for this function?
1136 bool HasFP = hasFP(MF) && FrameSize;
1138 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
1139 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
1142 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
1143 // on entry to the function. Add this offset back now.
1144 if (!Subtarget.isPPC64()) {
1145 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1146 !MFI->hasVarSizedObjects()) {
1147 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
1148 .addReg(PPC::R1).addImm(FrameSize);
1150 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1);
1153 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1154 !MFI->hasVarSizedObjects()) {
1155 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
1156 .addReg(PPC::X1).addImm(FrameSize);
1158 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1);
1165 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0)
1166 .addImm(LROffset/4).addReg(PPC::X1);
1169 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31)
1170 .addImm(FPOffset/4).addReg(PPC::X1);
1173 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0);
1176 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0)
1177 .addImm(LROffset).addReg(PPC::R1);
1180 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31)
1181 .addImm(FPOffset).addReg(PPC::R1);
1184 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0);
1188 unsigned PPCRegisterInfo::getRARegister() const {
1189 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
1192 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1193 if (!Subtarget.isPPC64())
1194 return hasFP(MF) ? PPC::R31 : PPC::R1;
1196 return hasFP(MF) ? PPC::X31 : PPC::X1;
1199 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1201 // Initial state of the frame pointer is R1.
1202 MachineLocation Dst(MachineLocation::VirtualFP);
1203 MachineLocation Src(PPC::R1, 0);
1204 Moves.push_back(MachineMove(0, Dst, Src));
1207 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
1208 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
1211 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
1212 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
1215 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1216 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
1217 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1220 #include "PPCGenRegisterInfo.inc"