1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PPCInstrBuilder.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCRegisterInfo.h"
19 #include "PPCFrameInfo.h"
20 #include "PPCSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Type.h"
23 #include "llvm/CodeGen/ValueTypes.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineLocation.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/Target/TargetFrameInfo.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
42 /// getRegisterNumbering - Given the enum value for some register, e.g.
43 /// PPC::F14, return the number that it corresponds to (e.g. 14).
44 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
47 case R0 : case X0 : case F0 : case V0 : case CR0: return 0;
48 case R1 : case X1 : case F1 : case V1 : case CR1: return 1;
49 case R2 : case X2 : case F2 : case V2 : case CR2: return 2;
50 case R3 : case X3 : case F3 : case V3 : case CR3: return 3;
51 case R4 : case X4 : case F4 : case V4 : case CR4: return 4;
52 case R5 : case X5 : case F5 : case V5 : case CR5: return 5;
53 case R6 : case X6 : case F6 : case V6 : case CR6: return 6;
54 case R7 : case X7 : case F7 : case V7 : case CR7: return 7;
55 case R8 : case X8 : case F8 : case V8 : return 8;
56 case R9 : case X9 : case F9 : case V9 : return 9;
57 case R10: case X10: case F10: case V10: return 10;
58 case R11: case X11: case F11: case V11: return 11;
59 case R12: case X12: case F12: case V12: return 12;
60 case R13: case X13: case F13: case V13: return 13;
61 case R14: case X14: case F14: case V14: return 14;
62 case R15: case X15: case F15: case V15: return 15;
63 case R16: case X16: case F16: case V16: return 16;
64 case R17: case X17: case F17: case V17: return 17;
65 case R18: case X18: case F18: case V18: return 18;
66 case R19: case X19: case F19: case V19: return 19;
67 case R20: case X20: case F20: case V20: return 20;
68 case R21: case X21: case F21: case V21: return 21;
69 case R22: case X22: case F22: case V22: return 22;
70 case R23: case X23: case F23: case V23: return 23;
71 case R24: case X24: case F24: case V24: return 24;
72 case R25: case X25: case F25: case V25: return 25;
73 case R26: case X26: case F26: case V26: return 26;
74 case R27: case X27: case F27: case V27: return 27;
75 case R28: case X28: case F28: case V28: return 28;
76 case R29: case X29: case F29: case V29: return 29;
77 case R30: case X30: case F30: case V30: return 30;
78 case R31: case X31: case F31: case V31: return 31;
80 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
85 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
86 const TargetInstrInfo &tii)
87 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
88 Subtarget(ST), TII(tii) {
89 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
90 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
91 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
92 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
93 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
94 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
95 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
96 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
97 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
101 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
102 MachineBasicBlock::iterator MI,
103 unsigned SrcReg, int FrameIdx,
104 const TargetRegisterClass *RC) const {
105 if (RC == PPC::GPRCRegisterClass) {
106 if (SrcReg != PPC::LR) {
107 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW))
108 .addReg(SrcReg, false, false, true), FrameIdx);
110 // FIXME: this spills LR immediately to memory in one step. To do this,
111 // we use R11, which we know cannot be used in the prolog/epilog. This is
113 BuildMI(MBB, MI, TII.get(PPC::MFLR), PPC::R11);
114 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW))
115 .addReg(PPC::R11, false, false, true), FrameIdx);
117 } else if (RC == PPC::G8RCRegisterClass) {
118 if (SrcReg != PPC::LR8) {
119 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD))
120 .addReg(SrcReg, false, false, true), FrameIdx);
122 // FIXME: this spills LR immediately to memory in one step. To do this,
123 // we use R11, which we know cannot be used in the prolog/epilog. This is
125 BuildMI(MBB, MI, TII.get(PPC::MFLR8), PPC::X11);
126 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD))
127 .addReg(PPC::X11, false, false, true), FrameIdx);
129 } else if (RC == PPC::F8RCRegisterClass) {
130 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD))
131 .addReg(SrcReg, false, false, true), FrameIdx);
132 } else if (RC == PPC::F4RCRegisterClass) {
133 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS))
134 .addReg(SrcReg, false, false, true), FrameIdx);
135 } else if (RC == PPC::CRRCRegisterClass) {
136 // FIXME: We use R0 here, because it isn't available for RA.
137 // We need to store the CR in the low 4-bits of the saved value. First,
138 // issue a MFCR to save all of the CRBits.
139 BuildMI(MBB, MI, TII.get(PPC::MFCR), PPC::R0);
141 // If the saved register wasn't CR0, shift the bits left so that they are in
143 if (SrcReg != PPC::CR0) {
144 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
145 // rlwinm r0, r0, ShiftBits, 0, 31.
146 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0)
147 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31);
150 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW))
151 .addReg(PPC::R0, false, false, true), FrameIdx);
152 } else if (RC == PPC::VRRCRegisterClass) {
153 // We don't have indexed addressing for vector loads. Emit:
155 // Dest = LVX R0, R11
157 // FIXME: We use R0 here, because it isn't available for RA.
158 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
160 BuildMI(MBB, MI, TII.get(PPC::STVX))
161 .addReg(SrcReg, false, false, true).addReg(PPC::R0).addReg(PPC::R0);
163 assert(0 && "Unknown regclass!");
169 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
170 MachineBasicBlock::iterator MI,
171 unsigned DestReg, int FrameIdx,
172 const TargetRegisterClass *RC) const {
173 if (RC == PPC::GPRCRegisterClass) {
174 if (DestReg != PPC::LR) {
175 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), DestReg), FrameIdx);
177 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R11),FrameIdx);
178 BuildMI(MBB, MI, TII.get(PPC::MTLR)).addReg(PPC::R11);
180 } else if (RC == PPC::G8RCRegisterClass) {
181 if (DestReg != PPC::LR8) {
182 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), DestReg), FrameIdx);
184 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), PPC::R11), FrameIdx);
185 BuildMI(MBB, MI, TII.get(PPC::MTLR8)).addReg(PPC::R11);
187 } else if (RC == PPC::F8RCRegisterClass) {
188 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFD), DestReg), FrameIdx);
189 } else if (RC == PPC::F4RCRegisterClass) {
190 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFS), DestReg), FrameIdx);
191 } else if (RC == PPC::CRRCRegisterClass) {
192 // FIXME: We use R0 here, because it isn't available for RA.
193 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R0), FrameIdx);
195 // If the reloaded register isn't CR0, shift the bits right so that they are
196 // in the right CR's slot.
197 if (DestReg != PPC::CR0) {
198 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
199 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
200 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0)
201 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31);
204 BuildMI(MBB, MI, TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0);
205 } else if (RC == PPC::VRRCRegisterClass) {
206 // We don't have indexed addressing for vector loads. Emit:
208 // Dest = LVX R0, R11
210 // FIXME: We use R0 here, because it isn't available for RA.
211 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
213 BuildMI(MBB, MI, TII.get(PPC::LVX),DestReg).addReg(PPC::R0).addReg(PPC::R0);
215 assert(0 && "Unknown regclass!");
220 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
221 MachineBasicBlock::iterator MI,
222 unsigned DestReg, unsigned SrcReg,
223 const TargetRegisterClass *RC) const {
224 if (RC == PPC::GPRCRegisterClass) {
225 BuildMI(MBB, MI, TII.get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
226 } else if (RC == PPC::G8RCRegisterClass) {
227 BuildMI(MBB, MI, TII.get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
228 } else if (RC == PPC::F4RCRegisterClass) {
229 BuildMI(MBB, MI, TII.get(PPC::FMRS), DestReg).addReg(SrcReg);
230 } else if (RC == PPC::F8RCRegisterClass) {
231 BuildMI(MBB, MI, TII.get(PPC::FMRD), DestReg).addReg(SrcReg);
232 } else if (RC == PPC::CRRCRegisterClass) {
233 BuildMI(MBB, MI, TII.get(PPC::MCRF), DestReg).addReg(SrcReg);
234 } else if (RC == PPC::VRRCRegisterClass) {
235 BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
237 cerr << "Attempt to copy register that is not GPR or FPR";
242 void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
243 MachineBasicBlock::iterator I,
245 const MachineInstr *Orig) const {
246 MachineInstr *MI = Orig->clone();
247 MI->getOperand(0).setReg(DestReg);
251 const unsigned* PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
253 // 32-bit Darwin calling convention.
254 static const unsigned Macho32_CalleeSavedRegs[] = {
255 PPC::R13, PPC::R14, PPC::R15,
256 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
257 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
258 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
259 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
261 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
262 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
263 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
264 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
267 PPC::CR2, PPC::CR3, PPC::CR4,
268 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
269 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
270 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
275 static const unsigned ELF32_CalleeSavedRegs[] = {
276 PPC::R13, PPC::R14, PPC::R15,
277 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
278 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
279 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
280 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
283 PPC::F10, PPC::F11, PPC::F12, PPC::F13,
284 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
285 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
286 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
287 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
290 PPC::CR2, PPC::CR3, PPC::CR4,
291 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
292 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
293 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
297 // 64-bit Darwin calling convention.
298 static const unsigned Macho64_CalleeSavedRegs[] = {
300 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
301 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
302 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
303 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
305 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
306 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
307 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
308 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
311 PPC::CR2, PPC::CR3, PPC::CR4,
312 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
313 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
314 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
319 if (Subtarget.isMachoABI())
320 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs :
321 Macho32_CalleeSavedRegs;
324 return ELF32_CalleeSavedRegs;
327 const TargetRegisterClass* const*
328 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
329 // 32-bit Macho calling convention.
330 static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = {
331 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
332 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
333 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
334 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
335 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
337 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
338 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
339 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
340 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
341 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
343 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
345 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
346 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
347 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
349 &PPC::GPRCRegClass, 0
352 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = {
353 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
354 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
355 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
356 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
357 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
360 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
361 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
362 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
363 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
364 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
365 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
367 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
369 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
370 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
371 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
373 &PPC::GPRCRegClass, 0
376 // 64-bit Macho calling convention.
377 static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = {
378 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
379 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
380 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
381 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
382 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
384 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
385 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
386 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
387 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
388 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
390 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
392 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
393 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
394 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
396 &PPC::G8RCRegClass, 0
399 if (Subtarget.isMachoABI())
400 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses :
401 Macho32_CalleeSavedRegClasses;
404 return ELF32_CalleeSavedRegClasses;
407 // needsFP - Return true if the specified function should have a dedicated frame
408 // pointer register. This is true if the function has variable sized allocas or
409 // if frame pointer elimination is disabled.
411 static bool needsFP(const MachineFunction &MF) {
412 const MachineFrameInfo *MFI = MF.getFrameInfo();
413 return NoFramePointerElim || MFI->hasVarSizedObjects();
416 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
417 BitVector Reserved(getNumRegs());
418 Reserved.set(PPC::R0);
419 Reserved.set(PPC::R1);
420 Reserved.set(PPC::LR);
421 // In Linux, r2 is reserved for the OS.
422 if (!Subtarget.isDarwin())
423 Reserved.set(PPC::R2);
424 // On PPC64, r13 is the thread pointer. Never allocate this register.
425 // Note that this is overconservative, as it also prevents allocation of
426 // R31 when the FP is not needed.
427 if (Subtarget.isPPC64()) {
428 Reserved.set(PPC::R13);
429 Reserved.set(PPC::R31);
432 Reserved.set(PPC::R31);
436 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
437 /// copy instructions, turning them into load/store instructions.
438 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
440 int FrameIndex) const {
441 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
442 // it takes more than one instruction to store it.
443 unsigned Opc = MI->getOpcode();
445 MachineInstr *NewMI = NULL;
446 if ((Opc == PPC::OR &&
447 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
448 if (OpNum == 0) { // move -> store
449 unsigned InReg = MI->getOperand(1).getReg();
450 NewMI = addFrameReference(BuildMI(TII.get(PPC::STW)).addReg(InReg),
452 } else { // move -> load
453 unsigned OutReg = MI->getOperand(0).getReg();
454 NewMI = addFrameReference(BuildMI(TII.get(PPC::LWZ), OutReg),
457 } else if ((Opc == PPC::OR8 &&
458 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
459 if (OpNum == 0) { // move -> store
460 unsigned InReg = MI->getOperand(1).getReg();
461 NewMI = addFrameReference(BuildMI(TII.get(PPC::STD)).addReg(InReg),
463 } else { // move -> load
464 unsigned OutReg = MI->getOperand(0).getReg();
465 NewMI = addFrameReference(BuildMI(TII.get(PPC::LD), OutReg), FrameIndex);
467 } else if (Opc == PPC::FMRD) {
468 if (OpNum == 0) { // move -> store
469 unsigned InReg = MI->getOperand(1).getReg();
470 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFD)).addReg(InReg),
472 } else { // move -> load
473 unsigned OutReg = MI->getOperand(0).getReg();
474 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFD), OutReg), FrameIndex);
476 } else if (Opc == PPC::FMRS) {
477 if (OpNum == 0) { // move -> store
478 unsigned InReg = MI->getOperand(1).getReg();
479 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFS)).addReg(InReg),
481 } else { // move -> load
482 unsigned OutReg = MI->getOperand(0).getReg();
483 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFS), OutReg), FrameIndex);
488 NewMI->copyKillDeadInfo(MI);
492 //===----------------------------------------------------------------------===//
493 // Stack Frame Processing methods
494 //===----------------------------------------------------------------------===//
496 // hasFP - Return true if the specified function actually has a dedicated frame
497 // pointer register. This is true if the function needs a frame pointer and has
498 // a non-zero stack size.
499 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
500 const MachineFrameInfo *MFI = MF.getFrameInfo();
501 return MFI->getStackSize() && needsFP(MF);
504 /// usesLR - Returns if the link registers (LR) has been used in the function.
506 bool PPCRegisterInfo::usesLR(MachineFunction &MF) const {
507 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
511 void PPCRegisterInfo::
512 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
513 MachineBasicBlock::iterator I) const {
514 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
518 /// LowerDynamicAlloc - Generate the code for allocating an object in the
519 /// current frame. The sequence of code with be in the general form
521 /// addi R0, SP, #frameSize ; get the address of the previous frame
522 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
523 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation
525 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
526 // Get the instruction.
527 MachineInstr &MI = *II;
528 // Get the instruction's basic block.
529 MachineBasicBlock &MBB = *MI.getParent();
530 // Get the basic block's function.
531 MachineFunction &MF = *MBB.getParent();
532 // Get the frame info.
533 MachineFrameInfo *MFI = MF.getFrameInfo();
534 // Determine whether 64-bit pointers are used.
535 bool LP64 = Subtarget.isPPC64();
537 // Get the maximum call stack size.
538 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
539 // Get the total frame size.
540 unsigned FrameSize = MFI->getStackSize();
542 // Get stack alignments.
543 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
544 unsigned MaxAlign = MFI->getMaxAlignment();
545 assert(MaxAlign <= TargetAlign &&
546 "Dynamic alloca with large aligns not supported");
548 // Determine the previous frame's address. If FrameSize can't be
549 // represented as 16 bits or we need special alignment, then we load the
550 // previous frame's address from 0(SP). Why not do an addis of the hi?
551 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
552 // Constructing the constant and adding would take 3 instructions.
553 // Fortunately, a frame greater than 32K is rare.
554 if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
555 BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0)
559 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
563 BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0)
568 // Grow the stack and update the stack pointer link, then
569 // determine the address of new allocated space.
571 BuildMI(MBB, II, TII.get(PPC::STDUX))
574 .addReg(MI.getOperand(1).getReg());
575 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
577 .addImm(maxCallFrameSize);
579 BuildMI(MBB, II, TII.get(PPC::STWUX))
582 .addReg(MI.getOperand(1).getReg());
583 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
585 .addImm(maxCallFrameSize);
588 // Discard the DYNALLOC instruction.
592 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
593 int SPAdj, RegScavenger *RS) const {
594 assert(SPAdj == 0 && "Unexpected");
596 // Get the instruction.
597 MachineInstr &MI = *II;
598 // Get the instruction's basic block.
599 MachineBasicBlock &MBB = *MI.getParent();
600 // Get the basic block's function.
601 MachineFunction &MF = *MBB.getParent();
602 // Get the frame info.
603 MachineFrameInfo *MFI = MF.getFrameInfo();
605 // Find out which operand is the frame index.
607 while (!MI.getOperand(i).isFrameIndex()) {
609 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
611 // Take into account whether it's an add or mem instruction
612 unsigned OffIdx = (i == 2) ? 1 : 2;
613 if (MI.getOpcode() == TargetInstrInfo::INLINEASM)
616 // Get the frame index.
617 int FrameIndex = MI.getOperand(i).getFrameIndex();
619 // Get the frame pointer save index. Users of this index are primarily
620 // DYNALLOC instructions.
621 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
622 int FPSI = FI->getFramePointerSaveIndex();
623 // Get the instruction opcode.
624 unsigned OpC = MI.getOpcode();
626 // Special case for dynamic alloca.
627 if (FPSI && FrameIndex == FPSI &&
628 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
629 lowerDynamicAlloc(II);
633 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
634 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, false);
636 // Figure out if the offset in the instruction is shifted right two bits. This
637 // is true for instructions like "STD", which the machine implicitly adds two
639 bool isIXAddr = false;
649 // Now add the frame object offset to the offset from r1.
650 int Offset = MFI->getObjectOffset(FrameIndex);
653 Offset += MI.getOperand(OffIdx).getImmedValue();
655 Offset += MI.getOperand(OffIdx).getImmedValue() << 2;
657 // If we're not using a Frame Pointer that has been set to the value of the
658 // SP before having the stack size subtracted from it, then add the stack size
659 // to Offset to get the correct offset.
660 Offset += MFI->getStackSize();
662 if (!isInt16(Offset)) {
663 // Insert a set of r0 with the full offset value before the ld, st, or add
664 BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16);
665 BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset);
667 // convert into indexed form of the instruction
668 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
669 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
670 assert(ImmToIdxMap.count(OpC) &&
671 "No indexed form of load or store available!");
672 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
673 MI.setInstrDescriptor(TII.get(NewOpcode));
674 MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false);
675 MI.getOperand(2).ChangeToRegister(PPC::R0, false);
678 assert((Offset & 3) == 0 && "Invalid frame offset!");
679 Offset >>= 2; // The actual encoded value has the low two bits zero.
681 MI.getOperand(OffIdx).ChangeToImmediate(Offset);
685 /// VRRegNo - Map from a numbered VR register to its enum value.
687 static const unsigned short VRRegNo[] = {
688 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
689 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
690 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
691 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
694 /// RemoveVRSaveCode - We have found that this function does not need any code
695 /// to manipulate the VRSAVE register, even though it uses vector registers.
696 /// This can happen when the only registers used are known to be live in or out
697 /// of the function. Remove all of the VRSAVE related code from the function.
698 static void RemoveVRSaveCode(MachineInstr *MI) {
699 MachineBasicBlock *Entry = MI->getParent();
700 MachineFunction *MF = Entry->getParent();
702 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
703 MachineBasicBlock::iterator MBBI = MI;
705 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
706 MBBI->eraseFromParent();
708 bool RemovedAllMTVRSAVEs = true;
709 // See if we can find and remove the MTVRSAVE instruction from all of the
711 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
712 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
713 // If last instruction is a return instruction, add an epilogue
714 if (!I->empty() && TII.isReturn(I->back().getOpcode())) {
715 bool FoundIt = false;
716 for (MBBI = I->end(); MBBI != I->begin(); ) {
718 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
719 MBBI->eraseFromParent(); // remove it.
724 RemovedAllMTVRSAVEs &= FoundIt;
728 // If we found and removed all MTVRSAVE instructions, remove the read of
730 if (RemovedAllMTVRSAVEs) {
732 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
734 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
735 MBBI->eraseFromParent();
738 // Finally, nuke the UPDATE_VRSAVE.
739 MI->eraseFromParent();
742 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
743 // instruction selector. Based on the vector registers that have been used,
744 // transform this into the appropriate ORI instruction.
745 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
746 MachineFunction *MF = MI->getParent()->getParent();
748 unsigned UsedRegMask = 0;
749 for (unsigned i = 0; i != 32; ++i)
750 if (MF->isPhysRegUsed(VRRegNo[i]))
751 UsedRegMask |= 1 << (31-i);
753 // Live in and live out values already must be in the mask, so don't bother
755 for (MachineFunction::livein_iterator I =
756 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) {
757 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
758 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
759 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
761 for (MachineFunction::liveout_iterator I =
762 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) {
763 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
764 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
765 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
768 unsigned SrcReg = MI->getOperand(1).getReg();
769 unsigned DstReg = MI->getOperand(0).getReg();
770 // If no registers are used, turn this into a copy.
771 if (UsedRegMask == 0) {
772 // Remove all VRSAVE code.
773 RemoveVRSaveCode(MI);
775 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
776 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
777 .addReg(SrcReg).addImm(UsedRegMask);
778 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
779 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
780 .addReg(SrcReg).addImm(UsedRegMask >> 16);
782 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
783 .addReg(SrcReg).addImm(UsedRegMask >> 16);
784 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
785 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
788 // Remove the old UPDATE_VRSAVE instruction.
789 MI->eraseFromParent();
792 /// determineFrameLayout - Determine the size of the frame and maximum call
794 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
795 MachineFrameInfo *MFI = MF.getFrameInfo();
797 // Get the number of bytes to allocate from the FrameInfo
798 unsigned FrameSize = MFI->getStackSize();
800 // Get the alignments provided by the target, and the maximum alignment
801 // (if any) of the fixed frame objects.
802 unsigned MaxAlign = MFI->getMaxAlignment();
803 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
804 unsigned AlignMask = TargetAlign - 1; //
806 // If we are a leaf function, and use up to 224 bytes of stack space,
807 // don't have a frame pointer, calls, or dynamic alloca then we do not need
808 // to adjust the stack pointer (we fit in the Red Zone).
809 if (FrameSize <= 224 && // Fits in red zone.
810 !MFI->hasVarSizedObjects() && // No dynamic alloca.
811 !MFI->hasCalls() && // No calls.
812 MaxAlign <= TargetAlign) { // No special alignment.
814 MFI->setStackSize(0);
818 // Get the maximum call frame size of all the calls.
819 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
821 // Maximum call frame needs to be at least big enough for linkage and 8 args.
822 unsigned minCallFrameSize =
823 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
824 Subtarget.isMachoABI());
825 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
827 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
828 // that allocations will be aligned.
829 if (MFI->hasVarSizedObjects())
830 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
832 // Update maximum call frame size.
833 MFI->setMaxCallFrameSize(maxCallFrameSize);
835 // Include call frame size in total.
836 FrameSize += maxCallFrameSize;
838 // Make sure the frame is aligned.
839 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
841 // Update frame info.
842 MFI->setStackSize(FrameSize);
845 void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
848 // Save and clear the LR state.
849 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
850 unsigned LR = getRARegister();
851 FI->setUsesLR(MF.isPhysRegUsed(LR));
852 MF.setPhysRegUnused(LR);
854 // Save R31 if necessary
855 int FPSI = FI->getFramePointerSaveIndex();
856 bool IsPPC64 = Subtarget.isPPC64();
857 bool IsELF32_ABI = Subtarget.isELF32_ABI();
858 bool IsMachoABI = Subtarget.isMachoABI();
859 const MachineFrameInfo *MFI = MF.getFrameInfo();
861 // If the frame pointer save index hasn't been defined yet.
862 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects())
864 // Find out what the fix offset of the frame pointer save area.
865 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
867 // Allocate the frame index for frame pointer save area.
868 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
870 FI->setFramePointerSaveIndex(FPSI);
875 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
876 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
877 MachineBasicBlock::iterator MBBI = MBB.begin();
878 MachineFrameInfo *MFI = MF.getFrameInfo();
879 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
881 // Prepare for frame info.
882 unsigned FrameLabelId = 0;
884 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
886 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
887 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
888 HandleVRSaveUpdate(MBBI, TII);
893 // Move MBBI back to the beginning of the function.
896 // Work out frame sizes.
897 determineFrameLayout(MF);
898 unsigned FrameSize = MFI->getStackSize();
900 int NegFrameSize = -FrameSize;
902 // Get processor type.
903 bool IsPPC64 = Subtarget.isPPC64();
904 // Get operating system
905 bool IsMachoABI = Subtarget.isMachoABI();
906 // Check if the link register (LR) has been used.
907 bool UsesLR = MFI->hasCalls() || usesLR(MF);
908 // Do we have a frame pointer for this function?
909 bool HasFP = hasFP(MF) && FrameSize;
911 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
912 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
916 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0);
919 BuildMI(MBB, MBBI, TII.get(PPC::STD))
920 .addReg(PPC::X31).addImm(FPOffset/4).addReg(PPC::X1);
923 BuildMI(MBB, MBBI, TII.get(PPC::STD))
924 .addReg(PPC::X0).addImm(LROffset/4).addReg(PPC::X1);
927 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0);
930 BuildMI(MBB, MBBI, TII.get(PPC::STW))
931 .addReg(PPC::R31).addImm(FPOffset).addReg(PPC::R1);
934 BuildMI(MBB, MBBI, TII.get(PPC::STW))
935 .addReg(PPC::R0).addImm(LROffset).addReg(PPC::R1);
938 // Skip if a leaf routine.
939 if (!FrameSize) return;
941 // Get stack alignments.
942 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
943 unsigned MaxAlign = MFI->getMaxAlignment();
945 if (MMI && MMI->needsFrameInfo()) {
946 // Mark effective beginning of when frame pointer becomes valid.
947 FrameLabelId = MMI->NextLabelID();
948 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId);
951 // Adjust stack pointer: r1 += NegFrameSize.
952 // If there is a preferred stack alignment, align R1 now
955 if (MaxAlign > TargetAlign) {
956 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
957 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
958 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0)
959 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
960 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0)
961 .addImm(NegFrameSize);
962 BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
963 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
964 } else if (isInt16(NegFrameSize)) {
965 BuildMI(MBB, MBBI, TII.get(PPC::STWU),
966 PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1);
968 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0).addImm(NegFrameSize >> 16);
969 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0)
970 .addImm(NegFrameSize & 0xFFFF);
971 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1)
975 if (MaxAlign > TargetAlign) {
976 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
977 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
978 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0)
979 .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign));
980 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0).addReg(PPC::X0)
981 .addImm(NegFrameSize);
982 BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
983 .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0);
984 } else if (isInt16(NegFrameSize)) {
985 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1)
986 .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1);
988 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0).addImm(NegFrameSize >>16);
989 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0)
990 .addImm(NegFrameSize & 0xFFFF);
991 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1)
996 if (MMI && MMI->needsFrameInfo()) {
997 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
1000 // Show update of SP.
1001 MachineLocation SPDst(MachineLocation::VirtualFP);
1002 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
1003 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1005 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
1006 Moves.push_back(MachineMove(FrameLabelId, SP, SP));
1010 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
1011 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
1012 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
1015 // Add callee saved registers to move list.
1016 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1017 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1018 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1019 unsigned Reg = CSI[I].getReg();
1020 if (Reg == PPC::LR || Reg == PPC::LR8) continue;
1021 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1022 MachineLocation CSSrc(Reg);
1023 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
1026 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
1027 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
1028 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
1030 // Mark effective beginning of when frame pointer is ready.
1031 unsigned ReadyLabelId = MMI->NextLabelID();
1032 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId);
1034 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
1035 (IsPPC64 ? PPC::X1 : PPC::R1));
1036 MachineLocation FPSrc(MachineLocation::VirtualFP);
1037 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1040 // If there is a frame pointer, copy R1 into R31
1043 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1)
1046 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1)
1052 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
1053 MachineBasicBlock &MBB) const {
1054 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1055 assert(MBBI->getOpcode() == PPC::BLR &&
1056 "Can only insert epilog into returning blocks");
1058 // Get alignment info so we know how to restore r1
1059 const MachineFrameInfo *MFI = MF.getFrameInfo();
1060 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1061 unsigned MaxAlign = MFI->getMaxAlignment();
1063 // Get the number of bytes allocated from the FrameInfo.
1064 unsigned FrameSize = MFI->getStackSize();
1066 // Get processor type.
1067 bool IsPPC64 = Subtarget.isPPC64();
1068 // Get operating system
1069 bool IsMachoABI = Subtarget.isMachoABI();
1070 // Check if the link register (LR) has been used.
1071 bool UsesLR = MFI->hasCalls() || usesLR(MF);
1072 // Do we have a frame pointer for this function?
1073 bool HasFP = hasFP(MF) && FrameSize;
1075 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
1076 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
1079 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
1080 // on entry to the function. Add this offset back now.
1081 if (!Subtarget.isPPC64()) {
1082 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1083 !MFI->hasVarSizedObjects()) {
1084 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
1085 .addReg(PPC::R1).addImm(FrameSize);
1087 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1);
1090 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1091 !MFI->hasVarSizedObjects()) {
1092 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
1093 .addReg(PPC::X1).addImm(FrameSize);
1095 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1);
1102 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0)
1103 .addImm(LROffset/4).addReg(PPC::X1);
1106 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31)
1107 .addImm(FPOffset/4).addReg(PPC::X1);
1110 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0);
1113 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0)
1114 .addImm(LROffset).addReg(PPC::R1);
1117 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31)
1118 .addImm(FPOffset).addReg(PPC::R1);
1121 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0);
1125 unsigned PPCRegisterInfo::getRARegister() const {
1126 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
1129 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1130 if (!Subtarget.isPPC64())
1131 return hasFP(MF) ? PPC::R31 : PPC::R1;
1133 return hasFP(MF) ? PPC::X31 : PPC::X1;
1136 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1138 // Initial state of the frame pointer is R1.
1139 MachineLocation Dst(MachineLocation::VirtualFP);
1140 MachineLocation Src(PPC::R1, 0);
1141 Moves.push_back(MachineMove(0, Dst, Src));
1144 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
1145 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
1148 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
1149 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
1152 #include "PPCGenRegisterInfo.inc"