1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
60 def tocentry32 : Operand<iPTR> {
61 let MIOperandInfo = (ops i32imm:$imm);
64 //===----------------------------------------------------------------------===//
65 // PowerPC specific DAG Nodes.
68 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
69 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
71 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
72 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
73 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
74 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
75 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
76 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
77 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
78 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
79 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
80 [SDNPHasChain, SDNPMayStore]>;
81 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
82 [SDNPHasChain, SDNPMayLoad]>;
83 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
84 [SDNPHasChain, SDNPMayLoad]>;
86 // Extract FPSCR (not modeled at the DAG level).
87 def PPCmffs : SDNode<"PPCISD::MFFS",
88 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
90 // Perform FADD in round-to-zero mode.
91 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
94 def PPCfsel : SDNode<"PPCISD::FSEL",
95 // Type constraint for fsel.
96 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
97 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
99 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
100 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
101 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
102 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
103 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
105 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
107 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
108 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
110 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
111 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
112 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
113 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
114 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
115 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
116 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
117 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
119 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
121 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
123 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
124 // amounts. These nodes are generated by the multi-precision shift code.
125 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
126 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
127 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
129 // These are target-independent nodes, but have target-specific formats.
130 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
131 [SDNPHasChain, SDNPOutGlue]>;
132 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
133 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
135 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
136 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
137 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
139 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
140 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
142 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
143 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
144 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
145 [SDNPHasChain, SDNPSideEffect,
146 SDNPInGlue, SDNPOutGlue]>;
147 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
149 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
150 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
153 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
154 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
156 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
157 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
159 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
160 SDTypeProfile<1, 1, [SDTCisInt<0>,
162 [SDNPHasChain, SDNPSideEffect]>;
163 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
164 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
165 [SDNPHasChain, SDNPSideEffect]>;
167 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
168 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
169 [SDNPHasChain, SDNPSideEffect]>;
171 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
172 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
174 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
175 [SDNPHasChain, SDNPOptInGlue]>;
177 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
178 [SDNPHasChain, SDNPMayLoad]>;
179 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
180 [SDNPHasChain, SDNPMayStore]>;
182 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
183 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
184 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
185 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
186 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
188 // Instructions to support atomic operations
189 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
190 [SDNPHasChain, SDNPMayLoad]>;
191 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
192 [SDNPHasChain, SDNPMayStore]>;
194 // Instructions to support medium and large code model
195 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
196 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
197 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
200 // Instructions to support dynamic alloca.
201 def SDTDynOp : SDTypeProfile<1, 2, []>;
202 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
204 //===----------------------------------------------------------------------===//
205 // PowerPC specific transformation functions and pattern fragments.
208 def SHL32 : SDNodeXForm<imm, [{
209 // Transformation function: 31 - imm
210 return getI32Imm(31 - N->getZExtValue());
213 def SRL32 : SDNodeXForm<imm, [{
214 // Transformation function: 32 - imm
215 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
218 def LO16 : SDNodeXForm<imm, [{
219 // Transformation function: get the low 16 bits.
220 return getI32Imm((unsigned short)N->getZExtValue());
223 def HI16 : SDNodeXForm<imm, [{
224 // Transformation function: shift the immediate value down into the low bits.
225 return getI32Imm((unsigned)N->getZExtValue() >> 16);
228 def HA16 : SDNodeXForm<imm, [{
229 // Transformation function: shift the immediate value down into the low bits.
230 signed int Val = N->getZExtValue();
231 return getI32Imm((Val - (signed short)Val) >> 16);
233 def MB : SDNodeXForm<imm, [{
234 // Transformation function: get the start bit of a mask
236 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
237 return getI32Imm(mb);
240 def ME : SDNodeXForm<imm, [{
241 // Transformation function: get the end bit of a mask
243 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
244 return getI32Imm(me);
246 def maskimm32 : PatLeaf<(imm), [{
247 // maskImm predicate - True if immediate is a run of ones.
249 if (N->getValueType(0) == MVT::i32)
250 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
255 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
256 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
257 // sign extended field. Used by instructions like 'addi'.
258 return (int32_t)Imm == (short)Imm;
260 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
261 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
262 // sign extended field. Used by instructions like 'addi'.
263 return (int64_t)Imm == (short)Imm;
265 def immZExt16 : PatLeaf<(imm), [{
266 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
267 // field. Used by instructions like 'ori'.
268 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
271 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
272 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
273 // identical in 32-bit mode, but in 64-bit mode, they return true if the
274 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
276 def imm16ShiftedZExt : PatLeaf<(imm), [{
277 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
278 // immediate are set. Used by instructions like 'xoris'.
279 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
282 def imm16ShiftedSExt : PatLeaf<(imm), [{
283 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
284 // immediate are set. Used by instructions like 'addis'. Identical to
285 // imm16ShiftedZExt in 32-bit mode.
286 if (N->getZExtValue() & 0xFFFF) return false;
287 if (N->getValueType(0) == MVT::i32)
289 // For 64-bit, make sure it is sext right.
290 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
293 def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
294 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
295 // zero extended field.
296 return isUInt<32>(Imm);
299 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
300 // restricted memrix (4-aligned) constants are alignment sensitive. If these
301 // offsets are hidden behind TOC entries than the values of the lower-order
302 // bits cannot be checked directly. As a result, we need to also incorporate
303 // an alignment check into the relevant patterns.
305 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
306 return cast<LoadSDNode>(N)->getAlignment() >= 4;
308 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
309 (store node:$val, node:$ptr), [{
310 return cast<StoreSDNode>(N)->getAlignment() >= 4;
312 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
313 return cast<LoadSDNode>(N)->getAlignment() >= 4;
315 def aligned4pre_store : PatFrag<
316 (ops node:$val, node:$base, node:$offset),
317 (pre_store node:$val, node:$base, node:$offset), [{
318 return cast<StoreSDNode>(N)->getAlignment() >= 4;
321 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
322 return cast<LoadSDNode>(N)->getAlignment() < 4;
324 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
325 (store node:$val, node:$ptr), [{
326 return cast<StoreSDNode>(N)->getAlignment() < 4;
328 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
329 return cast<LoadSDNode>(N)->getAlignment() < 4;
332 //===----------------------------------------------------------------------===//
333 // PowerPC Flag Definitions.
335 class isPPC64 { bit PPC64 = 1; }
336 class isDOT { bit RC = 1; }
338 class RegConstraint<string C> {
339 string Constraints = C;
341 class NoEncode<string E> {
342 string DisableEncoding = E;
346 //===----------------------------------------------------------------------===//
347 // PowerPC Operand Definitions.
349 // In the default PowerPC assembler syntax, registers are specified simply
350 // by number, so they cannot be distinguished from immediate values (without
351 // looking at the opcode). This means that the default operand matching logic
352 // for the asm parser does not work, and we need to specify custom matchers.
353 // Since those can only be specified with RegisterOperand classes and not
354 // directly on the RegisterClass, all instructions patterns used by the asm
355 // parser need to use a RegisterOperand (instead of a RegisterClass) for
356 // all their register operands.
357 // For this purpose, we define one RegisterOperand for each RegisterClass,
358 // using the same name as the class, just in lower case.
360 def PPCRegGPRCAsmOperand : AsmOperandClass {
361 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
363 def gprc : RegisterOperand<GPRC> {
364 let ParserMatchClass = PPCRegGPRCAsmOperand;
366 def PPCRegG8RCAsmOperand : AsmOperandClass {
367 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
369 def g8rc : RegisterOperand<G8RC> {
370 let ParserMatchClass = PPCRegG8RCAsmOperand;
372 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
373 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
375 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
376 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
378 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
379 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
381 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
382 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
384 def PPCRegF8RCAsmOperand : AsmOperandClass {
385 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
387 def f8rc : RegisterOperand<F8RC> {
388 let ParserMatchClass = PPCRegF8RCAsmOperand;
390 def PPCRegF4RCAsmOperand : AsmOperandClass {
391 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
393 def f4rc : RegisterOperand<F4RC> {
394 let ParserMatchClass = PPCRegF4RCAsmOperand;
396 def PPCRegVRRCAsmOperand : AsmOperandClass {
397 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
399 def vrrc : RegisterOperand<VRRC> {
400 let ParserMatchClass = PPCRegVRRCAsmOperand;
402 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
403 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
405 def crbitrc : RegisterOperand<CRBITRC> {
406 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
408 def PPCRegCRRCAsmOperand : AsmOperandClass {
409 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
411 def crrc : RegisterOperand<CRRC> {
412 let ParserMatchClass = PPCRegCRRCAsmOperand;
415 def PPCU2ImmAsmOperand : AsmOperandClass {
416 let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
417 let RenderMethod = "addImmOperands";
419 def u2imm : Operand<i32> {
420 let PrintMethod = "printU2ImmOperand";
421 let ParserMatchClass = PPCU2ImmAsmOperand;
424 def PPCU4ImmAsmOperand : AsmOperandClass {
425 let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
426 let RenderMethod = "addImmOperands";
428 def u4imm : Operand<i32> {
429 let PrintMethod = "printU4ImmOperand";
430 let ParserMatchClass = PPCU4ImmAsmOperand;
432 def PPCS5ImmAsmOperand : AsmOperandClass {
433 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
434 let RenderMethod = "addImmOperands";
436 def s5imm : Operand<i32> {
437 let PrintMethod = "printS5ImmOperand";
438 let ParserMatchClass = PPCS5ImmAsmOperand;
439 let DecoderMethod = "decodeSImmOperand<5>";
441 def PPCU5ImmAsmOperand : AsmOperandClass {
442 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
443 let RenderMethod = "addImmOperands";
445 def u5imm : Operand<i32> {
446 let PrintMethod = "printU5ImmOperand";
447 let ParserMatchClass = PPCU5ImmAsmOperand;
448 let DecoderMethod = "decodeUImmOperand<5>";
450 def PPCU6ImmAsmOperand : AsmOperandClass {
451 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
452 let RenderMethod = "addImmOperands";
454 def u6imm : Operand<i32> {
455 let PrintMethod = "printU6ImmOperand";
456 let ParserMatchClass = PPCU6ImmAsmOperand;
457 let DecoderMethod = "decodeUImmOperand<6>";
459 def PPCS16ImmAsmOperand : AsmOperandClass {
460 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
461 let RenderMethod = "addImmOperands";
463 def s16imm : Operand<i32> {
464 let PrintMethod = "printS16ImmOperand";
465 let EncoderMethod = "getImm16Encoding";
466 let ParserMatchClass = PPCS16ImmAsmOperand;
467 let DecoderMethod = "decodeSImmOperand<16>";
469 def PPCU16ImmAsmOperand : AsmOperandClass {
470 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
471 let RenderMethod = "addImmOperands";
473 def u16imm : Operand<i32> {
474 let PrintMethod = "printU16ImmOperand";
475 let EncoderMethod = "getImm16Encoding";
476 let ParserMatchClass = PPCU16ImmAsmOperand;
477 let DecoderMethod = "decodeUImmOperand<16>";
479 def PPCS17ImmAsmOperand : AsmOperandClass {
480 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
481 let RenderMethod = "addImmOperands";
483 def s17imm : Operand<i32> {
484 // This operand type is used for addis/lis to allow the assembler parser
485 // to accept immediates in the range -65536..65535 for compatibility with
486 // the GNU assembler. The operand is treated as 16-bit otherwise.
487 let PrintMethod = "printS16ImmOperand";
488 let EncoderMethod = "getImm16Encoding";
489 let ParserMatchClass = PPCS17ImmAsmOperand;
490 let DecoderMethod = "decodeSImmOperand<16>";
492 def PPCDirectBrAsmOperand : AsmOperandClass {
493 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
494 let RenderMethod = "addBranchTargetOperands";
496 def directbrtarget : Operand<OtherVT> {
497 let PrintMethod = "printBranchOperand";
498 let EncoderMethod = "getDirectBrEncoding";
499 let ParserMatchClass = PPCDirectBrAsmOperand;
501 def absdirectbrtarget : Operand<OtherVT> {
502 let PrintMethod = "printAbsBranchOperand";
503 let EncoderMethod = "getAbsDirectBrEncoding";
504 let ParserMatchClass = PPCDirectBrAsmOperand;
506 def PPCCondBrAsmOperand : AsmOperandClass {
507 let Name = "CondBr"; let PredicateMethod = "isCondBr";
508 let RenderMethod = "addBranchTargetOperands";
510 def condbrtarget : Operand<OtherVT> {
511 let PrintMethod = "printBranchOperand";
512 let EncoderMethod = "getCondBrEncoding";
513 let ParserMatchClass = PPCCondBrAsmOperand;
515 def abscondbrtarget : Operand<OtherVT> {
516 let PrintMethod = "printAbsBranchOperand";
517 let EncoderMethod = "getAbsCondBrEncoding";
518 let ParserMatchClass = PPCCondBrAsmOperand;
520 def calltarget : Operand<iPTR> {
521 let PrintMethod = "printBranchOperand";
522 let EncoderMethod = "getDirectBrEncoding";
523 let ParserMatchClass = PPCDirectBrAsmOperand;
525 def abscalltarget : Operand<iPTR> {
526 let PrintMethod = "printAbsBranchOperand";
527 let EncoderMethod = "getAbsDirectBrEncoding";
528 let ParserMatchClass = PPCDirectBrAsmOperand;
530 def PPCCRBitMaskOperand : AsmOperandClass {
531 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
533 def crbitm: Operand<i8> {
534 let PrintMethod = "printcrbitm";
535 let EncoderMethod = "get_crbitm_encoding";
536 let DecoderMethod = "decodeCRBitMOperand";
537 let ParserMatchClass = PPCCRBitMaskOperand;
540 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
541 def PPCRegGxRCNoR0Operand : AsmOperandClass {
542 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
544 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
545 let ParserMatchClass = PPCRegGxRCNoR0Operand;
547 // A version of ptr_rc usable with the asm parser.
548 def PPCRegGxRCOperand : AsmOperandClass {
549 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
551 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
552 let ParserMatchClass = PPCRegGxRCOperand;
555 def PPCDispRIOperand : AsmOperandClass {
556 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
557 let RenderMethod = "addImmOperands";
559 def dispRI : Operand<iPTR> {
560 let ParserMatchClass = PPCDispRIOperand;
562 def PPCDispRIXOperand : AsmOperandClass {
563 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
564 let RenderMethod = "addImmOperands";
566 def dispRIX : Operand<iPTR> {
567 let ParserMatchClass = PPCDispRIXOperand;
570 def memri : Operand<iPTR> {
571 let PrintMethod = "printMemRegImm";
572 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
573 let EncoderMethod = "getMemRIEncoding";
574 let DecoderMethod = "decodeMemRIOperands";
576 def memrr : Operand<iPTR> {
577 let PrintMethod = "printMemRegReg";
578 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
580 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
581 let PrintMethod = "printMemRegImm";
582 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
583 let EncoderMethod = "getMemRIXEncoding";
584 let DecoderMethod = "decodeMemRIXOperands";
587 // A single-register address. This is used with the SjLj
588 // pseudo-instructions.
589 def memr : Operand<iPTR> {
590 let MIOperandInfo = (ops ptr_rc:$ptrreg);
592 def PPCTLSRegOperand : AsmOperandClass {
593 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
594 let RenderMethod = "addTLSRegOperands";
596 def tlsreg32 : Operand<i32> {
597 let EncoderMethod = "getTLSRegEncoding";
598 let ParserMatchClass = PPCTLSRegOperand;
600 def tlsgd32 : Operand<i32> {}
601 def tlscall32 : Operand<i32> {
602 let PrintMethod = "printTLSCall";
603 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
604 let EncoderMethod = "getTLSCallEncoding";
607 // PowerPC Predicate operand.
608 def pred : Operand<OtherVT> {
609 let PrintMethod = "printPredicateOperand";
610 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
613 // Define PowerPC specific addressing mode.
614 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
615 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
616 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
617 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
619 // The address in a single register. This is used with the SjLj
620 // pseudo-instructions.
621 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
623 /// This is just the offset part of iaddr, used for preinc.
624 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
626 //===----------------------------------------------------------------------===//
627 // PowerPC Instruction Predicate Definitions.
628 def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">;
629 def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">;
630 def IsBookE : Predicate<"PPCSubTarget->isBookE()">;
631 def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">;
632 def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">;
633 def IsE500 : Predicate<"PPCSubTarget->isE500()">;
635 //===----------------------------------------------------------------------===//
636 // PowerPC Multiclass Definitions.
638 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
639 string asmbase, string asmstr, InstrItinClass itin,
641 let BaseName = asmbase in {
642 def NAME : XForm_6<opcode, xo, OOL, IOL,
643 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
644 pattern>, RecFormRel;
646 def o : XForm_6<opcode, xo, OOL, IOL,
647 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
648 []>, isDOT, RecFormRel;
652 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
653 string asmbase, string asmstr, InstrItinClass itin,
655 let BaseName = asmbase in {
656 let Defs = [CARRY] in
657 def NAME : XForm_6<opcode, xo, OOL, IOL,
658 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
659 pattern>, RecFormRel;
660 let Defs = [CARRY, CR0] in
661 def o : XForm_6<opcode, xo, OOL, IOL,
662 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
663 []>, isDOT, RecFormRel;
667 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
668 string asmbase, string asmstr, InstrItinClass itin,
670 let BaseName = asmbase in {
671 let Defs = [CARRY] in
672 def NAME : XForm_10<opcode, xo, OOL, IOL,
673 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
674 pattern>, RecFormRel;
675 let Defs = [CARRY, CR0] in
676 def o : XForm_10<opcode, xo, OOL, IOL,
677 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
678 []>, isDOT, RecFormRel;
682 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
683 string asmbase, string asmstr, InstrItinClass itin,
685 let BaseName = asmbase in {
686 def NAME : XForm_11<opcode, xo, OOL, IOL,
687 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
688 pattern>, RecFormRel;
690 def o : XForm_11<opcode, xo, OOL, IOL,
691 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
692 []>, isDOT, RecFormRel;
696 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
697 string asmbase, string asmstr, InstrItinClass itin,
699 let BaseName = asmbase in {
700 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
701 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
702 pattern>, RecFormRel;
704 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
705 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
706 []>, isDOT, RecFormRel;
710 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
711 string asmbase, string asmstr, InstrItinClass itin,
713 let BaseName = asmbase in {
714 let Defs = [CARRY] in
715 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
716 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
717 pattern>, RecFormRel;
718 let Defs = [CARRY, CR0] in
719 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
720 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
721 []>, isDOT, RecFormRel;
725 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
726 string asmbase, string asmstr, InstrItinClass itin,
728 let BaseName = asmbase in {
729 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
730 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
731 pattern>, RecFormRel;
733 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
734 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
735 []>, isDOT, RecFormRel;
739 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
740 string asmbase, string asmstr, InstrItinClass itin,
742 let BaseName = asmbase in {
743 let Defs = [CARRY] in
744 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
745 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
746 pattern>, RecFormRel;
747 let Defs = [CARRY, CR0] in
748 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
749 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
750 []>, isDOT, RecFormRel;
754 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
755 string asmbase, string asmstr, InstrItinClass itin,
757 let BaseName = asmbase in {
758 def NAME : MForm_2<opcode, OOL, IOL,
759 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
760 pattern>, RecFormRel;
762 def o : MForm_2<opcode, OOL, IOL,
763 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
764 []>, isDOT, RecFormRel;
768 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
769 string asmbase, string asmstr, InstrItinClass itin,
771 let BaseName = asmbase in {
772 def NAME : MDForm_1<opcode, xo, OOL, IOL,
773 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
774 pattern>, RecFormRel;
776 def o : MDForm_1<opcode, xo, OOL, IOL,
777 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
778 []>, isDOT, RecFormRel;
782 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
783 string asmbase, string asmstr, InstrItinClass itin,
785 let BaseName = asmbase in {
786 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
787 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
788 pattern>, RecFormRel;
790 def o : MDSForm_1<opcode, xo, OOL, IOL,
791 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
792 []>, isDOT, RecFormRel;
796 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
797 string asmbase, string asmstr, InstrItinClass itin,
799 let BaseName = asmbase in {
800 let Defs = [CARRY] in
801 def NAME : XSForm_1<opcode, xo, OOL, IOL,
802 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
803 pattern>, RecFormRel;
804 let Defs = [CARRY, CR0] in
805 def o : XSForm_1<opcode, xo, OOL, IOL,
806 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
807 []>, isDOT, RecFormRel;
811 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
812 string asmbase, string asmstr, InstrItinClass itin,
814 let BaseName = asmbase in {
815 def NAME : XForm_26<opcode, xo, OOL, IOL,
816 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
817 pattern>, RecFormRel;
819 def o : XForm_26<opcode, xo, OOL, IOL,
820 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
821 []>, isDOT, RecFormRel;
825 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
826 string asmbase, string asmstr, InstrItinClass itin,
828 let BaseName = asmbase in {
829 def NAME : XForm_28<opcode, xo, OOL, IOL,
830 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
831 pattern>, RecFormRel;
833 def o : XForm_28<opcode, xo, OOL, IOL,
834 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
835 []>, isDOT, RecFormRel;
839 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
840 string asmbase, string asmstr, InstrItinClass itin,
842 let BaseName = asmbase in {
843 def NAME : AForm_1<opcode, xo, OOL, IOL,
844 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
845 pattern>, RecFormRel;
847 def o : AForm_1<opcode, xo, OOL, IOL,
848 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
849 []>, isDOT, RecFormRel;
853 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
854 string asmbase, string asmstr, InstrItinClass itin,
856 let BaseName = asmbase in {
857 def NAME : AForm_2<opcode, xo, OOL, IOL,
858 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
859 pattern>, RecFormRel;
861 def o : AForm_2<opcode, xo, OOL, IOL,
862 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
863 []>, isDOT, RecFormRel;
867 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
868 string asmbase, string asmstr, InstrItinClass itin,
870 let BaseName = asmbase in {
871 def NAME : AForm_3<opcode, xo, OOL, IOL,
872 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
873 pattern>, RecFormRel;
875 def o : AForm_3<opcode, xo, OOL, IOL,
876 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
877 []>, isDOT, RecFormRel;
881 //===----------------------------------------------------------------------===//
882 // PowerPC Instruction Definitions.
884 // Pseudo-instructions:
886 let hasCtrlDep = 1 in {
887 let Defs = [R1], Uses = [R1] in {
888 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
889 [(callseq_start timm:$amt)]>;
890 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
891 [(callseq_end timm:$amt1, timm:$amt2)]>;
894 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
895 "UPDATE_VRSAVE $rD, $rS", []>;
898 let Defs = [R1], Uses = [R1] in
899 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
901 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
903 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
904 // instruction selection into a branch sequence.
905 let usesCustomInserter = 1, // Expanded after instruction selection.
906 PPC970_Single = 1 in {
907 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
908 // because either operand might become the first operand in an isel, and
909 // that operand cannot be r0.
910 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
911 gprc_nor0:$T, gprc_nor0:$F,
912 i32imm:$BROPC), "#SELECT_CC_I4",
914 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
915 g8rc_nox0:$T, g8rc_nox0:$F,
916 i32imm:$BROPC), "#SELECT_CC_I8",
918 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
919 i32imm:$BROPC), "#SELECT_CC_F4",
921 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
922 i32imm:$BROPC), "#SELECT_CC_F8",
924 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
925 i32imm:$BROPC), "#SELECT_CC_VRRC",
928 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
929 // register bit directly.
930 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
931 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
932 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
933 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
934 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
935 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
936 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
937 f4rc:$T, f4rc:$F), "#SELECT_F4",
938 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
939 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
940 f8rc:$T, f8rc:$F), "#SELECT_F8",
941 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
942 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
943 vrrc:$T, vrrc:$F), "#SELECT_VRRC",
945 (select i1:$cond, v4i32:$T, v4i32:$F))]>;
948 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
949 // scavenge a register for it.
950 let mayStore = 1 in {
951 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
953 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
957 // RESTORE_CR - Indicate that we're restoring the CR register (previously
958 // spilled), so we'll need to scavenge a register for it.
960 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
962 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
963 "#RESTORE_CRBIT", []>;
966 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
967 let isReturn = 1, Uses = [LR, RM] in
968 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
970 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
971 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
974 let isCodeGenOnly = 1 in {
975 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
976 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
979 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
980 "bcctr 12, $bi, 0", IIC_BrB, []>;
981 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
982 "bcctr 4, $bi, 0", IIC_BrB, []>;
988 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
991 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
992 let isBarrier = 1 in {
993 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
996 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
997 "ba $dst", IIC_BrB, []>;
1000 // BCC represents an arbitrary conditional branch on a predicate.
1001 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1002 // a two-value operand where a dag node expects two operands. :(
1003 let isCodeGenOnly = 1 in {
1004 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1005 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1006 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1007 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1008 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1010 let isReturn = 1, Uses = [LR, RM] in
1011 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1012 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1015 let isCodeGenOnly = 1 in {
1016 let Pattern = [(brcond i1:$bi, bb:$dst)] in
1017 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1018 "bc 12, $bi, $dst">;
1020 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1021 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1024 let isReturn = 1, Uses = [LR, RM] in
1025 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1026 "bclr 12, $bi, 0", IIC_BrB, []>;
1027 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1028 "bclr 4, $bi, 0", IIC_BrB, []>;
1031 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1032 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1033 "bdzlr", IIC_BrB, []>;
1034 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1035 "bdnzlr", IIC_BrB, []>;
1036 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1037 "bdzlr+", IIC_BrB, []>;
1038 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1039 "bdnzlr+", IIC_BrB, []>;
1040 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1041 "bdzlr-", IIC_BrB, []>;
1042 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1043 "bdnzlr-", IIC_BrB, []>;
1046 let Defs = [CTR], Uses = [CTR] in {
1047 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1049 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1051 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1053 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1055 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1057 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1059 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1061 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1063 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1065 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1067 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1069 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1074 // The unconditional BCL used by the SjLj setjmp code.
1075 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1076 let Defs = [LR], Uses = [RM] in {
1077 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1078 "bcl 20, 31, $dst">;
1082 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1083 // Convenient aliases for call instructions
1084 let Uses = [RM] in {
1085 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1086 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1087 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1088 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1090 let isCodeGenOnly = 1 in {
1091 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1092 "bl $func", IIC_BrB, []>;
1093 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1094 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1095 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1096 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1098 def BCL : BForm_4<16, 12, 0, 1, (outs),
1099 (ins crbitrc:$bi, condbrtarget:$dst),
1100 "bcl 12, $bi, $dst">;
1101 def BCLn : BForm_4<16, 4, 0, 1, (outs),
1102 (ins crbitrc:$bi, condbrtarget:$dst),
1103 "bcl 4, $bi, $dst">;
1106 let Uses = [CTR, RM] in {
1107 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1108 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1109 Requires<[In32BitMode]>;
1111 let isCodeGenOnly = 1 in {
1112 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1113 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1116 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1117 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1118 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1119 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1122 let Uses = [LR, RM] in {
1123 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1124 "blrl", IIC_BrB, []>;
1126 let isCodeGenOnly = 1 in {
1127 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1128 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1131 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1132 "bclrl 12, $bi, 0", IIC_BrB, []>;
1133 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1134 "bclrl 4, $bi, 0", IIC_BrB, []>;
1137 let Defs = [CTR], Uses = [CTR, RM] in {
1138 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1140 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1142 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1144 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1146 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1148 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1150 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1152 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1154 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1156 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1158 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1160 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1163 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1164 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1165 "bdzlrl", IIC_BrB, []>;
1166 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1167 "bdnzlrl", IIC_BrB, []>;
1168 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1169 "bdzlrl+", IIC_BrB, []>;
1170 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1171 "bdnzlrl+", IIC_BrB, []>;
1172 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1173 "bdzlrl-", IIC_BrB, []>;
1174 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1175 "bdnzlrl-", IIC_BrB, []>;
1179 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1180 def TCRETURNdi :Pseudo< (outs),
1181 (ins calltarget:$dst, i32imm:$offset),
1182 "#TC_RETURNd $dst $offset",
1186 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1187 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1188 "#TC_RETURNa $func $offset",
1189 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1191 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1192 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1193 "#TC_RETURNr $dst $offset",
1197 let isCodeGenOnly = 1 in {
1199 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1200 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1201 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1202 []>, Requires<[In32BitMode]>;
1204 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1205 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1206 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1210 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1211 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1212 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1218 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1220 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1221 "#EH_SJLJ_SETJMP32",
1222 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1223 Requires<[In32BitMode]>;
1224 let isTerminator = 1 in
1225 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1226 "#EH_SJLJ_LONGJMP32",
1227 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1228 Requires<[In32BitMode]>;
1231 let isBranch = 1, isTerminator = 1 in {
1232 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1233 "#EH_SjLj_Setup\t$dst", []>;
1237 let PPC970_Unit = 7 in {
1238 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1239 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1242 // DCB* instructions.
1243 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1244 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1245 PPC970_DGroup_Single;
1246 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1247 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1248 PPC970_DGroup_Single;
1249 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1250 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1251 PPC970_DGroup_Single;
1252 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1253 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1254 PPC970_DGroup_Single;
1255 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst",
1256 IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1257 PPC970_DGroup_Single;
1258 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst",
1259 IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1260 PPC970_DGroup_Single;
1261 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1262 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1263 PPC970_DGroup_Single;
1264 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1265 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1266 PPC970_DGroup_Single;
1268 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1269 (DCBT xoaddr:$dst)>;
1271 // Atomic operations
1272 let usesCustomInserter = 1 in {
1273 let Defs = [CR0] in {
1274 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1275 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1276 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1277 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1278 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1279 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1280 def ATOMIC_LOAD_AND_I8 : Pseudo<
1281 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1282 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1283 def ATOMIC_LOAD_OR_I8 : Pseudo<
1284 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1285 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1286 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1287 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1288 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1289 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1290 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1291 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1292 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1293 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1294 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1295 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1296 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1297 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1298 def ATOMIC_LOAD_AND_I16 : Pseudo<
1299 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1300 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1301 def ATOMIC_LOAD_OR_I16 : Pseudo<
1302 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1303 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1304 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1305 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1306 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1307 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1308 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1309 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1310 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1311 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1312 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1313 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1314 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1315 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1316 def ATOMIC_LOAD_AND_I32 : Pseudo<
1317 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1318 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1319 def ATOMIC_LOAD_OR_I32 : Pseudo<
1320 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1321 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1322 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1323 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1324 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1325 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1326 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1327 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1329 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1330 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1331 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1332 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1333 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1334 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1335 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1336 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1337 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1339 def ATOMIC_SWAP_I8 : Pseudo<
1340 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1341 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1342 def ATOMIC_SWAP_I16 : Pseudo<
1343 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1344 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1345 def ATOMIC_SWAP_I32 : Pseudo<
1346 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1347 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1351 // Instructions to support atomic operations
1352 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1353 "lwarx $rD, $src", IIC_LdStLWARX,
1354 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1357 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1358 "stwcx. $rS, $dst", IIC_LdStSTWCX,
1359 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1362 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1363 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1365 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1366 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1367 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1368 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1369 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1370 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1371 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1372 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1374 //===----------------------------------------------------------------------===//
1375 // PPC32 Load Instructions.
1378 // Unindexed (r+i) Loads.
1379 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1380 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1381 "lbz $rD, $src", IIC_LdStLoad,
1382 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1383 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1384 "lha $rD, $src", IIC_LdStLHA,
1385 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1386 PPC970_DGroup_Cracked;
1387 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1388 "lhz $rD, $src", IIC_LdStLoad,
1389 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1390 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1391 "lwz $rD, $src", IIC_LdStLoad,
1392 [(set i32:$rD, (load iaddr:$src))]>;
1394 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1395 "lfs $rD, $src", IIC_LdStLFD,
1396 [(set f32:$rD, (load iaddr:$src))]>;
1397 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1398 "lfd $rD, $src", IIC_LdStLFD,
1399 [(set f64:$rD, (load iaddr:$src))]>;
1402 // Unindexed (r+i) Loads with Update (preinc).
1403 let mayLoad = 1, neverHasSideEffects = 1 in {
1404 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1405 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1406 []>, RegConstraint<"$addr.reg = $ea_result">,
1407 NoEncode<"$ea_result">;
1409 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1410 "lhau $rD, $addr", IIC_LdStLHAU,
1411 []>, RegConstraint<"$addr.reg = $ea_result">,
1412 NoEncode<"$ea_result">;
1414 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1415 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1416 []>, RegConstraint<"$addr.reg = $ea_result">,
1417 NoEncode<"$ea_result">;
1419 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1420 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1421 []>, RegConstraint<"$addr.reg = $ea_result">,
1422 NoEncode<"$ea_result">;
1424 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1425 "lfsu $rD, $addr", IIC_LdStLFDU,
1426 []>, RegConstraint<"$addr.reg = $ea_result">,
1427 NoEncode<"$ea_result">;
1429 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1430 "lfdu $rD, $addr", IIC_LdStLFDU,
1431 []>, RegConstraint<"$addr.reg = $ea_result">,
1432 NoEncode<"$ea_result">;
1435 // Indexed (r+r) Loads with Update (preinc).
1436 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1438 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1439 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1440 NoEncode<"$ea_result">;
1442 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1444 "lhaux $rD, $addr", IIC_LdStLHAUX,
1445 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1446 NoEncode<"$ea_result">;
1448 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1450 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1451 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1452 NoEncode<"$ea_result">;
1454 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1456 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1457 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1458 NoEncode<"$ea_result">;
1460 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1462 "lfsux $rD, $addr", IIC_LdStLFDUX,
1463 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1464 NoEncode<"$ea_result">;
1466 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1468 "lfdux $rD, $addr", IIC_LdStLFDUX,
1469 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1470 NoEncode<"$ea_result">;
1474 // Indexed (r+r) Loads.
1476 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1477 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1478 "lbzx $rD, $src", IIC_LdStLoad,
1479 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1480 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1481 "lhax $rD, $src", IIC_LdStLHA,
1482 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1483 PPC970_DGroup_Cracked;
1484 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1485 "lhzx $rD, $src", IIC_LdStLoad,
1486 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1487 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1488 "lwzx $rD, $src", IIC_LdStLoad,
1489 [(set i32:$rD, (load xaddr:$src))]>;
1492 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1493 "lhbrx $rD, $src", IIC_LdStLoad,
1494 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1495 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1496 "lwbrx $rD, $src", IIC_LdStLoad,
1497 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1499 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1500 "lfsx $frD, $src", IIC_LdStLFD,
1501 [(set f32:$frD, (load xaddr:$src))]>;
1502 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1503 "lfdx $frD, $src", IIC_LdStLFD,
1504 [(set f64:$frD, (load xaddr:$src))]>;
1506 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1507 "lfiwax $frD, $src", IIC_LdStLFD,
1508 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1509 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1510 "lfiwzx $frD, $src", IIC_LdStLFD,
1511 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1515 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1516 "lmw $rD, $src", IIC_LdStLMW, []>;
1518 //===----------------------------------------------------------------------===//
1519 // PPC32 Store Instructions.
1522 // Unindexed (r+i) Stores.
1523 let PPC970_Unit = 2 in {
1524 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1525 "stb $rS, $src", IIC_LdStStore,
1526 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1527 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1528 "sth $rS, $src", IIC_LdStStore,
1529 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1530 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1531 "stw $rS, $src", IIC_LdStStore,
1532 [(store i32:$rS, iaddr:$src)]>;
1533 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1534 "stfs $rS, $dst", IIC_LdStSTFD,
1535 [(store f32:$rS, iaddr:$dst)]>;
1536 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1537 "stfd $rS, $dst", IIC_LdStSTFD,
1538 [(store f64:$rS, iaddr:$dst)]>;
1541 // Unindexed (r+i) Stores with Update (preinc).
1542 let PPC970_Unit = 2, mayStore = 1 in {
1543 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1544 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1545 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1546 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1547 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1548 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1549 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1550 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1551 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1552 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1553 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1554 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1555 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1556 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1557 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1560 // Patterns to match the pre-inc stores. We can't put the patterns on
1561 // the instruction definitions directly as ISel wants the address base
1562 // and offset to be separate operands, not a single complex operand.
1563 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1564 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1565 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1566 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1567 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1568 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1569 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1570 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1571 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1572 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1574 // Indexed (r+r) Stores.
1575 let PPC970_Unit = 2 in {
1576 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1577 "stbx $rS, $dst", IIC_LdStStore,
1578 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1579 PPC970_DGroup_Cracked;
1580 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1581 "sthx $rS, $dst", IIC_LdStStore,
1582 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1583 PPC970_DGroup_Cracked;
1584 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1585 "stwx $rS, $dst", IIC_LdStStore,
1586 [(store i32:$rS, xaddr:$dst)]>,
1587 PPC970_DGroup_Cracked;
1589 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1590 "sthbrx $rS, $dst", IIC_LdStStore,
1591 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1592 PPC970_DGroup_Cracked;
1593 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1594 "stwbrx $rS, $dst", IIC_LdStStore,
1595 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1596 PPC970_DGroup_Cracked;
1598 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1599 "stfiwx $frS, $dst", IIC_LdStSTFD,
1600 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1602 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1603 "stfsx $frS, $dst", IIC_LdStSTFD,
1604 [(store f32:$frS, xaddr:$dst)]>;
1605 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1606 "stfdx $frS, $dst", IIC_LdStSTFD,
1607 [(store f64:$frS, xaddr:$dst)]>;
1610 // Indexed (r+r) Stores with Update (preinc).
1611 let PPC970_Unit = 2, mayStore = 1 in {
1612 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1613 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1614 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1615 PPC970_DGroup_Cracked;
1616 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1617 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1618 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1619 PPC970_DGroup_Cracked;
1620 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1621 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1622 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1623 PPC970_DGroup_Cracked;
1624 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1625 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1626 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1627 PPC970_DGroup_Cracked;
1628 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1629 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1630 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1631 PPC970_DGroup_Cracked;
1634 // Patterns to match the pre-inc stores. We can't put the patterns on
1635 // the instruction definitions directly as ISel wants the address base
1636 // and offset to be separate operands, not a single complex operand.
1637 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1638 (STBUX $rS, $ptrreg, $ptroff)>;
1639 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1640 (STHUX $rS, $ptrreg, $ptroff)>;
1641 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1642 (STWUX $rS, $ptrreg, $ptroff)>;
1643 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1644 (STFSUX $rS, $ptrreg, $ptroff)>;
1645 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1646 (STFDUX $rS, $ptrreg, $ptroff)>;
1649 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1650 "stmw $rS, $dst", IIC_LdStLMW, []>;
1652 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1653 "sync $L", IIC_LdStSync, []>, Requires<[IsNotBookE]>;
1655 let isCodeGenOnly = 1 in {
1656 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1657 "msync", IIC_LdStSync, []>, Requires<[IsBookE]> {
1662 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[IsNotBookE]>;
1663 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[IsBookE]>;
1665 //===----------------------------------------------------------------------===//
1666 // PPC32 Arithmetic Instructions.
1669 let PPC970_Unit = 1 in { // FXU Operations.
1670 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1671 "addi $rD, $rA, $imm", IIC_IntSimple,
1672 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1673 let BaseName = "addic" in {
1674 let Defs = [CARRY] in
1675 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1676 "addic $rD, $rA, $imm", IIC_IntGeneral,
1677 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1678 RecFormRel, PPC970_DGroup_Cracked;
1679 let Defs = [CARRY, CR0] in
1680 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1681 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1682 []>, isDOT, RecFormRel;
1684 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1685 "addis $rD, $rA, $imm", IIC_IntSimple,
1686 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1687 let isCodeGenOnly = 1 in
1688 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1689 "la $rD, $sym($rA)", IIC_IntGeneral,
1690 [(set i32:$rD, (add i32:$rA,
1691 (PPClo tglobaladdr:$sym, 0)))]>;
1692 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1693 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1694 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1695 let Defs = [CARRY] in
1696 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1697 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1698 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1700 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1701 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1702 "li $rD, $imm", IIC_IntSimple,
1703 [(set i32:$rD, imm32SExt16:$imm)]>;
1704 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1705 "lis $rD, $imm", IIC_IntSimple,
1706 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1710 let PPC970_Unit = 1 in { // FXU Operations.
1711 let Defs = [CR0] in {
1712 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1713 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1714 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1716 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1717 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1718 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1721 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1722 "ori $dst, $src1, $src2", IIC_IntSimple,
1723 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1724 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1725 "oris $dst, $src1, $src2", IIC_IntSimple,
1726 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1727 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1728 "xori $dst, $src1, $src2", IIC_IntSimple,
1729 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1730 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1731 "xoris $dst, $src1, $src2", IIC_IntSimple,
1732 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1734 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1736 let isCodeGenOnly = 1 in {
1737 // The POWER6 and POWER7 have special group-terminating nops.
1738 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1739 "ori 1, 1, 0", IIC_IntSimple, []>;
1740 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1741 "ori 2, 2, 0", IIC_IntSimple, []>;
1744 let isCompare = 1, neverHasSideEffects = 1 in {
1745 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1746 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1747 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1748 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1752 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1753 let isCommutable = 1 in {
1754 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1755 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1756 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1757 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1758 "and", "$rA, $rS, $rB", IIC_IntSimple,
1759 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1761 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1762 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1763 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1764 let isCommutable = 1 in {
1765 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1766 "or", "$rA, $rS, $rB", IIC_IntSimple,
1767 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1768 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1769 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1770 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1772 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1773 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1774 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1775 let isCommutable = 1 in {
1776 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1777 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1778 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1779 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1780 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1781 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1783 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1784 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1785 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1786 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1787 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1788 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1789 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1790 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1791 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1794 let PPC970_Unit = 1 in { // FXU Operations.
1795 let neverHasSideEffects = 1 in {
1796 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1797 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1798 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1799 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1800 "cntlzw", "$rA, $rS", IIC_IntGeneral,
1801 [(set i32:$rA, (ctlz i32:$rS))]>;
1802 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1803 "extsb", "$rA, $rS", IIC_IntSimple,
1804 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1805 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1806 "extsh", "$rA, $rS", IIC_IntSimple,
1807 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1809 let isCompare = 1, neverHasSideEffects = 1 in {
1810 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1811 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
1812 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1813 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
1816 let PPC970_Unit = 3 in { // FPU Operations.
1817 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1818 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
1819 let isCompare = 1, neverHasSideEffects = 1 in {
1820 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1821 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1822 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1823 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1824 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1827 let Uses = [RM] in {
1828 let neverHasSideEffects = 1 in {
1829 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1830 "fctiw", "$frD, $frB", IIC_FPGeneral,
1832 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1833 "fctiwz", "$frD, $frB", IIC_FPGeneral,
1834 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1836 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1837 "frsp", "$frD, $frB", IIC_FPGeneral,
1838 [(set f32:$frD, (fround f64:$frB))]>;
1840 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1841 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1842 "frin", "$frD, $frB", IIC_FPGeneral,
1843 [(set f64:$frD, (frnd f64:$frB))]>;
1844 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1845 "frin", "$frD, $frB", IIC_FPGeneral,
1846 [(set f32:$frD, (frnd f32:$frB))]>;
1849 let neverHasSideEffects = 1 in {
1850 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1851 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1852 "frip", "$frD, $frB", IIC_FPGeneral,
1853 [(set f64:$frD, (fceil f64:$frB))]>;
1854 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1855 "frip", "$frD, $frB", IIC_FPGeneral,
1856 [(set f32:$frD, (fceil f32:$frB))]>;
1857 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1858 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1859 "friz", "$frD, $frB", IIC_FPGeneral,
1860 [(set f64:$frD, (ftrunc f64:$frB))]>;
1861 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1862 "friz", "$frD, $frB", IIC_FPGeneral,
1863 [(set f32:$frD, (ftrunc f32:$frB))]>;
1864 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1865 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1866 "frim", "$frD, $frB", IIC_FPGeneral,
1867 [(set f64:$frD, (ffloor f64:$frB))]>;
1868 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1869 "frim", "$frD, $frB", IIC_FPGeneral,
1870 [(set f32:$frD, (ffloor f32:$frB))]>;
1872 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1873 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
1874 [(set f64:$frD, (fsqrt f64:$frB))]>;
1875 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1876 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
1877 [(set f32:$frD, (fsqrt f32:$frB))]>;
1882 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1883 /// often coalesced away and we don't want the dispatch group builder to think
1884 /// that they will fill slots (which could cause the load of a LSU reject to
1885 /// sneak into a d-group with a store).
1886 let neverHasSideEffects = 1 in
1887 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1888 "fmr", "$frD, $frB", IIC_FPGeneral,
1889 []>, // (set f32:$frD, f32:$frB)
1892 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1893 // These are artificially split into two different forms, for 4/8 byte FP.
1894 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
1895 "fabs", "$frD, $frB", IIC_FPGeneral,
1896 [(set f32:$frD, (fabs f32:$frB))]>;
1897 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1898 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
1899 "fabs", "$frD, $frB", IIC_FPGeneral,
1900 [(set f64:$frD, (fabs f64:$frB))]>;
1901 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
1902 "fnabs", "$frD, $frB", IIC_FPGeneral,
1903 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1904 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1905 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
1906 "fnabs", "$frD, $frB", IIC_FPGeneral,
1907 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1908 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
1909 "fneg", "$frD, $frB", IIC_FPGeneral,
1910 [(set f32:$frD, (fneg f32:$frB))]>;
1911 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1912 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
1913 "fneg", "$frD, $frB", IIC_FPGeneral,
1914 [(set f64:$frD, (fneg f64:$frB))]>;
1916 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
1917 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1918 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
1919 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1920 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
1921 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
1922 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
1924 // Reciprocal estimates.
1925 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
1926 "fre", "$frD, $frB", IIC_FPGeneral,
1927 [(set f64:$frD, (PPCfre f64:$frB))]>;
1928 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
1929 "fres", "$frD, $frB", IIC_FPGeneral,
1930 [(set f32:$frD, (PPCfre f32:$frB))]>;
1931 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
1932 "frsqrte", "$frD, $frB", IIC_FPGeneral,
1933 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1934 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
1935 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
1936 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
1939 // XL-Form instructions. condition register logical ops.
1941 let neverHasSideEffects = 1 in
1942 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
1943 "mcrf $BF, $BFA", IIC_BrMCR>,
1944 PPC970_DGroup_First, PPC970_Unit_CRU;
1946 let isCommutable = 1 in {
1947 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
1948 (ins crbitrc:$CRA, crbitrc:$CRB),
1949 "crand $CRD, $CRA, $CRB", IIC_BrCR,
1950 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
1952 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
1953 (ins crbitrc:$CRA, crbitrc:$CRB),
1954 "crnand $CRD, $CRA, $CRB", IIC_BrCR,
1955 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
1957 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
1958 (ins crbitrc:$CRA, crbitrc:$CRB),
1959 "cror $CRD, $CRA, $CRB", IIC_BrCR,
1960 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
1962 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
1963 (ins crbitrc:$CRA, crbitrc:$CRB),
1964 "crxor $CRD, $CRA, $CRB", IIC_BrCR,
1965 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
1967 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
1968 (ins crbitrc:$CRA, crbitrc:$CRB),
1969 "crnor $CRD, $CRA, $CRB", IIC_BrCR,
1970 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
1972 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
1973 (ins crbitrc:$CRA, crbitrc:$CRB),
1974 "creqv $CRD, $CRA, $CRB", IIC_BrCR,
1975 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
1978 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
1979 (ins crbitrc:$CRA, crbitrc:$CRB),
1980 "crandc $CRD, $CRA, $CRB", IIC_BrCR,
1981 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
1983 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
1984 (ins crbitrc:$CRA, crbitrc:$CRB),
1985 "crorc $CRD, $CRA, $CRB", IIC_BrCR,
1986 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
1988 let isCodeGenOnly = 1 in {
1989 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
1990 "creqv $dst, $dst, $dst", IIC_BrCR,
1991 [(set i1:$dst, 1)]>;
1993 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
1994 "crxor $dst, $dst, $dst", IIC_BrCR,
1995 [(set i1:$dst, 0)]>;
1997 let Defs = [CR1EQ], CRD = 6 in {
1998 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1999 "creqv 6, 6, 6", IIC_BrCR,
2002 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2003 "crxor 6, 6, 6", IIC_BrCR,
2008 // XFX-Form instructions. Instructions that deal with SPRs.
2011 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2012 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2013 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2014 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2016 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2017 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>;
2019 let Uses = [CTR] in {
2020 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2021 "mfctr $rT", IIC_SprMFSPR>,
2022 PPC970_DGroup_First, PPC970_Unit_FXU;
2024 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2025 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2026 "mtctr $rS", IIC_SprMTSPR>,
2027 PPC970_DGroup_First, PPC970_Unit_FXU;
2029 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2030 let Pattern = [(int_ppc_mtctr i32:$rS)] in
2031 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2032 "mtctr $rS", IIC_SprMTSPR>,
2033 PPC970_DGroup_First, PPC970_Unit_FXU;
2036 let Defs = [LR] in {
2037 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2038 "mtlr $rS", IIC_SprMTSPR>,
2039 PPC970_DGroup_First, PPC970_Unit_FXU;
2041 let Uses = [LR] in {
2042 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2043 "mflr $rT", IIC_SprMFSPR>,
2044 PPC970_DGroup_First, PPC970_Unit_FXU;
2047 let isCodeGenOnly = 1 in {
2048 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2049 // like a GPR on the PPC970. As such, copies in and out have the same
2050 // performance characteristics as an OR instruction.
2051 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2052 "mtspr 256, $rS", IIC_IntGeneral>,
2053 PPC970_DGroup_Single, PPC970_Unit_FXU;
2054 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2055 "mfspr $rT, 256", IIC_IntGeneral>,
2056 PPC970_DGroup_First, PPC970_Unit_FXU;
2058 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2059 (outs VRSAVERC:$reg), (ins gprc:$rS),
2060 "mtspr 256, $rS", IIC_IntGeneral>,
2061 PPC970_DGroup_Single, PPC970_Unit_FXU;
2062 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2063 (ins VRSAVERC:$reg),
2064 "mfspr $rT, 256", IIC_IntGeneral>,
2065 PPC970_DGroup_First, PPC970_Unit_FXU;
2068 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2069 // so we'll need to scavenge a register for it.
2071 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2072 "#SPILL_VRSAVE", []>;
2074 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2075 // spilled), so we'll need to scavenge a register for it.
2077 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2078 "#RESTORE_VRSAVE", []>;
2080 let neverHasSideEffects = 1 in {
2081 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2082 "mtocrf $FXM, $ST", IIC_BrMCRX>,
2083 PPC970_DGroup_First, PPC970_Unit_CRU;
2085 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2086 "mtcrf $FXM, $rS", IIC_BrMCRX>,
2087 PPC970_MicroCode, PPC970_Unit_CRU;
2089 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
2090 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2091 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2092 PPC970_DGroup_First, PPC970_Unit_CRU;
2094 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2095 "mfcr $rT", IIC_SprMFCR>,
2096 PPC970_MicroCode, PPC970_Unit_CRU;
2097 } // neverHasSideEffects = 1
2099 // Pseudo instruction to perform FADD in round-to-zero mode.
2100 let usesCustomInserter = 1, Uses = [RM] in {
2101 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2102 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2105 // The above pseudo gets expanded to make use of the following instructions
2106 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
2107 let Uses = [RM], Defs = [RM] in {
2108 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2109 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2110 PPC970_DGroup_Single, PPC970_Unit_FPU;
2111 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2112 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2113 PPC970_DGroup_Single, PPC970_Unit_FPU;
2114 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2115 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2116 PPC970_DGroup_Single, PPC970_Unit_FPU;
2118 let Uses = [RM] in {
2119 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2120 "mffs $rT", IIC_IntMFFS,
2121 [(set f64:$rT, (PPCmffs))]>,
2122 PPC970_DGroup_Single, PPC970_Unit_FPU;
2126 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
2127 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2128 let isCommutable = 1 in
2129 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2130 "add", "$rT, $rA, $rB", IIC_IntSimple,
2131 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2132 let isCodeGenOnly = 1 in
2133 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2134 "add $rT, $rA, $rB", IIC_IntSimple,
2135 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2136 let isCommutable = 1 in
2137 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2138 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2139 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2140 PPC970_DGroup_Cracked;
2142 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2143 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2144 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
2145 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2146 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2147 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2148 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
2149 PPC970_DGroup_First, PPC970_DGroup_Cracked;
2150 let isCommutable = 1 in {
2151 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2152 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2153 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2154 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2155 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2156 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2157 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2158 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2159 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2161 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2162 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2163 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2164 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2165 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2166 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2167 PPC970_DGroup_Cracked;
2168 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2169 "neg", "$rT, $rA", IIC_IntSimple,
2170 [(set i32:$rT, (ineg i32:$rA))]>;
2171 let Uses = [CARRY] in {
2172 let isCommutable = 1 in
2173 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2174 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2175 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2176 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2177 "addme", "$rT, $rA", IIC_IntGeneral,
2178 [(set i32:$rT, (adde i32:$rA, -1))]>;
2179 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2180 "addze", "$rT, $rA", IIC_IntGeneral,
2181 [(set i32:$rT, (adde i32:$rA, 0))]>;
2182 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2183 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2184 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2185 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2186 "subfme", "$rT, $rA", IIC_IntGeneral,
2187 [(set i32:$rT, (sube -1, i32:$rA))]>;
2188 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2189 "subfze", "$rT, $rA", IIC_IntGeneral,
2190 [(set i32:$rT, (sube 0, i32:$rA))]>;
2194 // A-Form instructions. Most of the instructions executed in the FPU are of
2197 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
2198 let Uses = [RM] in {
2199 let isCommutable = 1 in {
2200 defm FMADD : AForm_1r<63, 29,
2201 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2202 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2203 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2204 defm FMADDS : AForm_1r<59, 29,
2205 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2206 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2207 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2208 defm FMSUB : AForm_1r<63, 28,
2209 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2210 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2212 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2213 defm FMSUBS : AForm_1r<59, 28,
2214 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2215 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2217 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2218 defm FNMADD : AForm_1r<63, 31,
2219 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2220 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2222 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2223 defm FNMADDS : AForm_1r<59, 31,
2224 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2225 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2227 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2228 defm FNMSUB : AForm_1r<63, 30,
2229 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2230 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2231 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2232 (fneg f64:$FRB))))]>;
2233 defm FNMSUBS : AForm_1r<59, 30,
2234 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2235 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2236 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2237 (fneg f32:$FRB))))]>;
2240 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2241 // having 4 of these, force the comparison to always be an 8-byte double (code
2242 // should use an FMRSD if the input comparison value really wants to be a float)
2243 // and 4/8 byte forms for the result and operand type..
2244 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2245 defm FSELD : AForm_1r<63, 23,
2246 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2247 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2248 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2249 defm FSELS : AForm_1r<63, 23,
2250 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2251 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2252 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2253 let Uses = [RM] in {
2254 let isCommutable = 1 in {
2255 defm FADD : AForm_2r<63, 21,
2256 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2257 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2258 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2259 defm FADDS : AForm_2r<59, 21,
2260 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2261 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2262 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2264 defm FDIV : AForm_2r<63, 18,
2265 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2266 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2267 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2268 defm FDIVS : AForm_2r<59, 18,
2269 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2270 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2271 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2272 let isCommutable = 1 in {
2273 defm FMUL : AForm_3r<63, 25,
2274 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2275 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2276 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2277 defm FMULS : AForm_3r<59, 25,
2278 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2279 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2280 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2282 defm FSUB : AForm_2r<63, 20,
2283 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2284 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2285 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2286 defm FSUBS : AForm_2r<59, 20,
2287 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2288 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2289 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2293 let neverHasSideEffects = 1 in {
2294 let PPC970_Unit = 1 in { // FXU Operations.
2296 def ISEL : AForm_4<31, 15,
2297 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2298 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
2302 let PPC970_Unit = 1 in { // FXU Operations.
2303 // M-Form instructions. rotate and mask instructions.
2305 let isCommutable = 1 in {
2306 // RLWIMI can be commuted if the rotate amount is zero.
2307 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2308 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2309 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2310 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2311 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2313 let BaseName = "rlwinm" in {
2314 def RLWINM : MForm_2<21,
2315 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2316 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2319 def RLWINMo : MForm_2<21,
2320 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2321 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2322 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2324 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2325 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2326 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2329 } // neverHasSideEffects = 1
2331 //===----------------------------------------------------------------------===//
2332 // PowerPC Instruction Patterns
2335 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2336 def : Pat<(i32 imm:$imm),
2337 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2339 // Implement the 'not' operation with the NOR instruction.
2340 def i32not : OutPatFrag<(ops node:$in),
2342 def : Pat<(not i32:$in),
2345 // ADD an arbitrary immediate.
2346 def : Pat<(add i32:$in, imm:$imm),
2347 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2348 // OR an arbitrary immediate.
2349 def : Pat<(or i32:$in, imm:$imm),
2350 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2351 // XOR an arbitrary immediate.
2352 def : Pat<(xor i32:$in, imm:$imm),
2353 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2355 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2356 (SUBFIC $in, imm:$imm)>;
2359 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2360 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2361 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2362 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2365 def : Pat<(rotl i32:$in, i32:$sh),
2366 (RLWNM $in, $sh, 0, 31)>;
2367 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2368 (RLWINM $in, imm:$imm, 0, 31)>;
2371 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2372 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2375 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2376 (BL tglobaladdr:$dst)>;
2377 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2378 (BL texternalsym:$dst)>;
2381 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2382 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2384 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2385 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2387 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2388 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2392 // Hi and Lo for Darwin Global Addresses.
2393 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2394 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2395 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2396 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2397 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2398 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2399 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2400 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2401 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2402 (ADDIS $in, tglobaltlsaddr:$g)>;
2403 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2404 (ADDI $in, tglobaltlsaddr:$g)>;
2405 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2406 (ADDIS $in, tglobaladdr:$g)>;
2407 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2408 (ADDIS $in, tconstpool:$g)>;
2409 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2410 (ADDIS $in, tjumptable:$g)>;
2411 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2412 (ADDIS $in, tblockaddress:$g)>;
2414 // Support for thread-local storage.
2415 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2416 [(set i32:$rD, (PPCppc32GOT))]>;
2418 // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2419 // This uses two output registers, the first as the real output, the second as a
2420 // temporary register, used internally in code generation.
2421 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2422 []>, NoEncode<"$rT">;
2424 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2427 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2428 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2429 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2431 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2434 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2435 def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2438 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2439 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2442 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2443 def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2446 (PPCgetTlsldAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2447 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2450 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2451 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2454 (PPCaddisDtprelHA i32:$reg,
2455 tglobaltlsaddr:$disp))]>;
2457 // Support for Position-independent code
2458 def LWZtoc: Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2461 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2462 // Get Global (GOT) Base Register offset, from the word immediately preceding
2463 // the function label.
2464 def GetGBRO: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#GetGBRO", []>;
2465 // Update the Global(GOT) Base Register with the above offset.
2466 def UpdateGBR: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2469 // Standard shifts. These are represented separately from the real shifts above
2470 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2472 def : Pat<(sra i32:$rS, i32:$rB),
2474 def : Pat<(srl i32:$rS, i32:$rB),
2476 def : Pat<(shl i32:$rS, i32:$rB),
2479 def : Pat<(zextloadi1 iaddr:$src),
2481 def : Pat<(zextloadi1 xaddr:$src),
2483 def : Pat<(extloadi1 iaddr:$src),
2485 def : Pat<(extloadi1 xaddr:$src),
2487 def : Pat<(extloadi8 iaddr:$src),
2489 def : Pat<(extloadi8 xaddr:$src),
2491 def : Pat<(extloadi16 iaddr:$src),
2493 def : Pat<(extloadi16 xaddr:$src),
2495 def : Pat<(f64 (extloadf32 iaddr:$src)),
2496 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2497 def : Pat<(f64 (extloadf32 xaddr:$src)),
2498 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2500 def : Pat<(f64 (fextend f32:$src)),
2501 (COPY_TO_REGCLASS $src, F8RC)>;
2503 def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>, Requires<[IsNotBookE]>;
2504 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[IsBookE]>;
2506 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2507 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2508 (FNMSUB $A, $C, $B)>;
2509 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2510 (FNMSUB $A, $C, $B)>;
2511 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2512 (FNMSUBS $A, $C, $B)>;
2513 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2514 (FNMSUBS $A, $C, $B)>;
2516 // FCOPYSIGN's operand types need not agree.
2517 def : Pat<(fcopysign f64:$frB, f32:$frA),
2518 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2519 def : Pat<(fcopysign f32:$frB, f64:$frA),
2520 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2522 include "PPCInstrAltivec.td"
2523 include "PPCInstr64Bit.td"
2524 include "PPCInstrVSX.td"
2526 def crnot : OutPatFrag<(ops node:$in),
2528 def : Pat<(not i1:$in),
2531 // Patterns for arithmetic i1 operations.
2532 def : Pat<(add i1:$a, i1:$b),
2534 def : Pat<(sub i1:$a, i1:$b),
2536 def : Pat<(mul i1:$a, i1:$b),
2539 // We're sometimes asked to materialize i1 -1, which is just 1 in this case
2540 // (-1 is used to mean all bits set).
2541 def : Pat<(i1 -1), (CRSET)>;
2543 // i1 extensions, implemented in terms of isel.
2544 def : Pat<(i32 (zext i1:$in)),
2545 (SELECT_I4 $in, (LI 1), (LI 0))>;
2546 def : Pat<(i32 (sext i1:$in)),
2547 (SELECT_I4 $in, (LI -1), (LI 0))>;
2549 def : Pat<(i64 (zext i1:$in)),
2550 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2551 def : Pat<(i64 (sext i1:$in)),
2552 (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2554 // FIXME: We should choose either a zext or a sext based on other constants
2556 def : Pat<(i32 (anyext i1:$in)),
2557 (SELECT_I4 $in, (LI 1), (LI 0))>;
2558 def : Pat<(i64 (anyext i1:$in)),
2559 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2561 // match setcc on i1 variables.
2562 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2564 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2566 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2568 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2570 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2572 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2574 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2576 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2578 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2580 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2583 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
2584 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2585 // floating-point types.
2587 multiclass CRNotPat<dag pattern, dag result> {
2588 def : Pat<pattern, (crnot result)>;
2589 def : Pat<(not pattern), result>;
2591 // We can also fold the crnot into an extension:
2592 def : Pat<(i32 (zext pattern)),
2593 (SELECT_I4 result, (LI 0), (LI 1))>;
2594 def : Pat<(i32 (sext pattern)),
2595 (SELECT_I4 result, (LI 0), (LI -1))>;
2597 // We can also fold the crnot into an extension:
2598 def : Pat<(i64 (zext pattern)),
2599 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2600 def : Pat<(i64 (sext pattern)),
2601 (SELECT_I8 result, (LI8 0), (LI8 -1))>;
2603 // FIXME: We should choose either a zext or a sext based on other constants
2605 def : Pat<(i32 (anyext pattern)),
2606 (SELECT_I4 result, (LI 0), (LI 1))>;
2608 def : Pat<(i64 (anyext pattern)),
2609 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2612 // FIXME: Because of what seems like a bug in TableGen's type-inference code,
2613 // we need to write imm:$imm in the output patterns below, not just $imm, or
2614 // else the resulting matcher will not correctly add the immediate operand
2615 // (making it a register operand instead).
2618 multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
2619 OutPatFrag rfrag, OutPatFrag rfrag8> {
2620 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
2622 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
2624 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
2625 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2626 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
2627 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2629 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
2631 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
2633 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
2634 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2635 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
2636 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2639 // Note that we do all inversions below with i(32|64)not, instead of using
2640 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
2641 // has 2-cycle latency.
2643 defm : ExtSetCCPat<SETEQ,
2644 PatFrag<(ops node:$in, node:$cc),
2645 (setcc $in, 0, $cc)>,
2646 OutPatFrag<(ops node:$in),
2647 (RLWINM (CNTLZW $in), 27, 31, 31)>,
2648 OutPatFrag<(ops node:$in),
2649 (RLDICL (CNTLZD $in), 58, 63)> >;
2651 defm : ExtSetCCPat<SETNE,
2652 PatFrag<(ops node:$in, node:$cc),
2653 (setcc $in, 0, $cc)>,
2654 OutPatFrag<(ops node:$in),
2655 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
2656 OutPatFrag<(ops node:$in),
2657 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
2659 defm : ExtSetCCPat<SETLT,
2660 PatFrag<(ops node:$in, node:$cc),
2661 (setcc $in, 0, $cc)>,
2662 OutPatFrag<(ops node:$in),
2663 (RLWINM $in, 1, 31, 31)>,
2664 OutPatFrag<(ops node:$in),
2665 (RLDICL $in, 1, 63)> >;
2667 defm : ExtSetCCPat<SETGE,
2668 PatFrag<(ops node:$in, node:$cc),
2669 (setcc $in, 0, $cc)>,
2670 OutPatFrag<(ops node:$in),
2671 (RLWINM (i32not $in), 1, 31, 31)>,
2672 OutPatFrag<(ops node:$in),
2673 (RLDICL (i64not $in), 1, 63)> >;
2675 defm : ExtSetCCPat<SETGT,
2676 PatFrag<(ops node:$in, node:$cc),
2677 (setcc $in, 0, $cc)>,
2678 OutPatFrag<(ops node:$in),
2679 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
2680 OutPatFrag<(ops node:$in),
2681 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
2683 defm : ExtSetCCPat<SETLE,
2684 PatFrag<(ops node:$in, node:$cc),
2685 (setcc $in, 0, $cc)>,
2686 OutPatFrag<(ops node:$in),
2687 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
2688 OutPatFrag<(ops node:$in),
2689 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
2691 defm : ExtSetCCPat<SETLT,
2692 PatFrag<(ops node:$in, node:$cc),
2693 (setcc $in, -1, $cc)>,
2694 OutPatFrag<(ops node:$in),
2695 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
2696 OutPatFrag<(ops node:$in),
2697 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2699 defm : ExtSetCCPat<SETGE,
2700 PatFrag<(ops node:$in, node:$cc),
2701 (setcc $in, -1, $cc)>,
2702 OutPatFrag<(ops node:$in),
2703 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
2704 OutPatFrag<(ops node:$in),
2705 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2707 defm : ExtSetCCPat<SETGT,
2708 PatFrag<(ops node:$in, node:$cc),
2709 (setcc $in, -1, $cc)>,
2710 OutPatFrag<(ops node:$in),
2711 (RLWINM (i32not $in), 1, 31, 31)>,
2712 OutPatFrag<(ops node:$in),
2713 (RLDICL (i64not $in), 1, 63)> >;
2715 defm : ExtSetCCPat<SETLE,
2716 PatFrag<(ops node:$in, node:$cc),
2717 (setcc $in, -1, $cc)>,
2718 OutPatFrag<(ops node:$in),
2719 (RLWINM $in, 1, 31, 31)>,
2720 OutPatFrag<(ops node:$in),
2721 (RLDICL $in, 1, 63)> >;
2724 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
2725 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2726 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
2727 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2728 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
2729 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2730 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
2731 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2732 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
2733 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2734 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
2735 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2737 // For non-equality comparisons, the default code would materialize the
2738 // constant, then compare against it, like this:
2740 // ori r2, r2, 22136
2743 // Since we are just comparing for equality, we can emit this instead:
2744 // xoris r0,r3,0x1234
2745 // cmplwi cr0,r0,0x5678
2748 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
2749 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2750 (LO16 imm:$imm)), sub_eq)>;
2752 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
2753 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2754 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
2755 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2756 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
2757 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2758 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
2759 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2760 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
2761 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2762 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
2763 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2765 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
2766 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2767 (LO16 imm:$imm)), sub_eq)>;
2769 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
2770 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2771 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
2772 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2773 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
2774 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2775 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
2776 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2777 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
2778 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2780 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
2781 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
2782 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
2783 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
2784 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
2785 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
2786 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
2787 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
2788 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
2789 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
2792 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
2793 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2794 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
2795 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2796 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
2797 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2798 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
2799 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2800 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
2801 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2802 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
2803 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2805 // For non-equality comparisons, the default code would materialize the
2806 // constant, then compare against it, like this:
2808 // ori r2, r2, 22136
2811 // Since we are just comparing for equality, we can emit this instead:
2812 // xoris r0,r3,0x1234
2813 // cmpldi cr0,r0,0x5678
2816 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
2817 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2818 (LO16 imm:$imm)), sub_eq)>;
2820 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
2821 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
2822 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
2823 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
2824 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
2825 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
2826 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
2827 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
2828 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
2829 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
2830 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
2831 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
2833 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
2834 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2835 (LO16 imm:$imm)), sub_eq)>;
2837 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
2838 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2839 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
2840 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2841 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
2842 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2843 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
2844 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2845 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
2846 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2848 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
2849 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
2850 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
2851 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
2852 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
2853 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
2854 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
2855 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
2856 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
2857 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
2860 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
2861 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2862 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
2863 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2864 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
2865 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2866 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
2867 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2868 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
2869 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2870 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
2871 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2872 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
2873 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2875 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
2876 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2877 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
2878 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
2879 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
2880 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2881 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
2882 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
2883 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
2884 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2885 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
2886 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
2887 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
2888 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
2891 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
2892 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2893 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
2894 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2895 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
2896 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2897 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
2898 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2899 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
2900 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2901 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
2902 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2903 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
2904 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
2906 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
2907 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2908 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
2909 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
2910 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
2911 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2912 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
2913 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
2914 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
2915 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2916 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
2917 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
2918 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
2919 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
2921 // match select on i1 variables:
2922 def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
2923 (CROR (CRAND $cond , $tval),
2924 (CRAND (crnot $cond), $fval))>;
2926 // match selectcc on i1 variables:
2927 // select (lhs == rhs), tval, fval is:
2928 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
2929 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
2930 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
2931 (CRAND (CRORC $lhs, $rhs), $fval))>;
2932 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
2933 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
2934 (CRAND (CRANDC $lhs, $rhs), $fval))>;
2935 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
2936 (CROR (CRAND (CREQV $lhs, $rhs), $tval),
2937 (CRAND (CRXOR $lhs, $rhs), $fval))>;
2938 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
2939 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
2940 (CRAND (CRANDC $rhs, $lhs), $fval))>;
2941 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
2942 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
2943 (CRAND (CRORC $rhs, $lhs), $fval))>;
2944 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
2945 (CROR (CRAND (CREQV $lhs, $rhs), $fval),
2946 (CRAND (CRXOR $lhs, $rhs), $tval))>;
2948 // match selectcc on i1 variables with non-i1 output.
2949 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
2950 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
2951 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
2952 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
2953 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
2954 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
2955 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
2956 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
2957 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
2958 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
2959 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
2960 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
2962 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
2963 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
2964 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
2965 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
2966 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
2967 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
2968 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
2969 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
2970 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
2971 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
2972 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
2973 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
2975 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
2976 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
2977 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
2978 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
2979 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
2980 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
2981 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
2982 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
2983 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
2984 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
2985 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
2986 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
2988 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
2989 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
2990 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
2991 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
2992 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
2993 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
2994 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
2995 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
2996 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
2997 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
2998 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
2999 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3001 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3002 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3003 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3004 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3005 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3006 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3007 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3008 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3009 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3010 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3011 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3012 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3014 let usesCustomInserter = 1 in {
3015 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3017 [(set i1:$dst, (trunc (not i32:$in)))]>;
3018 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3020 [(set i1:$dst, (trunc i32:$in))]>;
3022 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3024 [(set i1:$dst, (trunc (not i64:$in)))]>;
3025 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3027 [(set i1:$dst, (trunc i64:$in))]>;
3030 def : Pat<(i1 (not (trunc i32:$in))),
3031 (ANDIo_1_EQ_BIT $in)>;
3032 def : Pat<(i1 (not (trunc i64:$in))),
3033 (ANDIo_1_EQ_BIT8 $in)>;
3035 //===----------------------------------------------------------------------===//
3036 // PowerPC Instructions used for assembler/disassembler only
3039 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3040 "isync", IIC_SprISYNC, []>;
3042 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3043 "icbi $src", IIC_LdStICBI, []>;
3045 def EIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3046 "eieio", IIC_LdStLoad, []>;
3048 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3049 "wait $L", IIC_LdStLoad, []>;
3051 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3052 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3054 def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3055 "mtsr $SR, $RS", IIC_SprMTSR>;
3057 def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3058 "mfsr $RS, $SR", IIC_SprMFSR>;
3060 def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3061 "mtsrin $RS, $RB", IIC_SprMTSR>;
3063 def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3064 "mfsrin $RS, $RB", IIC_SprMFSR>;
3066 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3067 "mtmsr $RS, $L", IIC_SprMTMSR>;
3069 def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3070 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3074 def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3075 Requires<[IsBookE]> {
3079 let Inst{21-30} = 163;
3082 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3083 "mfmsr $RT", IIC_SprMFMSR, []>;
3085 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3086 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3088 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3089 "slbie $RB", IIC_SprSLBIE, []>;
3091 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3092 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3094 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3095 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3097 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3099 def TLBIA : XForm_0<31, 370, (outs), (ins),
3100 "tlbia", IIC_SprTLBIA, []>;
3102 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3103 "tlbsync", IIC_SprTLBSYNC, []>;
3105 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3106 "tlbiel $RB", IIC_SprTLBIEL, []>;
3108 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3109 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3111 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3112 IIC_LdStLoad>, Requires<[IsBookE]>;
3114 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3115 IIC_LdStLoad>, Requires<[IsBookE]>;
3117 def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3118 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3120 def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3121 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3123 def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_BrB, []>,
3124 Requires<[IsBookE]>;
3125 def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3126 Requires<[IsBookE]>;
3128 def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3130 def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3133 def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3134 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3135 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3136 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3138 //===----------------------------------------------------------------------===//
3139 // PowerPC Assembler Instruction Aliases
3142 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
3143 // These are aliases that require C++ handling to convert to the target
3144 // instruction, while InstAliases can be handled directly by tblgen.
3145 class PPCAsmPseudo<string asm, dag iops>
3147 let Namespace = "PPC";
3148 bit PPC64 = 0; // Default value, override with isPPC64
3150 let OutOperandList = (outs);
3151 let InOperandList = iops;
3153 let AsmString = asm;
3154 let isAsmParserOnly = 1;
3158 def : InstAlias<"sc", (SC 0)>;
3160 def : InstAlias<"sync", (SYNC 0)>, Requires<[IsNotBookE]>;
3161 def : InstAlias<"msync", (SYNC 0)>, Requires<[IsNotBookE]>;
3162 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[IsNotBookE]>;
3163 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[IsNotBookE]>;
3165 def : InstAlias<"wait", (WAIT 0)>;
3166 def : InstAlias<"waitrsv", (WAIT 1)>;
3167 def : InstAlias<"waitimpl", (WAIT 2)>;
3169 def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3171 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3172 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3173 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3174 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3176 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3177 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3179 def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3180 def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3182 def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3183 def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3185 def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3186 def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3188 def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3189 def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3191 def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3192 def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3194 def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3195 def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3197 def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3198 def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3200 def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3201 def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3203 def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3204 def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3206 def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3207 def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3209 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3210 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3212 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3214 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3215 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3217 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3218 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3220 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3222 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3224 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3225 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3226 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3227 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3228 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3229 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3230 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3231 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3233 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3234 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3235 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3236 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3238 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3239 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3241 def : InstAlias<"mfsprg $RT, 0", (MFSPR gprc:$RT, 272)>;
3242 def : InstAlias<"mfsprg $RT, 1", (MFSPR gprc:$RT, 273)>;
3243 def : InstAlias<"mfsprg $RT, 2", (MFSPR gprc:$RT, 274)>;
3244 def : InstAlias<"mfsprg $RT, 3", (MFSPR gprc:$RT, 275)>;
3245 def : InstAlias<"mfsprg $RT, 4", (MFSPR gprc:$RT, 260)>, Requires<[IsBookE]>;
3246 def : InstAlias<"mfsprg $RT, 5", (MFSPR gprc:$RT, 261)>, Requires<[IsBookE]>;
3247 def : InstAlias<"mfsprg $RT, 6", (MFSPR gprc:$RT, 262)>, Requires<[IsBookE]>;
3248 def : InstAlias<"mfsprg $RT, 7", (MFSPR gprc:$RT, 263)>, Requires<[IsBookE]>;
3250 def : InstAlias<"mfsprg0 $RT", (MFSPR gprc:$RT, 272)>;
3251 def : InstAlias<"mfsprg1 $RT", (MFSPR gprc:$RT, 273)>;
3252 def : InstAlias<"mfsprg2 $RT", (MFSPR gprc:$RT, 274)>;
3253 def : InstAlias<"mfsprg3 $RT", (MFSPR gprc:$RT, 275)>;
3254 def : InstAlias<"mfsprg4 $RT", (MFSPR gprc:$RT, 260)>, Requires<[IsBookE]>;
3255 def : InstAlias<"mfsprg5 $RT", (MFSPR gprc:$RT, 261)>, Requires<[IsBookE]>;
3256 def : InstAlias<"mfsprg6 $RT", (MFSPR gprc:$RT, 262)>, Requires<[IsBookE]>;
3257 def : InstAlias<"mfsprg7 $RT", (MFSPR gprc:$RT, 263)>, Requires<[IsBookE]>;
3259 def : InstAlias<"mtsprg 0, $RT", (MTSPR 272, gprc:$RT)>;
3260 def : InstAlias<"mtsprg 1, $RT", (MTSPR 273, gprc:$RT)>;
3261 def : InstAlias<"mtsprg 2, $RT", (MTSPR 274, gprc:$RT)>;
3262 def : InstAlias<"mtsprg 3, $RT", (MTSPR 275, gprc:$RT)>;
3263 def : InstAlias<"mtsprg 4, $RT", (MTSPR 260, gprc:$RT)>, Requires<[IsBookE]>;
3264 def : InstAlias<"mtsprg 5, $RT", (MTSPR 261, gprc:$RT)>, Requires<[IsBookE]>;
3265 def : InstAlias<"mtsprg 6, $RT", (MTSPR 262, gprc:$RT)>, Requires<[IsBookE]>;
3266 def : InstAlias<"mtsprg 7, $RT", (MTSPR 263, gprc:$RT)>, Requires<[IsBookE]>;
3268 def : InstAlias<"mtsprg0 $RT", (MTSPR 272, gprc:$RT)>;
3269 def : InstAlias<"mtsprg1 $RT", (MTSPR 273, gprc:$RT)>;
3270 def : InstAlias<"mtsprg2 $RT", (MTSPR 274, gprc:$RT)>;
3271 def : InstAlias<"mtsprg3 $RT", (MTSPR 275, gprc:$RT)>;
3272 def : InstAlias<"mtsprg4 $RT", (MTSPR 260, gprc:$RT)>, Requires<[IsBookE]>;
3273 def : InstAlias<"mtsprg5 $RT", (MTSPR 261, gprc:$RT)>, Requires<[IsBookE]>;
3274 def : InstAlias<"mtsprg6 $RT", (MTSPR 262, gprc:$RT)>, Requires<[IsBookE]>;
3275 def : InstAlias<"mtsprg7 $RT", (MTSPR 263, gprc:$RT)>, Requires<[IsBookE]>;
3277 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3279 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3280 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3282 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3284 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3285 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3287 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3288 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3289 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3290 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3292 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3294 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3295 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3296 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3297 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3298 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3299 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3300 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3301 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3302 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3303 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3304 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3305 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3306 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3307 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3308 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3309 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3310 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3311 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3312 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3313 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3314 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3315 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3316 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3317 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3318 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3319 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3320 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3321 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3322 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3323 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3324 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3325 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3326 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3327 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3328 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3329 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3331 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3332 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3333 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3334 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3335 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3336 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3338 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3339 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3340 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3341 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3342 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3343 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3344 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3345 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3346 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3347 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3348 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3349 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3350 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3351 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3352 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3353 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3354 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3355 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3356 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3357 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3358 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3359 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3360 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3361 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3362 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
3363 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3364 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
3365 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3366 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
3367 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3368 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
3369 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3371 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3372 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3373 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3374 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3375 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3376 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3378 // These generic branch instruction forms are used for the assembler parser only.
3379 // Defs and Uses are conservative, since we don't know the BO value.
3380 let PPC970_Unit = 7 in {
3381 let Defs = [CTR], Uses = [CTR, RM] in {
3382 def gBC : BForm_3<16, 0, 0, (outs),
3383 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3384 "bc $bo, $bi, $dst">;
3385 def gBCA : BForm_3<16, 1, 0, (outs),
3386 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3387 "bca $bo, $bi, $dst">;
3389 let Defs = [LR, CTR], Uses = [CTR, RM] in {
3390 def gBCL : BForm_3<16, 0, 1, (outs),
3391 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3392 "bcl $bo, $bi, $dst">;
3393 def gBCLA : BForm_3<16, 1, 1, (outs),
3394 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3395 "bcla $bo, $bi, $dst">;
3397 let Defs = [CTR], Uses = [CTR, LR, RM] in
3398 def gBCLR : XLForm_2<19, 16, 0, (outs),
3399 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3400 "bclr $bo, $bi, $bh", IIC_BrB, []>;
3401 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3402 def gBCLRL : XLForm_2<19, 16, 1, (outs),
3403 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3404 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
3405 let Defs = [CTR], Uses = [CTR, LR, RM] in
3406 def gBCCTR : XLForm_2<19, 528, 0, (outs),
3407 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3408 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
3409 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3410 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
3411 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3412 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
3414 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
3415 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
3416 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
3417 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
3419 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
3420 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
3421 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3422 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
3423 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
3424 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3425 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
3427 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
3428 : BranchSimpleMnemonic1<name, pm, bo> {
3429 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
3430 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
3432 defm : BranchSimpleMnemonic2<"t", "", 12>;
3433 defm : BranchSimpleMnemonic2<"f", "", 4>;
3434 defm : BranchSimpleMnemonic2<"t", "-", 14>;
3435 defm : BranchSimpleMnemonic2<"f", "-", 6>;
3436 defm : BranchSimpleMnemonic2<"t", "+", 15>;
3437 defm : BranchSimpleMnemonic2<"f", "+", 7>;
3438 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
3439 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
3440 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
3441 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
3443 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
3444 def : InstAlias<"b"#name#pm#" $cc, $dst",
3445 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
3446 def : InstAlias<"b"#name#pm#" $dst",
3447 (BCC bibo, CR0, condbrtarget:$dst)>;
3449 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
3450 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3451 def : InstAlias<"b"#name#"a"#pm#" $dst",
3452 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
3454 def : InstAlias<"b"#name#"lr"#pm#" $cc",
3455 (BCCLR bibo, crrc:$cc)>;
3456 def : InstAlias<"b"#name#"lr"#pm,
3459 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
3460 (BCCCTR bibo, crrc:$cc)>;
3461 def : InstAlias<"b"#name#"ctr"#pm,
3462 (BCCCTR bibo, CR0)>;
3464 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
3465 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
3466 def : InstAlias<"b"#name#"l"#pm#" $dst",
3467 (BCCL bibo, CR0, condbrtarget:$dst)>;
3469 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
3470 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3471 def : InstAlias<"b"#name#"la"#pm#" $dst",
3472 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
3474 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
3475 (BCCLRL bibo, crrc:$cc)>;
3476 def : InstAlias<"b"#name#"lrl"#pm,
3477 (BCCLRL bibo, CR0)>;
3479 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
3480 (BCCCTRL bibo, crrc:$cc)>;
3481 def : InstAlias<"b"#name#"ctrl"#pm,
3482 (BCCCTRL bibo, CR0)>;
3484 multiclass BranchExtendedMnemonic<string name, int bibo> {
3485 defm : BranchExtendedMnemonicPM<name, "", bibo>;
3486 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
3487 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
3489 defm : BranchExtendedMnemonic<"lt", 12>;
3490 defm : BranchExtendedMnemonic<"gt", 44>;
3491 defm : BranchExtendedMnemonic<"eq", 76>;
3492 defm : BranchExtendedMnemonic<"un", 108>;
3493 defm : BranchExtendedMnemonic<"so", 108>;
3494 defm : BranchExtendedMnemonic<"ge", 4>;
3495 defm : BranchExtendedMnemonic<"nl", 4>;
3496 defm : BranchExtendedMnemonic<"le", 36>;
3497 defm : BranchExtendedMnemonic<"ng", 36>;
3498 defm : BranchExtendedMnemonic<"ne", 68>;
3499 defm : BranchExtendedMnemonic<"nu", 100>;
3500 defm : BranchExtendedMnemonic<"ns", 100>;
3502 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
3503 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
3504 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
3505 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
3506 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
3507 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
3508 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
3509 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
3511 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
3512 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
3513 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
3514 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
3515 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
3516 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3517 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
3518 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3520 multiclass TrapExtendedMnemonic<string name, int to> {
3521 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
3522 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
3523 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
3524 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
3526 defm : TrapExtendedMnemonic<"lt", 16>;
3527 defm : TrapExtendedMnemonic<"le", 20>;
3528 defm : TrapExtendedMnemonic<"eq", 4>;
3529 defm : TrapExtendedMnemonic<"ge", 12>;
3530 defm : TrapExtendedMnemonic<"gt", 8>;
3531 defm : TrapExtendedMnemonic<"nl", 12>;
3532 defm : TrapExtendedMnemonic<"ne", 24>;
3533 defm : TrapExtendedMnemonic<"ng", 20>;
3534 defm : TrapExtendedMnemonic<"llt", 2>;
3535 defm : TrapExtendedMnemonic<"lle", 6>;
3536 defm : TrapExtendedMnemonic<"lge", 5>;
3537 defm : TrapExtendedMnemonic<"lgt", 1>;
3538 defm : TrapExtendedMnemonic<"lnl", 5>;
3539 defm : TrapExtendedMnemonic<"lng", 6>;
3540 defm : TrapExtendedMnemonic<"u", 31>;