1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
26 def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
38 def SDT_PPClbrx : SDTypeProfile<1, 2, [
39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
41 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPClarx : SDTypeProfile<1, 1, [
46 SDTCisInt<0>, SDTCisPtrTy<1>
48 def SDT_PPCstcx : SDTypeProfile<0, 2, [
49 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
53 SDTCisPtrTy<0>, SDTCisVT<1, i32>
56 def SDT_PPCnop : SDTypeProfile<0, 0, []>;
58 //===----------------------------------------------------------------------===//
59 // PowerPC specific DAG Nodes.
62 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
63 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
64 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
65 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
66 [SDNPHasChain, SDNPMayStore]>;
68 // This sequence is used for long double->int conversions. It changes the
69 // bits in the FPSCR which is not modelled.
70 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
72 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
73 [SDNPInGlue, SDNPOutGlue]>;
74 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
75 [SDNPInGlue, SDNPOutGlue]>;
76 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
77 [SDNPInGlue, SDNPOutGlue]>;
78 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
79 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
83 def PPCfsel : SDNode<"PPCISD::FSEL",
84 // Type constraint for fsel.
85 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
86 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
88 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
89 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
90 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
91 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
92 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
94 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
96 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
97 // amounts. These nodes are generated by the multi-precision shift code.
98 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
99 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
100 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
102 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
103 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
104 [SDNPHasChain, SDNPMayStore]>;
106 // These are target-independent nodes, but have target-specific formats.
107 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
108 [SDNPHasChain, SDNPOutGlue]>;
109 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
110 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
112 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
113 def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall,
114 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
116 def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall,
117 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 def PPCcall_nop_SVR4 : SDNode<"PPCISD::CALL_NOP_SVR4", SDT_PPCCall,
120 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
122 def PPCnop : SDNode<"PPCISD::NOP", SDT_PPCnop, [SDNPInGlue, SDNPOutGlue]>;
123 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
124 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
125 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
126 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
127 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
128 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
129 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
130 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
131 def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone,
132 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
135 def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone,
136 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
139 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
140 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
142 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
143 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
145 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
146 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
148 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
149 [SDNPHasChain, SDNPOptInGlue]>;
151 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
152 [SDNPHasChain, SDNPMayLoad]>;
153 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
154 [SDNPHasChain, SDNPMayStore]>;
156 // Instructions to support atomic operations
157 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
158 [SDNPHasChain, SDNPMayLoad]>;
159 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
160 [SDNPHasChain, SDNPMayStore]>;
162 // Instructions to support dynamic alloca.
163 def SDTDynOp : SDTypeProfile<1, 2, []>;
164 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
166 //===----------------------------------------------------------------------===//
167 // PowerPC specific transformation functions and pattern fragments.
170 def SHL32 : SDNodeXForm<imm, [{
171 // Transformation function: 31 - imm
172 return getI32Imm(31 - N->getZExtValue());
175 def SRL32 : SDNodeXForm<imm, [{
176 // Transformation function: 32 - imm
177 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
180 def LO16 : SDNodeXForm<imm, [{
181 // Transformation function: get the low 16 bits.
182 return getI32Imm((unsigned short)N->getZExtValue());
185 def HI16 : SDNodeXForm<imm, [{
186 // Transformation function: shift the immediate value down into the low bits.
187 return getI32Imm((unsigned)N->getZExtValue() >> 16);
190 def HA16 : SDNodeXForm<imm, [{
191 // Transformation function: shift the immediate value down into the low bits.
192 signed int Val = N->getZExtValue();
193 return getI32Imm((Val - (signed short)Val) >> 16);
195 def MB : SDNodeXForm<imm, [{
196 // Transformation function: get the start bit of a mask
198 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
199 return getI32Imm(mb);
202 def ME : SDNodeXForm<imm, [{
203 // Transformation function: get the end bit of a mask
205 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
206 return getI32Imm(me);
208 def maskimm32 : PatLeaf<(imm), [{
209 // maskImm predicate - True if immediate is a run of ones.
211 if (N->getValueType(0) == MVT::i32)
212 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
217 def immSExt16 : PatLeaf<(imm), [{
218 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
219 // field. Used by instructions like 'addi'.
220 if (N->getValueType(0) == MVT::i32)
221 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
223 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
225 def immZExt16 : PatLeaf<(imm), [{
226 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
227 // field. Used by instructions like 'ori'.
228 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
231 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
232 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
233 // identical in 32-bit mode, but in 64-bit mode, they return true if the
234 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
236 def imm16ShiftedZExt : PatLeaf<(imm), [{
237 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
238 // immediate are set. Used by instructions like 'xoris'.
239 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
242 def imm16ShiftedSExt : PatLeaf<(imm), [{
243 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
244 // immediate are set. Used by instructions like 'addis'. Identical to
245 // imm16ShiftedZExt in 32-bit mode.
246 if (N->getZExtValue() & 0xFFFF) return false;
247 if (N->getValueType(0) == MVT::i32)
249 // For 64-bit, make sure it is sext right.
250 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
254 //===----------------------------------------------------------------------===//
255 // PowerPC Flag Definitions.
257 class isPPC64 { bit PPC64 = 1; }
259 list<Register> Defs = [CR0];
263 class RegConstraint<string C> {
264 string Constraints = C;
266 class NoEncode<string E> {
267 string DisableEncoding = E;
271 //===----------------------------------------------------------------------===//
272 // PowerPC Operand Definitions.
274 def s5imm : Operand<i32> {
275 let PrintMethod = "printS5ImmOperand";
277 def u5imm : Operand<i32> {
278 let PrintMethod = "printU5ImmOperand";
280 def u6imm : Operand<i32> {
281 let PrintMethod = "printU6ImmOperand";
283 def s16imm : Operand<i32> {
284 let PrintMethod = "printS16ImmOperand";
286 def u16imm : Operand<i32> {
287 let PrintMethod = "printU16ImmOperand";
289 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
290 let PrintMethod = "printS16X4ImmOperand";
292 def directbrtarget : Operand<OtherVT> {
293 let PrintMethod = "printBranchOperand";
294 let EncoderMethod = "getDirectBrEncoding";
296 def condbrtarget : Operand<OtherVT> {
297 let PrintMethod = "printBranchOperand";
298 let EncoderMethod = "getCondBrEncoding";
300 def calltarget : Operand<iPTR> {
301 let EncoderMethod = "getDirectBrEncoding";
303 def aaddr : Operand<iPTR> {
304 let PrintMethod = "printAbsAddrOperand";
306 def symbolHi: Operand<i32> {
307 let PrintMethod = "printSymbolHi";
308 let EncoderMethod = "getHA16Encoding";
310 def symbolLo: Operand<i32> {
311 let PrintMethod = "printSymbolLo";
312 let EncoderMethod = "getLO16Encoding";
314 def crbitm: Operand<i8> {
315 let PrintMethod = "printcrbitm";
316 let EncoderMethod = "get_crbitm_encoding";
319 def memri : Operand<iPTR> {
320 let PrintMethod = "printMemRegImm";
321 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
322 let EncoderMethod = "getMemRIEncoding";
324 def memrr : Operand<iPTR> {
325 let PrintMethod = "printMemRegReg";
326 let MIOperandInfo = (ops ptr_rc, ptr_rc);
328 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
329 let PrintMethod = "printMemRegImmShifted";
330 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
331 let EncoderMethod = "getMemRIXEncoding";
333 def tocentry : Operand<iPTR> {
334 let MIOperandInfo = (ops i32imm:$imm);
337 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
338 // that doesn't matter.
339 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
340 (ops (i32 20), (i32 zero_reg))> {
341 let PrintMethod = "printPredicateOperand";
344 // Define PowerPC specific addressing mode.
345 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
346 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
347 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
348 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
350 /// This is just the offset part of iaddr, used for preinc.
351 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
353 //===----------------------------------------------------------------------===//
354 // PowerPC Instruction Predicate Definitions.
355 def FPContractions : Predicate<"!TM.Options.NoExcessFPPrecision">;
356 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
357 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
358 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
360 //===----------------------------------------------------------------------===//
361 // PowerPC Instruction Definitions.
363 // Pseudo-instructions:
365 let hasCtrlDep = 1 in {
366 let Defs = [R1], Uses = [R1] in {
367 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "",
368 [(callseq_start timm:$amt)]>;
369 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "",
370 [(callseq_end timm:$amt1, timm:$amt2)]>;
373 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
374 "UPDATE_VRSAVE $rD, $rS", []>;
377 let Defs = [R1], Uses = [R1] in
378 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "",
380 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
382 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
383 // instruction selection into a branch sequence.
384 let usesCustomInserter = 1, // Expanded after instruction selection.
385 PPC970_Single = 1 in {
386 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
389 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
392 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
395 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
398 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
403 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
404 // scavenge a register for it.
406 def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F),
409 // RESTORE_CR - Indicate that we're restoring the CR register (previously
410 // spilled), so we'll need to scavenge a register for it.
412 def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F),
415 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
416 let isReturn = 1, Uses = [LR, RM] in
417 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
418 "b${p:cc}lr ${p:reg}", BrB,
420 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in
421 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
425 def MovePCtoLR : Pseudo<(outs), (ins), "", []>,
428 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
429 let isBarrier = 1 in {
430 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
435 // BCC represents an arbitrary conditional branch on a predicate.
436 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
437 // a two-value operand where a dag node expects two operands. :(
438 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
439 "b${cond:cc} ${cond:reg}, $dst"
440 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
442 let Defs = [CTR], Uses = [CTR] in {
443 def BDZ : IForm_ext<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
444 "bdz $dst", BrB, []>;
445 def BDNZ : IForm_ext<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
446 "bdnz $dst", BrB, []>;
451 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
452 // Convenient aliases for call instructions
454 def BL_Darwin : IForm<18, 0, 1,
455 (outs), (ins calltarget:$func, variable_ops),
456 "bl $func", BrB, []>; // See Pat patterns below.
457 def BLA_Darwin : IForm<18, 1, 1,
458 (outs), (ins aaddr:$func, variable_ops),
459 "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>;
461 let Uses = [CTR, RM] in {
462 def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1,
463 (outs), (ins variable_ops),
465 [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>;
470 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
471 // Convenient aliases for call instructions
473 def BL_SVR4 : IForm<18, 0, 1,
474 (outs), (ins calltarget:$func, variable_ops),
475 "bl $func", BrB, []>; // See Pat patterns below.
476 def BLA_SVR4 : IForm<18, 1, 1,
477 (outs), (ins aaddr:$func, variable_ops),
479 [(PPCcall_SVR4 (i32 imm:$func))]>;
481 let Uses = [CTR, RM] in {
482 def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1,
483 (outs), (ins variable_ops),
485 [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>;
490 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
491 def TCRETURNdi :Pseudo< (outs),
492 (ins calltarget:$dst, i32imm:$offset, variable_ops),
493 "#TC_RETURNd $dst $offset",
497 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
498 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops),
499 "#TC_RETURNa $func $offset",
500 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
502 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
503 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset, variable_ops),
504 "#TC_RETURNr $dst $offset",
508 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
509 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
510 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
511 Requires<[In32BitMode]>;
515 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
516 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
517 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
522 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
523 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
524 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
529 // DCB* instructions.
530 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
531 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
532 PPC970_DGroup_Single;
533 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
534 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
535 PPC970_DGroup_Single;
536 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
537 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
538 PPC970_DGroup_Single;
539 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
540 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
541 PPC970_DGroup_Single;
542 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
543 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
544 PPC970_DGroup_Single;
545 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
546 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
547 PPC970_DGroup_Single;
548 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
549 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
550 PPC970_DGroup_Single;
551 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
552 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
553 PPC970_DGroup_Single;
555 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
559 let usesCustomInserter = 1 in {
560 let Defs = [CR0] in {
561 def ATOMIC_LOAD_ADD_I8 : Pseudo<
562 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
563 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>;
564 def ATOMIC_LOAD_SUB_I8 : Pseudo<
565 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
566 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>;
567 def ATOMIC_LOAD_AND_I8 : Pseudo<
568 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
569 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>;
570 def ATOMIC_LOAD_OR_I8 : Pseudo<
571 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
572 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>;
573 def ATOMIC_LOAD_XOR_I8 : Pseudo<
574 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
575 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>;
576 def ATOMIC_LOAD_NAND_I8 : Pseudo<
577 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
578 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>;
579 def ATOMIC_LOAD_ADD_I16 : Pseudo<
580 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
581 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>;
582 def ATOMIC_LOAD_SUB_I16 : Pseudo<
583 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
584 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>;
585 def ATOMIC_LOAD_AND_I16 : Pseudo<
586 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
587 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>;
588 def ATOMIC_LOAD_OR_I16 : Pseudo<
589 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
590 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>;
591 def ATOMIC_LOAD_XOR_I16 : Pseudo<
592 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
593 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>;
594 def ATOMIC_LOAD_NAND_I16 : Pseudo<
595 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
596 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>;
597 def ATOMIC_LOAD_ADD_I32 : Pseudo<
598 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
599 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>;
600 def ATOMIC_LOAD_SUB_I32 : Pseudo<
601 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
602 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>;
603 def ATOMIC_LOAD_AND_I32 : Pseudo<
604 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
605 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>;
606 def ATOMIC_LOAD_OR_I32 : Pseudo<
607 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
608 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>;
609 def ATOMIC_LOAD_XOR_I32 : Pseudo<
610 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
611 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>;
612 def ATOMIC_LOAD_NAND_I32 : Pseudo<
613 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
614 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>;
616 def ATOMIC_CMP_SWAP_I8 : Pseudo<
617 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
619 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
620 def ATOMIC_CMP_SWAP_I16 : Pseudo<
621 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
623 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
624 def ATOMIC_CMP_SWAP_I32 : Pseudo<
625 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
627 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
629 def ATOMIC_SWAP_I8 : Pseudo<
630 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
631 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>;
632 def ATOMIC_SWAP_I16 : Pseudo<
633 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
634 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>;
635 def ATOMIC_SWAP_I32 : Pseudo<
636 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
637 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>;
641 // Instructions to support atomic operations
642 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
643 "lwarx $rD, $src", LdStLWARX,
644 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>;
647 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
648 "stwcx. $rS, $dst", LdStSTWCX,
649 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>,
652 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
653 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>;
655 //===----------------------------------------------------------------------===//
656 // PPC32 Load Instructions.
659 // Unindexed (r+i) Loads.
660 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
661 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
662 "lbz $rD, $src", LdStLoad,
663 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
664 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
665 "lha $rD, $src", LdStLHA,
666 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
667 PPC970_DGroup_Cracked;
668 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
669 "lhz $rD, $src", LdStLoad,
670 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
671 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
672 "lwz $rD, $src", LdStLoad,
673 [(set GPRC:$rD, (load iaddr:$src))]>;
675 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
676 "lfs $rD, $src", LdStLFDU,
677 [(set F4RC:$rD, (load iaddr:$src))]>;
678 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
679 "lfd $rD, $src", LdStLFD,
680 [(set F8RC:$rD, (load iaddr:$src))]>;
683 // Unindexed (r+i) Loads with Update (preinc).
685 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
686 "lbzu $rD, $addr", LdStLoad,
687 []>, RegConstraint<"$addr.reg = $ea_result">,
688 NoEncode<"$ea_result">;
690 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
691 "lhau $rD, $addr", LdStLoad,
692 []>, RegConstraint<"$addr.reg = $ea_result">,
693 NoEncode<"$ea_result">;
695 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
696 "lhzu $rD, $addr", LdStLoad,
697 []>, RegConstraint<"$addr.reg = $ea_result">,
698 NoEncode<"$ea_result">;
700 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
701 "lwzu $rD, $addr", LdStLoad,
702 []>, RegConstraint<"$addr.reg = $ea_result">,
703 NoEncode<"$ea_result">;
705 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
706 "lfs $rD, $addr", LdStLFDU,
707 []>, RegConstraint<"$addr.reg = $ea_result">,
708 NoEncode<"$ea_result">;
710 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
711 "lfd $rD, $addr", LdStLFD,
712 []>, RegConstraint<"$addr.reg = $ea_result">,
713 NoEncode<"$ea_result">;
717 // Indexed (r+r) Loads.
719 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
720 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
721 "lbzx $rD, $src", LdStLoad,
722 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
723 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
724 "lhax $rD, $src", LdStLHA,
725 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
726 PPC970_DGroup_Cracked;
727 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
728 "lhzx $rD, $src", LdStLoad,
729 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
730 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
731 "lwzx $rD, $src", LdStLoad,
732 [(set GPRC:$rD, (load xaddr:$src))]>;
735 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
736 "lhbrx $rD, $src", LdStLoad,
737 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i16))]>;
738 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
739 "lwbrx $rD, $src", LdStLoad,
740 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>;
742 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
743 "lfsx $frD, $src", LdStLFDU,
744 [(set F4RC:$frD, (load xaddr:$src))]>;
745 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
746 "lfdx $frD, $src", LdStLFDU,
747 [(set F8RC:$frD, (load xaddr:$src))]>;
750 //===----------------------------------------------------------------------===//
751 // PPC32 Store Instructions.
754 // Unindexed (r+i) Stores.
755 let PPC970_Unit = 2 in {
756 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
757 "stb $rS, $src", LdStStore,
758 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
759 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
760 "sth $rS, $src", LdStStore,
761 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
762 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
763 "stw $rS, $src", LdStStore,
764 [(store GPRC:$rS, iaddr:$src)]>;
765 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
766 "stfs $rS, $dst", LdStUX,
767 [(store F4RC:$rS, iaddr:$dst)]>;
768 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
769 "stfd $rS, $dst", LdStUX,
770 [(store F8RC:$rS, iaddr:$dst)]>;
773 // Unindexed (r+i) Stores with Update (preinc).
774 let PPC970_Unit = 2 in {
775 def STBU : DForm_1a<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
776 symbolLo:$ptroff, ptr_rc:$ptrreg),
777 "stbu $rS, $ptroff($ptrreg)", LdStStore,
778 [(set ptr_rc:$ea_res,
779 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
780 iaddroff:$ptroff))]>,
781 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
782 def STHU : DForm_1a<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
783 symbolLo:$ptroff, ptr_rc:$ptrreg),
784 "sthu $rS, $ptroff($ptrreg)", LdStStore,
785 [(set ptr_rc:$ea_res,
786 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
787 iaddroff:$ptroff))]>,
788 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
789 def STWU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
790 symbolLo:$ptroff, ptr_rc:$ptrreg),
791 "stwu $rS, $ptroff($ptrreg)", LdStStore,
792 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
793 iaddroff:$ptroff))]>,
794 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
795 def STFSU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
796 symbolLo:$ptroff, ptr_rc:$ptrreg),
797 "stfsu $rS, $ptroff($ptrreg)", LdStStore,
798 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
799 iaddroff:$ptroff))]>,
800 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
801 def STFDU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
802 symbolLo:$ptroff, ptr_rc:$ptrreg),
803 "stfdu $rS, $ptroff($ptrreg)", LdStStore,
804 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
805 iaddroff:$ptroff))]>,
806 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
810 // Indexed (r+r) Stores.
812 let PPC970_Unit = 2 in {
813 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
814 "stbx $rS, $dst", LdStStore,
815 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
816 PPC970_DGroup_Cracked;
817 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
818 "sthx $rS, $dst", LdStStore,
819 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
820 PPC970_DGroup_Cracked;
821 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
822 "stwx $rS, $dst", LdStStore,
823 [(store GPRC:$rS, xaddr:$dst)]>,
824 PPC970_DGroup_Cracked;
826 let mayStore = 1 in {
827 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
828 "stwux $rS, $rA, $rB", LdStStore,
831 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
832 "sthbrx $rS, $dst", LdStStore,
833 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>,
834 PPC970_DGroup_Cracked;
835 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
836 "stwbrx $rS, $dst", LdStStore,
837 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i32)]>,
838 PPC970_DGroup_Cracked;
840 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
841 "stfiwx $frS, $dst", LdStUX,
842 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
844 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
845 "stfsx $frS, $dst", LdStUX,
846 [(store F4RC:$frS, xaddr:$dst)]>;
847 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
848 "stfdx $frS, $dst", LdStUX,
849 [(store F8RC:$frS, xaddr:$dst)]>;
852 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
856 //===----------------------------------------------------------------------===//
857 // PPC32 Arithmetic Instructions.
860 let PPC970_Unit = 1 in { // FXU Operations.
861 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
862 "addi $rD, $rA, $imm", IntSimple,
863 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
864 def ADDIL : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$imm),
865 "addi $rD, $rA, $imm", IntSimple,
866 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
867 let Defs = [CARRY] in {
868 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
869 "addic $rD, $rA, $imm", IntGeneral,
870 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
871 PPC970_DGroup_Cracked;
872 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
873 "addic. $rD, $rA, $imm", IntGeneral,
876 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
877 "addis $rD, $rA, $imm", IntSimple,
878 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
879 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
880 "la $rD, $sym($rA)", IntGeneral,
881 [(set GPRC:$rD, (add GPRC:$rA,
882 (PPClo tglobaladdr:$sym, 0)))]>;
883 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
884 "mulli $rD, $rA, $imm", IntMulLI,
885 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
886 let Defs = [CARRY] in {
887 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
888 "subfic $rD, $rA, $imm", IntGeneral,
889 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
892 let isReMaterializable = 1 in {
893 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
894 "li $rD, $imm", IntSimple,
895 [(set GPRC:$rD, immSExt16:$imm)]>;
896 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
897 "lis $rD, $imm", IntSimple,
898 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
902 let PPC970_Unit = 1 in { // FXU Operations.
903 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
904 "andi. $dst, $src1, $src2", IntGeneral,
905 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
907 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
908 "andis. $dst, $src1, $src2", IntGeneral,
909 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
911 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
912 "ori $dst, $src1, $src2", IntSimple,
913 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
914 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
915 "oris $dst, $src1, $src2", IntSimple,
916 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
917 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
918 "xori $dst, $src1, $src2", IntSimple,
919 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
920 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
921 "xoris $dst, $src1, $src2", IntSimple,
922 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
923 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple,
925 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
926 "cmpwi $crD, $rA, $imm", IntCompare>;
927 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
928 "cmplwi $dst, $src1, $src2", IntCompare>;
932 let PPC970_Unit = 1 in { // FXU Operations.
933 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
934 "nand $rA, $rS, $rB", IntSimple,
935 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
936 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
937 "and $rA, $rS, $rB", IntSimple,
938 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
939 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
940 "andc $rA, $rS, $rB", IntSimple,
941 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
942 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
943 "or $rA, $rS, $rB", IntSimple,
944 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
945 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
946 "nor $rA, $rS, $rB", IntSimple,
947 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
948 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
949 "orc $rA, $rS, $rB", IntSimple,
950 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
951 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
952 "eqv $rA, $rS, $rB", IntSimple,
953 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
954 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
955 "xor $rA, $rS, $rB", IntSimple,
956 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
957 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
958 "slw $rA, $rS, $rB", IntGeneral,
959 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
960 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
961 "srw $rA, $rS, $rB", IntGeneral,
962 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
963 let Defs = [CARRY] in {
964 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
965 "sraw $rA, $rS, $rB", IntShift,
966 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
970 let PPC970_Unit = 1 in { // FXU Operations.
971 let Defs = [CARRY] in {
972 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
973 "srawi $rA, $rS, $SH", IntShift,
974 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
976 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
977 "cntlzw $rA, $rS", IntGeneral,
978 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
979 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
980 "extsb $rA, $rS", IntSimple,
981 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
982 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
983 "extsh $rA, $rS", IntSimple,
984 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
986 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
987 "cmpw $crD, $rA, $rB", IntCompare>;
988 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
989 "cmplw $crD, $rA, $rB", IntCompare>;
991 let PPC970_Unit = 3 in { // FPU Operations.
992 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
993 // "fcmpo $crD, $fA, $fB", FPCompare>;
994 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
995 "fcmpu $crD, $fA, $fB", FPCompare>;
996 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
997 "fcmpu $crD, $fA, $fB", FPCompare>;
1000 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
1001 "fctiwz $frD, $frB", FPGeneral,
1002 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
1003 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
1004 "frsp $frD, $frB", FPGeneral,
1005 [(set F4RC:$frD, (fround F8RC:$frB))]>;
1006 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
1007 "fsqrt $frD, $frB", FPSqrt,
1008 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
1009 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
1010 "fsqrts $frD, $frB", FPSqrt,
1011 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
1015 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1016 /// often coalesced away and we don't want the dispatch group builder to think
1017 /// that they will fill slots (which could cause the load of a LSU reject to
1018 /// sneak into a d-group with a store).
1019 def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
1020 "fmr $frD, $frB", FPGeneral,
1021 []>, // (set F4RC:$frD, F4RC:$frB)
1024 let PPC970_Unit = 3 in { // FPU Operations.
1025 // These are artificially split into two different forms, for 4/8 byte FP.
1026 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
1027 "fabs $frD, $frB", FPGeneral,
1028 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
1029 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
1030 "fabs $frD, $frB", FPGeneral,
1031 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
1032 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
1033 "fnabs $frD, $frB", FPGeneral,
1034 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
1035 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
1036 "fnabs $frD, $frB", FPGeneral,
1037 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
1038 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
1039 "fneg $frD, $frB", FPGeneral,
1040 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
1041 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
1042 "fneg $frD, $frB", FPGeneral,
1043 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
1047 // XL-Form instructions. condition register logical ops.
1049 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
1050 "mcrf $BF, $BFA", BrMCR>,
1051 PPC970_DGroup_First, PPC970_Unit_CRU;
1053 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
1054 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1055 "creqv $CRD, $CRA, $CRB", BrCR,
1058 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
1059 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1060 "cror $CRD, $CRA, $CRB", BrCR,
1063 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
1064 "creqv $dst, $dst, $dst", BrCR,
1067 def CRUNSET: XLForm_1_ext<19, 193, (outs CRBITRC:$dst), (ins),
1068 "crxor $dst, $dst, $dst", BrCR,
1071 // XFX-Form instructions. Instructions that deal with SPRs.
1073 let Uses = [CTR] in {
1074 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
1075 "mfctr $rT", SprMFSPR>,
1076 PPC970_DGroup_First, PPC970_Unit_FXU;
1078 let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in {
1079 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
1080 "mtctr $rS", SprMTSPR>,
1081 PPC970_DGroup_First, PPC970_Unit_FXU;
1084 let Defs = [LR] in {
1085 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1086 "mtlr $rS", SprMTSPR>,
1087 PPC970_DGroup_First, PPC970_Unit_FXU;
1089 let Uses = [LR] in {
1090 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1091 "mflr $rT", SprMFSPR>,
1092 PPC970_DGroup_First, PPC970_Unit_FXU;
1095 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1096 // a GPR on the PPC970. As such, copies in and out have the same performance
1097 // characteristics as an OR instruction.
1098 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1099 "mtspr 256, $rS", IntGeneral>,
1100 PPC970_DGroup_Single, PPC970_Unit_FXU;
1101 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1102 "mfspr $rT, 256", IntGeneral>,
1103 PPC970_DGroup_First, PPC970_Unit_FXU;
1105 def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS),
1106 "mtcrf $FXM, $rS", BrMCRX>,
1107 PPC970_MicroCode, PPC970_Unit_CRU;
1109 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
1110 // declaring that here gives the local register allocator problems with this:
1112 // MFCR <kill of whatever preg got assigned to vreg>
1113 // while not declaring it breaks DeadMachineInstructionElimination.
1114 // As it turns out, in all cases where we currently use this,
1115 // we're only interested in one subregister of it. Represent this in the
1116 // instruction to keep the register allocator from becoming confused.
1118 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
1119 def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1121 PPC970_MicroCode, PPC970_Unit_CRU;
1123 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
1124 "mfcr $rT", SprMFCR>,
1125 PPC970_MicroCode, PPC970_Unit_CRU;
1127 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1128 "mfocrf $rT, $FXM", SprMFCR>,
1129 PPC970_DGroup_First, PPC970_Unit_CRU;
1131 // Instructions to manipulate FPSCR. Only long double handling uses these.
1132 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
1134 let Uses = [RM], Defs = [RM] in {
1135 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1136 "mtfsb0 $FM", IntMTFSB0,
1137 [(PPCmtfsb0 (i32 imm:$FM))]>,
1138 PPC970_DGroup_Single, PPC970_Unit_FPU;
1139 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1140 "mtfsb1 $FM", IntMTFSB0,
1141 [(PPCmtfsb1 (i32 imm:$FM))]>,
1142 PPC970_DGroup_Single, PPC970_Unit_FPU;
1143 // MTFSF does not actually produce an FP result. We pretend it copies
1144 // input reg B to the output. If we didn't do this it would look like the
1145 // instruction had no outputs (because we aren't modelling the FPSCR) and
1146 // it would be deleted.
1147 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
1148 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
1149 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
1150 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM),
1151 F8RC:$rT, F8RC:$FRB))]>,
1152 PPC970_DGroup_Single, PPC970_Unit_FPU;
1154 let Uses = [RM] in {
1155 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1156 "mffs $rT", IntMFFS,
1157 [(set F8RC:$rT, (PPCmffs))]>,
1158 PPC970_DGroup_Single, PPC970_Unit_FPU;
1159 def FADDrtz: AForm_2<63, 21,
1160 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1161 "fadd $FRT, $FRA, $FRB", FPGeneral,
1162 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>,
1163 PPC970_DGroup_Single, PPC970_Unit_FPU;
1167 let PPC970_Unit = 1 in { // FXU Operations.
1169 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1171 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1172 "add $rT, $rA, $rB", IntSimple,
1173 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
1174 let Defs = [CARRY] in {
1175 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1176 "addc $rT, $rA, $rB", IntGeneral,
1177 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
1178 PPC970_DGroup_Cracked;
1180 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1181 "divw $rT, $rA, $rB", IntDivW,
1182 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
1183 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1184 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1185 "divwu $rT, $rA, $rB", IntDivW,
1186 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
1187 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1188 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1189 "mulhw $rT, $rA, $rB", IntMulHW,
1190 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
1191 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1192 "mulhwu $rT, $rA, $rB", IntMulHWU,
1193 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
1194 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1195 "mullw $rT, $rA, $rB", IntMulHW,
1196 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
1197 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1198 "subf $rT, $rA, $rB", IntGeneral,
1199 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
1200 let Defs = [CARRY] in {
1201 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1202 "subfc $rT, $rA, $rB", IntGeneral,
1203 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
1204 PPC970_DGroup_Cracked;
1206 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1207 "neg $rT, $rA", IntSimple,
1208 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
1209 let Uses = [CARRY], Defs = [CARRY] in {
1210 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1211 "adde $rT, $rA, $rB", IntGeneral,
1212 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
1213 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1214 "addme $rT, $rA", IntGeneral,
1215 [(set GPRC:$rT, (adde GPRC:$rA, -1))]>;
1216 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1217 "addze $rT, $rA", IntGeneral,
1218 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
1219 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1220 "subfe $rT, $rA, $rB", IntGeneral,
1221 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
1222 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1223 "subfme $rT, $rA", IntGeneral,
1224 [(set GPRC:$rT, (sube -1, GPRC:$rA))]>;
1225 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1226 "subfze $rT, $rA", IntGeneral,
1227 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
1231 // A-Form instructions. Most of the instructions executed in the FPU are of
1234 let PPC970_Unit = 3 in { // FPU Operations.
1235 let Uses = [RM] in {
1236 def FMADD : AForm_1<63, 29,
1237 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1238 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1239 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1241 Requires<[FPContractions]>;
1242 def FMADDS : AForm_1<59, 29,
1243 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1244 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1245 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1247 Requires<[FPContractions]>;
1248 def FMSUB : AForm_1<63, 28,
1249 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1250 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1251 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1253 Requires<[FPContractions]>;
1254 def FMSUBS : AForm_1<59, 28,
1255 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1256 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1257 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1259 Requires<[FPContractions]>;
1260 def FNMADD : AForm_1<63, 31,
1261 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1262 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1263 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1265 Requires<[FPContractions]>;
1266 def FNMADDS : AForm_1<59, 31,
1267 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1268 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1269 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1271 Requires<[FPContractions]>;
1272 def FNMSUB : AForm_1<63, 30,
1273 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1274 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1275 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1277 Requires<[FPContractions]>;
1278 def FNMSUBS : AForm_1<59, 30,
1279 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1280 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1281 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1283 Requires<[FPContractions]>;
1285 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1286 // having 4 of these, force the comparison to always be an 8-byte double (code
1287 // should use an FMRSD if the input comparison value really wants to be a float)
1288 // and 4/8 byte forms for the result and operand type..
1289 def FSELD : AForm_1<63, 23,
1290 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1291 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1292 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
1293 def FSELS : AForm_1<63, 23,
1294 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1295 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1296 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
1297 let Uses = [RM] in {
1298 def FADD : AForm_2<63, 21,
1299 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1300 "fadd $FRT, $FRA, $FRB", FPGeneral,
1301 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
1302 def FADDS : AForm_2<59, 21,
1303 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1304 "fadds $FRT, $FRA, $FRB", FPGeneral,
1305 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
1306 def FDIV : AForm_2<63, 18,
1307 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1308 "fdiv $FRT, $FRA, $FRB", FPDivD,
1309 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1310 def FDIVS : AForm_2<59, 18,
1311 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1312 "fdivs $FRT, $FRA, $FRB", FPDivS,
1313 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1314 def FMUL : AForm_3<63, 25,
1315 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1316 "fmul $FRT, $FRA, $FRB", FPFused,
1317 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
1318 def FMULS : AForm_3<59, 25,
1319 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1320 "fmuls $FRT, $FRA, $FRB", FPGeneral,
1321 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
1322 def FSUB : AForm_2<63, 20,
1323 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1324 "fsub $FRT, $FRA, $FRB", FPGeneral,
1325 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1326 def FSUBS : AForm_2<59, 20,
1327 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1328 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1329 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1333 let PPC970_Unit = 1 in { // FXU Operations.
1334 // M-Form instructions. rotate and mask instructions.
1336 let isCommutable = 1 in {
1337 // RLWIMI can be commuted if the rotate amount is zero.
1338 def RLWIMI : MForm_2<20,
1339 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1340 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1341 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1344 def RLWINM : MForm_2<21,
1345 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1346 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1348 def RLWINMo : MForm_2<21,
1349 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1350 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1351 []>, isDOT, PPC970_DGroup_Cracked;
1352 def RLWNM : MForm_2<23,
1353 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1354 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1359 //===----------------------------------------------------------------------===//
1360 // PowerPC Instruction Patterns
1363 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1364 def : Pat<(i32 imm:$imm),
1365 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1367 // Implement the 'not' operation with the NOR instruction.
1368 def NOT : Pat<(not GPRC:$in),
1369 (NOR GPRC:$in, GPRC:$in)>;
1371 // ADD an arbitrary immediate.
1372 def : Pat<(add GPRC:$in, imm:$imm),
1373 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1374 // OR an arbitrary immediate.
1375 def : Pat<(or GPRC:$in, imm:$imm),
1376 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1377 // XOR an arbitrary immediate.
1378 def : Pat<(xor GPRC:$in, imm:$imm),
1379 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1381 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1382 (SUBFIC GPRC:$in, imm:$imm)>;
1385 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1386 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1387 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1388 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1391 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1392 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1393 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1394 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1397 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1398 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1401 def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)),
1402 (BL_Darwin tglobaladdr:$dst)>;
1403 def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)),
1404 (BL_Darwin texternalsym:$dst)>;
1405 def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)),
1406 (BL_SVR4 tglobaladdr:$dst)>;
1407 def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)),
1408 (BL_SVR4 texternalsym:$dst)>;
1411 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1412 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1414 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1415 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1417 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1418 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1422 // Hi and Lo for Darwin Global Addresses.
1423 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1424 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1425 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1426 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1427 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1428 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1429 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
1430 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
1431 def : Pat<(PPChi tglobaltlsaddr:$g, GPRC:$in),
1432 (ADDIS GPRC:$in, tglobaltlsaddr:$g)>;
1433 def : Pat<(PPClo tglobaltlsaddr:$g, GPRC:$in),
1434 (ADDIL GPRC:$in, tglobaltlsaddr:$g)>;
1435 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1436 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1437 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1438 (ADDIS GPRC:$in, tconstpool:$g)>;
1439 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1440 (ADDIS GPRC:$in, tjumptable:$g)>;
1441 def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)),
1442 (ADDIS GPRC:$in, tblockaddress:$g)>;
1444 // Fused negative multiply subtract, alternate pattern
1445 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1446 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1447 Requires<[FPContractions]>;
1448 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1449 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1450 Requires<[FPContractions]>;
1452 // Standard shifts. These are represented separately from the real shifts above
1453 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1455 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1456 (SRAW GPRC:$rS, GPRC:$rB)>;
1457 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1458 (SRW GPRC:$rS, GPRC:$rB)>;
1459 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1460 (SLW GPRC:$rS, GPRC:$rB)>;
1462 def : Pat<(zextloadi1 iaddr:$src),
1464 def : Pat<(zextloadi1 xaddr:$src),
1466 def : Pat<(extloadi1 iaddr:$src),
1468 def : Pat<(extloadi1 xaddr:$src),
1470 def : Pat<(extloadi8 iaddr:$src),
1472 def : Pat<(extloadi8 xaddr:$src),
1474 def : Pat<(extloadi16 iaddr:$src),
1476 def : Pat<(extloadi16 xaddr:$src),
1478 def : Pat<(f64 (extloadf32 iaddr:$src)),
1479 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
1480 def : Pat<(f64 (extloadf32 xaddr:$src)),
1481 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
1483 def : Pat<(f64 (fextend F4RC:$src)),
1484 (COPY_TO_REGCLASS F4RC:$src, F8RC)>;
1487 def : Pat<(membarrier (i32 imm /*ll*/),
1491 (i32 imm /*device*/)),
1494 def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
1496 include "PPCInstrAltivec.td"
1497 include "PPCInstr64Bit.td"