1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
26 def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
38 def SDT_PPClbrx : SDTypeProfile<1, 2, [
39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
41 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPClarx : SDTypeProfile<1, 1, [
46 SDTCisInt<0>, SDTCisPtrTy<1>
48 def SDT_PPCstcx : SDTypeProfile<0, 2, [
49 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
53 SDTCisPtrTy<0>, SDTCisVT<1, i32>
56 def SDT_PPCnop : SDTypeProfile<0, 0, []>;
58 //===----------------------------------------------------------------------===//
59 // PowerPC specific DAG Nodes.
62 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
63 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
64 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
65 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
66 [SDNPHasChain, SDNPMayStore]>;
68 // This sequence is used for long double->int conversions. It changes the
69 // bits in the FPSCR which is not modelled.
70 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
72 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
73 [SDNPInFlag, SDNPOutFlag]>;
74 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
75 [SDNPInFlag, SDNPOutFlag]>;
76 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
77 [SDNPInFlag, SDNPOutFlag]>;
78 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
79 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
83 def PPCfsel : SDNode<"PPCISD::FSEL",
84 // Type constraint for fsel.
85 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
86 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
88 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
89 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
90 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
91 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
92 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
94 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
96 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
97 // amounts. These nodes are generated by the multi-precision shift code.
98 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
99 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
100 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
102 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
103 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
104 [SDNPHasChain, SDNPMayStore]>;
106 // These are target-independent nodes, but have target-specific formats.
107 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
108 [SDNPHasChain, SDNPOutFlag]>;
109 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
110 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
112 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
113 def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall,
114 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
116 def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall,
117 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
119 def PPCnop : SDNode<"PPCISD::NOP", SDT_PPCnop, [SDNPInFlag, SDNPOutFlag]>;
120 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
121 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
122 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
123 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
124 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
125 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
126 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
127 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
128 def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone,
129 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
132 def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone,
133 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
136 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
137 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
139 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
140 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
142 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
143 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
145 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
146 [SDNPHasChain, SDNPOptInFlag]>;
148 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
149 [SDNPHasChain, SDNPMayLoad]>;
150 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
151 [SDNPHasChain, SDNPMayStore]>;
153 // Instructions to support atomic operations
154 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
155 [SDNPHasChain, SDNPMayLoad]>;
156 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
157 [SDNPHasChain, SDNPMayStore]>;
159 // Instructions to support dynamic alloca.
160 def SDTDynOp : SDTypeProfile<1, 2, []>;
161 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
163 //===----------------------------------------------------------------------===//
164 // PowerPC specific transformation functions and pattern fragments.
167 def SHL32 : SDNodeXForm<imm, [{
168 // Transformation function: 31 - imm
169 return getI32Imm(31 - N->getZExtValue());
172 def SRL32 : SDNodeXForm<imm, [{
173 // Transformation function: 32 - imm
174 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
177 def LO16 : SDNodeXForm<imm, [{
178 // Transformation function: get the low 16 bits.
179 return getI32Imm((unsigned short)N->getZExtValue());
182 def HI16 : SDNodeXForm<imm, [{
183 // Transformation function: shift the immediate value down into the low bits.
184 return getI32Imm((unsigned)N->getZExtValue() >> 16);
187 def HA16 : SDNodeXForm<imm, [{
188 // Transformation function: shift the immediate value down into the low bits.
189 signed int Val = N->getZExtValue();
190 return getI32Imm((Val - (signed short)Val) >> 16);
192 def MB : SDNodeXForm<imm, [{
193 // Transformation function: get the start bit of a mask
195 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
196 return getI32Imm(mb);
199 def ME : SDNodeXForm<imm, [{
200 // Transformation function: get the end bit of a mask
202 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
203 return getI32Imm(me);
205 def maskimm32 : PatLeaf<(imm), [{
206 // maskImm predicate - True if immediate is a run of ones.
208 if (N->getValueType(0) == MVT::i32)
209 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
214 def immSExt16 : PatLeaf<(imm), [{
215 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
216 // field. Used by instructions like 'addi'.
217 if (N->getValueType(0) == MVT::i32)
218 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
220 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
222 def immZExt16 : PatLeaf<(imm), [{
223 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
224 // field. Used by instructions like 'ori'.
225 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
228 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
229 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
230 // identical in 32-bit mode, but in 64-bit mode, they return true if the
231 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
233 def imm16ShiftedZExt : PatLeaf<(imm), [{
234 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
235 // immediate are set. Used by instructions like 'xoris'.
236 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
239 def imm16ShiftedSExt : PatLeaf<(imm), [{
240 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
241 // immediate are set. Used by instructions like 'addis'. Identical to
242 // imm16ShiftedZExt in 32-bit mode.
243 if (N->getZExtValue() & 0xFFFF) return false;
244 if (N->getValueType(0) == MVT::i32)
246 // For 64-bit, make sure it is sext right.
247 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
251 //===----------------------------------------------------------------------===//
252 // PowerPC Flag Definitions.
254 class isPPC64 { bit PPC64 = 1; }
256 list<Register> Defs = [CR0];
260 class RegConstraint<string C> {
261 string Constraints = C;
263 class NoEncode<string E> {
264 string DisableEncoding = E;
268 //===----------------------------------------------------------------------===//
269 // PowerPC Operand Definitions.
271 def s5imm : Operand<i32> {
272 let PrintMethod = "printS5ImmOperand";
274 def u5imm : Operand<i32> {
275 let PrintMethod = "printU5ImmOperand";
277 def u6imm : Operand<i32> {
278 let PrintMethod = "printU6ImmOperand";
280 def s16imm : Operand<i32> {
281 let PrintMethod = "printS16ImmOperand";
283 def u16imm : Operand<i32> {
284 let PrintMethod = "printU16ImmOperand";
286 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
287 let PrintMethod = "printS16X4ImmOperand";
289 def directbrtarget : Operand<OtherVT> {
290 let PrintMethod = "printBranchOperand";
291 let EncoderMethod = "getDirectBrEncoding";
293 def condbrtarget : Operand<OtherVT> {
294 let EncoderMethod = "getCondBrEncoding";
296 def calltarget : Operand<iPTR> {
297 let EncoderMethod = "getDirectBrEncoding";
299 def aaddr : Operand<iPTR> {
300 let PrintMethod = "printAbsAddrOperand";
302 def piclabel: Operand<iPTR> {}
303 def symbolHi: Operand<i32> {
304 let PrintMethod = "printSymbolHi";
305 let EncoderMethod = "getHA16Encoding";
307 def symbolLo: Operand<i32> {
308 let PrintMethod = "printSymbolLo";
309 let EncoderMethod = "getLO16Encoding";
311 def crbitm: Operand<i8> {
312 let PrintMethod = "printcrbitm";
313 let EncoderMethod = "get_crbitm_encoding";
316 def memri : Operand<iPTR> {
317 let PrintMethod = "printMemRegImm";
318 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
320 def memrr : Operand<iPTR> {
321 let PrintMethod = "printMemRegReg";
322 let MIOperandInfo = (ops ptr_rc, ptr_rc);
324 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
325 let PrintMethod = "printMemRegImmShifted";
326 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
327 let EncoderMethod = "getMemRIXEncoding";
329 def tocentry : Operand<iPTR> {
330 let MIOperandInfo = (ops i32imm:$imm);
333 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
334 // that doesn't matter.
335 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
336 (ops (i32 20), (i32 zero_reg))> {
337 let PrintMethod = "printPredicateOperand";
340 // Define PowerPC specific addressing mode.
341 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
342 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
343 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
344 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
346 /// This is just the offset part of iaddr, used for preinc.
347 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
349 //===----------------------------------------------------------------------===//
350 // PowerPC Instruction Predicate Definitions.
351 def FPContractions : Predicate<"!NoExcessFPPrecision">;
352 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
353 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
356 //===----------------------------------------------------------------------===//
357 // PowerPC Instruction Definitions.
359 // Pseudo-instructions:
361 let hasCtrlDep = 1 in {
362 let Defs = [R1], Uses = [R1] in {
363 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "",
364 [(callseq_start timm:$amt)]>;
365 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "",
366 [(callseq_end timm:$amt1, timm:$amt2)]>;
369 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
370 "UPDATE_VRSAVE $rD, $rS", []>;
373 let Defs = [R1], Uses = [R1] in
374 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "",
376 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
378 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
379 // instruction selection into a branch sequence.
380 let usesCustomInserter = 1, // Expanded after instruction selection.
381 PPC970_Single = 1 in {
382 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
385 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
388 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
391 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
394 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
399 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
400 // scavenge a register for it.
401 def SPILL_CR : Pseudo<(outs), (ins GPRC:$cond, memri:$F),
404 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
405 let isReturn = 1, Uses = [LR, RM] in
406 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
407 "b${p:cc}lr ${p:reg}", BrB,
409 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in
410 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
414 def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "", []>,
417 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
418 let isBarrier = 1 in {
419 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
424 // BCC represents an arbitrary conditional branch on a predicate.
425 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
426 // a two-value operand where a dag node expects two operands. :(
427 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
428 "b${cond:cc} ${cond:reg}, $dst"
429 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
433 let isCall = 1, PPC970_Unit = 7,
434 // All calls clobber the non-callee saved registers...
435 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
436 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
437 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
439 CR0,CR1,CR5,CR6,CR7,CARRY] in {
440 // Convenient aliases for call instructions
442 def BL_Darwin : IForm<18, 0, 1,
443 (outs), (ins calltarget:$func, variable_ops),
444 "bl $func", BrB, []>; // See Pat patterns below.
445 def BLA_Darwin : IForm<18, 1, 1,
446 (outs), (ins aaddr:$func, variable_ops),
447 "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>;
449 let Uses = [CTR, RM] in {
450 def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1,
451 (outs), (ins variable_ops),
453 [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>;
458 let isCall = 1, PPC970_Unit = 7,
459 // All calls clobber the non-callee saved registers...
460 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
461 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
462 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
464 CR0,CR1,CR5,CR6,CR7,CARRY] in {
465 // Convenient aliases for call instructions
467 def BL_SVR4 : IForm<18, 0, 1,
468 (outs), (ins calltarget:$func, variable_ops),
469 "bl $func", BrB, []>; // See Pat patterns below.
470 def BLA_SVR4 : IForm<18, 1, 1,
471 (outs), (ins aaddr:$func, variable_ops),
473 [(PPCcall_SVR4 (i32 imm:$func))]>;
475 let Uses = [CTR, RM] in {
476 def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1,
477 (outs), (ins variable_ops),
479 [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>;
484 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
485 def TCRETURNdi :Pseudo< (outs),
486 (ins calltarget:$dst, i32imm:$offset, variable_ops),
487 "#TC_RETURNd $dst $offset",
491 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
492 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops),
493 "#TC_RETURNa $func $offset",
494 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
496 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
497 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset, variable_ops),
498 "#TC_RETURNr $dst $offset",
502 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
503 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
504 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
505 Requires<[In32BitMode]>;
509 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
510 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
511 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
516 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
517 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
518 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
523 // DCB* instructions.
524 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
525 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
526 PPC970_DGroup_Single;
527 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
528 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
529 PPC970_DGroup_Single;
530 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
531 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
532 PPC970_DGroup_Single;
533 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
534 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
535 PPC970_DGroup_Single;
536 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
537 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
538 PPC970_DGroup_Single;
539 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
540 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
541 PPC970_DGroup_Single;
542 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
543 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
544 PPC970_DGroup_Single;
545 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
546 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
547 PPC970_DGroup_Single;
550 let usesCustomInserter = 1 in {
551 let Uses = [CR0] in {
552 def ATOMIC_LOAD_ADD_I8 : Pseudo<
553 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
554 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>;
555 def ATOMIC_LOAD_SUB_I8 : Pseudo<
556 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
557 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>;
558 def ATOMIC_LOAD_AND_I8 : Pseudo<
559 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
560 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>;
561 def ATOMIC_LOAD_OR_I8 : Pseudo<
562 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
563 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>;
564 def ATOMIC_LOAD_XOR_I8 : Pseudo<
565 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
566 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>;
567 def ATOMIC_LOAD_NAND_I8 : Pseudo<
568 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
569 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>;
570 def ATOMIC_LOAD_ADD_I16 : Pseudo<
571 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
572 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>;
573 def ATOMIC_LOAD_SUB_I16 : Pseudo<
574 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
575 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>;
576 def ATOMIC_LOAD_AND_I16 : Pseudo<
577 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
578 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>;
579 def ATOMIC_LOAD_OR_I16 : Pseudo<
580 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
581 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>;
582 def ATOMIC_LOAD_XOR_I16 : Pseudo<
583 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
584 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>;
585 def ATOMIC_LOAD_NAND_I16 : Pseudo<
586 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
587 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>;
588 def ATOMIC_LOAD_ADD_I32 : Pseudo<
589 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
590 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>;
591 def ATOMIC_LOAD_SUB_I32 : Pseudo<
592 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
593 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>;
594 def ATOMIC_LOAD_AND_I32 : Pseudo<
595 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
596 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>;
597 def ATOMIC_LOAD_OR_I32 : Pseudo<
598 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
599 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>;
600 def ATOMIC_LOAD_XOR_I32 : Pseudo<
601 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
602 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>;
603 def ATOMIC_LOAD_NAND_I32 : Pseudo<
604 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
605 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>;
607 def ATOMIC_CMP_SWAP_I8 : Pseudo<
608 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
610 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
611 def ATOMIC_CMP_SWAP_I16 : Pseudo<
612 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
614 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
615 def ATOMIC_CMP_SWAP_I32 : Pseudo<
616 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
618 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
620 def ATOMIC_SWAP_I8 : Pseudo<
621 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
622 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>;
623 def ATOMIC_SWAP_I16 : Pseudo<
624 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
625 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>;
626 def ATOMIC_SWAP_I32 : Pseudo<
627 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
628 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>;
632 // Instructions to support atomic operations
633 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
634 "lwarx $rD, $src", LdStLWARX,
635 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>;
638 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
639 "stwcx. $rS, $dst", LdStSTWCX,
640 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>,
643 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
644 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStGeneral, [(trap)]>;
646 //===----------------------------------------------------------------------===//
647 // PPC32 Load Instructions.
650 // Unindexed (r+i) Loads.
651 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
652 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
653 "lbz $rD, $src", LdStGeneral,
654 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
655 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
656 "lha $rD, $src", LdStLHA,
657 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
658 PPC970_DGroup_Cracked;
659 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
660 "lhz $rD, $src", LdStGeneral,
661 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
662 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
663 "lwz $rD, $src", LdStGeneral,
664 [(set GPRC:$rD, (load iaddr:$src))]>;
666 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
667 "lfs $rD, $src", LdStLFDU,
668 [(set F4RC:$rD, (load iaddr:$src))]>;
669 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
670 "lfd $rD, $src", LdStLFD,
671 [(set F8RC:$rD, (load iaddr:$src))]>;
674 // Unindexed (r+i) Loads with Update (preinc).
676 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
677 "lbzu $rD, $addr", LdStGeneral,
678 []>, RegConstraint<"$addr.reg = $ea_result">,
679 NoEncode<"$ea_result">;
681 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
682 "lhau $rD, $addr", LdStGeneral,
683 []>, RegConstraint<"$addr.reg = $ea_result">,
684 NoEncode<"$ea_result">;
686 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
687 "lhzu $rD, $addr", LdStGeneral,
688 []>, RegConstraint<"$addr.reg = $ea_result">,
689 NoEncode<"$ea_result">;
691 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
692 "lwzu $rD, $addr", LdStGeneral,
693 []>, RegConstraint<"$addr.reg = $ea_result">,
694 NoEncode<"$ea_result">;
696 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
697 "lfs $rD, $addr", LdStLFDU,
698 []>, RegConstraint<"$addr.reg = $ea_result">,
699 NoEncode<"$ea_result">;
701 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
702 "lfd $rD, $addr", LdStLFD,
703 []>, RegConstraint<"$addr.reg = $ea_result">,
704 NoEncode<"$ea_result">;
708 // Indexed (r+r) Loads.
710 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
711 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
712 "lbzx $rD, $src", LdStGeneral,
713 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
714 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
715 "lhax $rD, $src", LdStLHA,
716 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
717 PPC970_DGroup_Cracked;
718 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
719 "lhzx $rD, $src", LdStGeneral,
720 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
721 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
722 "lwzx $rD, $src", LdStGeneral,
723 [(set GPRC:$rD, (load xaddr:$src))]>;
726 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
727 "lhbrx $rD, $src", LdStGeneral,
728 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i16))]>;
729 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
730 "lwbrx $rD, $src", LdStGeneral,
731 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>;
733 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
734 "lfsx $frD, $src", LdStLFDU,
735 [(set F4RC:$frD, (load xaddr:$src))]>;
736 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
737 "lfdx $frD, $src", LdStLFDU,
738 [(set F8RC:$frD, (load xaddr:$src))]>;
741 //===----------------------------------------------------------------------===//
742 // PPC32 Store Instructions.
745 // Unindexed (r+i) Stores.
746 let PPC970_Unit = 2 in {
747 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
748 "stb $rS, $src", LdStGeneral,
749 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
750 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
751 "sth $rS, $src", LdStGeneral,
752 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
753 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
754 "stw $rS, $src", LdStGeneral,
755 [(store GPRC:$rS, iaddr:$src)]>;
756 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
757 "stfs $rS, $dst", LdStUX,
758 [(store F4RC:$rS, iaddr:$dst)]>;
759 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
760 "stfd $rS, $dst", LdStUX,
761 [(store F8RC:$rS, iaddr:$dst)]>;
764 // Unindexed (r+i) Stores with Update (preinc).
765 let PPC970_Unit = 2 in {
766 def STBU : DForm_1<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
767 symbolLo:$ptroff, ptr_rc:$ptrreg),
768 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
769 [(set ptr_rc:$ea_res,
770 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
771 iaddroff:$ptroff))]>,
772 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
773 def STHU : DForm_1<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
774 symbolLo:$ptroff, ptr_rc:$ptrreg),
775 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
776 [(set ptr_rc:$ea_res,
777 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
778 iaddroff:$ptroff))]>,
779 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
780 def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
781 symbolLo:$ptroff, ptr_rc:$ptrreg),
782 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
783 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
784 iaddroff:$ptroff))]>,
785 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
786 def STFSU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
787 symbolLo:$ptroff, ptr_rc:$ptrreg),
788 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral,
789 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
790 iaddroff:$ptroff))]>,
791 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
792 def STFDU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
793 symbolLo:$ptroff, ptr_rc:$ptrreg),
794 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral,
795 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
796 iaddroff:$ptroff))]>,
797 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
801 // Indexed (r+r) Stores.
803 let PPC970_Unit = 2 in {
804 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
805 "stbx $rS, $dst", LdStGeneral,
806 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
807 PPC970_DGroup_Cracked;
808 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
809 "sthx $rS, $dst", LdStGeneral,
810 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
811 PPC970_DGroup_Cracked;
812 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
813 "stwx $rS, $dst", LdStGeneral,
814 [(store GPRC:$rS, xaddr:$dst)]>,
815 PPC970_DGroup_Cracked;
817 let mayStore = 1 in {
818 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
819 "stwux $rS, $rA, $rB", LdStGeneral,
822 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
823 "sthbrx $rS, $dst", LdStGeneral,
824 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>,
825 PPC970_DGroup_Cracked;
826 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
827 "stwbrx $rS, $dst", LdStGeneral,
828 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i32)]>,
829 PPC970_DGroup_Cracked;
831 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
832 "stfiwx $frS, $dst", LdStUX,
833 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
835 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
836 "stfsx $frS, $dst", LdStUX,
837 [(store F4RC:$frS, xaddr:$dst)]>;
838 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
839 "stfdx $frS, $dst", LdStUX,
840 [(store F8RC:$frS, xaddr:$dst)]>;
843 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
847 //===----------------------------------------------------------------------===//
848 // PPC32 Arithmetic Instructions.
851 let PPC970_Unit = 1 in { // FXU Operations.
852 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
853 "addi $rD, $rA, $imm", IntGeneral,
854 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
855 let Defs = [CARRY] in {
856 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
857 "addic $rD, $rA, $imm", IntGeneral,
858 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
859 PPC970_DGroup_Cracked;
860 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
861 "addic. $rD, $rA, $imm", IntGeneral,
864 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
865 "addis $rD, $rA, $imm", IntGeneral,
866 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
867 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
868 "la $rD, $sym($rA)", IntGeneral,
869 [(set GPRC:$rD, (add GPRC:$rA,
870 (PPClo tglobaladdr:$sym, 0)))]>;
871 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
872 "mulli $rD, $rA, $imm", IntMulLI,
873 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
874 let Defs = [CARRY] in {
875 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
876 "subfic $rD, $rA, $imm", IntGeneral,
877 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
880 let isReMaterializable = 1 in {
881 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
882 "li $rD, $imm", IntGeneral,
883 [(set GPRC:$rD, immSExt16:$imm)]>;
884 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
885 "lis $rD, $imm", IntGeneral,
886 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
890 let PPC970_Unit = 1 in { // FXU Operations.
891 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
892 "andi. $dst, $src1, $src2", IntGeneral,
893 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
895 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
896 "andis. $dst, $src1, $src2", IntGeneral,
897 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
899 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
900 "ori $dst, $src1, $src2", IntGeneral,
901 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
902 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
903 "oris $dst, $src1, $src2", IntGeneral,
904 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
905 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
906 "xori $dst, $src1, $src2", IntGeneral,
907 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
908 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
909 "xoris $dst, $src1, $src2", IntGeneral,
910 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
911 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral,
913 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
914 "cmpwi $crD, $rA, $imm", IntCompare>;
915 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
916 "cmplwi $dst, $src1, $src2", IntCompare>;
920 let PPC970_Unit = 1 in { // FXU Operations.
921 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
922 "nand $rA, $rS, $rB", IntGeneral,
923 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
924 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
925 "and $rA, $rS, $rB", IntGeneral,
926 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
927 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
928 "andc $rA, $rS, $rB", IntGeneral,
929 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
930 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
931 "or $rA, $rS, $rB", IntGeneral,
932 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
933 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
934 "nor $rA, $rS, $rB", IntGeneral,
935 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
936 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
937 "orc $rA, $rS, $rB", IntGeneral,
938 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
939 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
940 "eqv $rA, $rS, $rB", IntGeneral,
941 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
942 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
943 "xor $rA, $rS, $rB", IntGeneral,
944 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
945 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
946 "slw $rA, $rS, $rB", IntGeneral,
947 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
948 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
949 "srw $rA, $rS, $rB", IntGeneral,
950 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
951 let Defs = [CARRY] in {
952 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
953 "sraw $rA, $rS, $rB", IntShift,
954 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
958 let PPC970_Unit = 1 in { // FXU Operations.
959 let Defs = [CARRY] in {
960 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
961 "srawi $rA, $rS, $SH", IntShift,
962 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
964 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
965 "cntlzw $rA, $rS", IntGeneral,
966 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
967 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
968 "extsb $rA, $rS", IntGeneral,
969 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
970 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
971 "extsh $rA, $rS", IntGeneral,
972 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
974 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
975 "cmpw $crD, $rA, $rB", IntCompare>;
976 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
977 "cmplw $crD, $rA, $rB", IntCompare>;
979 let PPC970_Unit = 3 in { // FPU Operations.
980 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
981 // "fcmpo $crD, $fA, $fB", FPCompare>;
982 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
983 "fcmpu $crD, $fA, $fB", FPCompare>;
984 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
985 "fcmpu $crD, $fA, $fB", FPCompare>;
988 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
989 "fctiwz $frD, $frB", FPGeneral,
990 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
991 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
992 "frsp $frD, $frB", FPGeneral,
993 [(set F4RC:$frD, (fround F8RC:$frB))]>;
994 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
995 "fsqrt $frD, $frB", FPSqrt,
996 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
997 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
998 "fsqrts $frD, $frB", FPSqrt,
999 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
1003 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1004 /// often coalesced away and we don't want the dispatch group builder to think
1005 /// that they will fill slots (which could cause the load of a LSU reject to
1006 /// sneak into a d-group with a store).
1007 def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
1008 "fmr $frD, $frB", FPGeneral,
1009 []>, // (set F4RC:$frD, F4RC:$frB)
1012 let PPC970_Unit = 3 in { // FPU Operations.
1013 // These are artificially split into two different forms, for 4/8 byte FP.
1014 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
1015 "fabs $frD, $frB", FPGeneral,
1016 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
1017 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
1018 "fabs $frD, $frB", FPGeneral,
1019 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
1020 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
1021 "fnabs $frD, $frB", FPGeneral,
1022 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
1023 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
1024 "fnabs $frD, $frB", FPGeneral,
1025 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
1026 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
1027 "fneg $frD, $frB", FPGeneral,
1028 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
1029 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
1030 "fneg $frD, $frB", FPGeneral,
1031 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
1035 // XL-Form instructions. condition register logical ops.
1037 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
1038 "mcrf $BF, $BFA", BrMCR>,
1039 PPC970_DGroup_First, PPC970_Unit_CRU;
1041 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
1042 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1043 "creqv $CRD, $CRA, $CRB", BrCR,
1046 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
1047 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1048 "cror $CRD, $CRA, $CRB", BrCR,
1051 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
1052 "creqv $dst, $dst, $dst", BrCR,
1055 // XFX-Form instructions. Instructions that deal with SPRs.
1057 let Uses = [CTR] in {
1058 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
1059 "mfctr $rT", SprMFSPR>,
1060 PPC970_DGroup_First, PPC970_Unit_FXU;
1062 let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in {
1063 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
1064 "mtctr $rS", SprMTSPR>,
1065 PPC970_DGroup_First, PPC970_Unit_FXU;
1068 let Defs = [LR] in {
1069 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1070 "mtlr $rS", SprMTSPR>,
1071 PPC970_DGroup_First, PPC970_Unit_FXU;
1073 let Uses = [LR] in {
1074 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1075 "mflr $rT", SprMFSPR>,
1076 PPC970_DGroup_First, PPC970_Unit_FXU;
1079 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1080 // a GPR on the PPC970. As such, copies in and out have the same performance
1081 // characteristics as an OR instruction.
1082 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1083 "mtspr 256, $rS", IntGeneral>,
1084 PPC970_DGroup_Single, PPC970_Unit_FXU;
1085 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1086 "mfspr $rT, 256", IntGeneral>,
1087 PPC970_DGroup_First, PPC970_Unit_FXU;
1089 def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS),
1090 "mtcrf $FXM, $rS", BrMCRX>,
1091 PPC970_MicroCode, PPC970_Unit_CRU;
1093 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
1094 // declaring that here gives the local register allocator problems with this:
1096 // MFCR <kill of whatever preg got assigned to vreg>
1097 // while not declaring it breaks DeadMachineInstructionElimination.
1098 // As it turns out, in all cases where we currently use this,
1099 // we're only interested in one subregister of it. Represent this in the
1100 // instruction to keep the register allocator from becoming confused.
1102 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
1103 def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1105 PPC970_MicroCode, PPC970_Unit_CRU;
1107 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
1108 "mfcr $rT", SprMFCR>,
1109 PPC970_MicroCode, PPC970_Unit_CRU;
1111 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1112 "mfcr $rT, $FXM", SprMFCR>,
1113 PPC970_DGroup_First, PPC970_Unit_CRU;
1115 // Instructions to manipulate FPSCR. Only long double handling uses these.
1116 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
1118 let Uses = [RM], Defs = [RM] in {
1119 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1120 "mtfsb0 $FM", IntMTFSB0,
1121 [(PPCmtfsb0 (i32 imm:$FM))]>,
1122 PPC970_DGroup_Single, PPC970_Unit_FPU;
1123 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1124 "mtfsb1 $FM", IntMTFSB0,
1125 [(PPCmtfsb1 (i32 imm:$FM))]>,
1126 PPC970_DGroup_Single, PPC970_Unit_FPU;
1127 // MTFSF does not actually produce an FP result. We pretend it copies
1128 // input reg B to the output. If we didn't do this it would look like the
1129 // instruction had no outputs (because we aren't modelling the FPSCR) and
1130 // it would be deleted.
1131 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
1132 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
1133 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
1134 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM),
1135 F8RC:$rT, F8RC:$FRB))]>,
1136 PPC970_DGroup_Single, PPC970_Unit_FPU;
1138 let Uses = [RM] in {
1139 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1140 "mffs $rT", IntMFFS,
1141 [(set F8RC:$rT, (PPCmffs))]>,
1142 PPC970_DGroup_Single, PPC970_Unit_FPU;
1143 def FADDrtz: AForm_2<63, 21,
1144 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1145 "fadd $FRT, $FRA, $FRB", FPGeneral,
1146 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>,
1147 PPC970_DGroup_Single, PPC970_Unit_FPU;
1151 let PPC970_Unit = 1 in { // FXU Operations.
1153 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1155 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1156 "add $rT, $rA, $rB", IntGeneral,
1157 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
1158 let Defs = [CARRY] in {
1159 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1160 "addc $rT, $rA, $rB", IntGeneral,
1161 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
1162 PPC970_DGroup_Cracked;
1164 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1165 "divw $rT, $rA, $rB", IntDivW,
1166 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
1167 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1168 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1169 "divwu $rT, $rA, $rB", IntDivW,
1170 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
1171 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1172 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1173 "mulhw $rT, $rA, $rB", IntMulHW,
1174 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
1175 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1176 "mulhwu $rT, $rA, $rB", IntMulHWU,
1177 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
1178 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1179 "mullw $rT, $rA, $rB", IntMulHW,
1180 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
1181 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1182 "subf $rT, $rA, $rB", IntGeneral,
1183 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
1184 let Defs = [CARRY] in {
1185 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1186 "subfc $rT, $rA, $rB", IntGeneral,
1187 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
1188 PPC970_DGroup_Cracked;
1190 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1191 "neg $rT, $rA", IntGeneral,
1192 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
1193 let Uses = [CARRY], Defs = [CARRY] in {
1194 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1195 "adde $rT, $rA, $rB", IntGeneral,
1196 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
1197 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1198 "addme $rT, $rA", IntGeneral,
1199 [(set GPRC:$rT, (adde GPRC:$rA, -1))]>;
1200 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1201 "addze $rT, $rA", IntGeneral,
1202 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
1203 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1204 "subfe $rT, $rA, $rB", IntGeneral,
1205 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
1206 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1207 "subfme $rT, $rA", IntGeneral,
1208 [(set GPRC:$rT, (sube -1, GPRC:$rA))]>;
1209 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1210 "subfze $rT, $rA", IntGeneral,
1211 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
1215 // A-Form instructions. Most of the instructions executed in the FPU are of
1218 let PPC970_Unit = 3 in { // FPU Operations.
1219 let Uses = [RM] in {
1220 def FMADD : AForm_1<63, 29,
1221 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1222 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1223 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1225 Requires<[FPContractions]>;
1226 def FMADDS : AForm_1<59, 29,
1227 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1228 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1229 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1231 Requires<[FPContractions]>;
1232 def FMSUB : AForm_1<63, 28,
1233 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1234 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1235 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1237 Requires<[FPContractions]>;
1238 def FMSUBS : AForm_1<59, 28,
1239 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1240 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1241 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1243 Requires<[FPContractions]>;
1244 def FNMADD : AForm_1<63, 31,
1245 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1246 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1247 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1249 Requires<[FPContractions]>;
1250 def FNMADDS : AForm_1<59, 31,
1251 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1252 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1253 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1255 Requires<[FPContractions]>;
1256 def FNMSUB : AForm_1<63, 30,
1257 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1258 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1259 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1261 Requires<[FPContractions]>;
1262 def FNMSUBS : AForm_1<59, 30,
1263 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1264 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1265 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1267 Requires<[FPContractions]>;
1269 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1270 // having 4 of these, force the comparison to always be an 8-byte double (code
1271 // should use an FMRSD if the input comparison value really wants to be a float)
1272 // and 4/8 byte forms for the result and operand type..
1273 def FSELD : AForm_1<63, 23,
1274 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1275 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1276 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
1277 def FSELS : AForm_1<63, 23,
1278 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1279 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1280 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
1281 let Uses = [RM] in {
1282 def FADD : AForm_2<63, 21,
1283 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1284 "fadd $FRT, $FRA, $FRB", FPGeneral,
1285 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
1286 def FADDS : AForm_2<59, 21,
1287 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1288 "fadds $FRT, $FRA, $FRB", FPGeneral,
1289 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
1290 def FDIV : AForm_2<63, 18,
1291 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1292 "fdiv $FRT, $FRA, $FRB", FPDivD,
1293 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1294 def FDIVS : AForm_2<59, 18,
1295 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1296 "fdivs $FRT, $FRA, $FRB", FPDivS,
1297 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1298 def FMUL : AForm_3<63, 25,
1299 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1300 "fmul $FRT, $FRA, $FRB", FPFused,
1301 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
1302 def FMULS : AForm_3<59, 25,
1303 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1304 "fmuls $FRT, $FRA, $FRB", FPGeneral,
1305 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
1306 def FSUB : AForm_2<63, 20,
1307 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1308 "fsub $FRT, $FRA, $FRB", FPGeneral,
1309 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1310 def FSUBS : AForm_2<59, 20,
1311 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1312 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1313 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1317 let PPC970_Unit = 1 in { // FXU Operations.
1318 // M-Form instructions. rotate and mask instructions.
1320 let isCommutable = 1 in {
1321 // RLWIMI can be commuted if the rotate amount is zero.
1322 def RLWIMI : MForm_2<20,
1323 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1324 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1325 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1328 def RLWINM : MForm_2<21,
1329 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1330 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1332 def RLWINMo : MForm_2<21,
1333 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1334 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1335 []>, isDOT, PPC970_DGroup_Cracked;
1336 def RLWNM : MForm_2<23,
1337 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1338 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1343 //===----------------------------------------------------------------------===//
1344 // PowerPC Instruction Patterns
1347 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1348 def : Pat<(i32 imm:$imm),
1349 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1351 // Implement the 'not' operation with the NOR instruction.
1352 def NOT : Pat<(not GPRC:$in),
1353 (NOR GPRC:$in, GPRC:$in)>;
1355 // ADD an arbitrary immediate.
1356 def : Pat<(add GPRC:$in, imm:$imm),
1357 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1358 // OR an arbitrary immediate.
1359 def : Pat<(or GPRC:$in, imm:$imm),
1360 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1361 // XOR an arbitrary immediate.
1362 def : Pat<(xor GPRC:$in, imm:$imm),
1363 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1365 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1366 (SUBFIC GPRC:$in, imm:$imm)>;
1369 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1370 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1371 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1372 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1375 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1376 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1377 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1378 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1381 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1382 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1385 def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)),
1386 (BL_Darwin tglobaladdr:$dst)>;
1387 def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)),
1388 (BL_Darwin texternalsym:$dst)>;
1389 def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)),
1390 (BL_SVR4 tglobaladdr:$dst)>;
1391 def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)),
1392 (BL_SVR4 texternalsym:$dst)>;
1395 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1396 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1398 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1399 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1401 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1402 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1406 // Hi and Lo for Darwin Global Addresses.
1407 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1408 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1409 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1410 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1411 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1412 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1413 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
1414 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
1415 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1416 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1417 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1418 (ADDIS GPRC:$in, tconstpool:$g)>;
1419 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1420 (ADDIS GPRC:$in, tjumptable:$g)>;
1421 def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)),
1422 (ADDIS GPRC:$in, tblockaddress:$g)>;
1424 // Fused negative multiply subtract, alternate pattern
1425 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1426 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1427 Requires<[FPContractions]>;
1428 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1429 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1430 Requires<[FPContractions]>;
1432 // Standard shifts. These are represented separately from the real shifts above
1433 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1435 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1436 (SRAW GPRC:$rS, GPRC:$rB)>;
1437 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1438 (SRW GPRC:$rS, GPRC:$rB)>;
1439 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1440 (SLW GPRC:$rS, GPRC:$rB)>;
1442 def : Pat<(zextloadi1 iaddr:$src),
1444 def : Pat<(zextloadi1 xaddr:$src),
1446 def : Pat<(extloadi1 iaddr:$src),
1448 def : Pat<(extloadi1 xaddr:$src),
1450 def : Pat<(extloadi8 iaddr:$src),
1452 def : Pat<(extloadi8 xaddr:$src),
1454 def : Pat<(extloadi16 iaddr:$src),
1456 def : Pat<(extloadi16 xaddr:$src),
1458 def : Pat<(f64 (extloadf32 iaddr:$src)),
1459 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
1460 def : Pat<(f64 (extloadf32 xaddr:$src)),
1461 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
1463 def : Pat<(f64 (fextend F4RC:$src)),
1464 (COPY_TO_REGCLASS F4RC:$src, F8RC)>;
1467 def : Pat<(membarrier (i32 imm /*ll*/),
1471 (i32 imm /*device*/)),
1474 include "PPCInstrAltivec.td"
1475 include "PPCInstr64Bit.td"