1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
26 def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
38 def SDT_PPClbrx : SDTypeProfile<1, 2, [
39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
41 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPClarx : SDTypeProfile<1, 1, [
46 SDTCisInt<0>, SDTCisPtrTy<1>
48 def SDT_PPCstcx : SDTypeProfile<0, 2, [
49 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
53 SDTCisPtrTy<0>, SDTCisVT<1, i32>
57 //===----------------------------------------------------------------------===//
58 // PowerPC specific DAG Nodes.
61 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
62 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
63 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
64 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
65 [SDNPHasChain, SDNPMayStore]>;
67 // This sequence is used for long double->int conversions. It changes the
68 // bits in the FPSCR which is not modelled.
69 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
71 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
72 [SDNPInGlue, SDNPOutGlue]>;
73 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
74 [SDNPInGlue, SDNPOutGlue]>;
75 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
76 [SDNPInGlue, SDNPOutGlue]>;
77 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
78 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
82 def PPCfsel : SDNode<"PPCISD::FSEL",
83 // Type constraint for fsel.
84 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
85 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
87 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
88 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
89 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
90 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
91 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
93 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
94 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
96 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
97 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
98 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
99 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
100 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
101 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
102 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
103 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
105 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
107 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
109 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
110 // amounts. These nodes are generated by the multi-precision shift code.
111 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
112 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
113 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
115 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
116 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
117 [SDNPHasChain, SDNPMayStore]>;
119 // These are target-independent nodes, but have target-specific formats.
120 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
121 [SDNPHasChain, SDNPOutGlue]>;
122 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
123 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
125 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
126 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
127 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
129 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
130 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
132 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
133 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
134 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
135 [SDNPHasChain, SDNPSideEffect,
136 SDNPInGlue, SDNPOutGlue]>;
137 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
138 [SDNPHasChain, SDNPSideEffect,
139 SDNPInGlue, SDNPOutGlue]>;
140 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
141 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
142 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
143 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
146 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
147 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
149 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
150 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
152 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
153 SDTypeProfile<1, 1, [SDTCisInt<0>,
155 [SDNPHasChain, SDNPSideEffect]>;
156 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
157 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
158 [SDNPHasChain, SDNPSideEffect]>;
160 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
161 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
163 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
164 [SDNPHasChain, SDNPOptInGlue]>;
166 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
167 [SDNPHasChain, SDNPMayLoad]>;
168 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
169 [SDNPHasChain, SDNPMayStore]>;
171 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
172 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
173 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
174 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
175 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
177 // Instructions to support atomic operations
178 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
179 [SDNPHasChain, SDNPMayLoad]>;
180 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
181 [SDNPHasChain, SDNPMayStore]>;
183 // Instructions to support medium and large code model
184 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
185 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
186 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
189 // Instructions to support dynamic alloca.
190 def SDTDynOp : SDTypeProfile<1, 2, []>;
191 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
193 //===----------------------------------------------------------------------===//
194 // PowerPC specific transformation functions and pattern fragments.
197 def SHL32 : SDNodeXForm<imm, [{
198 // Transformation function: 31 - imm
199 return getI32Imm(31 - N->getZExtValue());
202 def SRL32 : SDNodeXForm<imm, [{
203 // Transformation function: 32 - imm
204 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
207 def LO16 : SDNodeXForm<imm, [{
208 // Transformation function: get the low 16 bits.
209 return getI32Imm((unsigned short)N->getZExtValue());
212 def HI16 : SDNodeXForm<imm, [{
213 // Transformation function: shift the immediate value down into the low bits.
214 return getI32Imm((unsigned)N->getZExtValue() >> 16);
217 def HA16 : SDNodeXForm<imm, [{
218 // Transformation function: shift the immediate value down into the low bits.
219 signed int Val = N->getZExtValue();
220 return getI32Imm((Val - (signed short)Val) >> 16);
222 def MB : SDNodeXForm<imm, [{
223 // Transformation function: get the start bit of a mask
225 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
226 return getI32Imm(mb);
229 def ME : SDNodeXForm<imm, [{
230 // Transformation function: get the end bit of a mask
232 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
233 return getI32Imm(me);
235 def maskimm32 : PatLeaf<(imm), [{
236 // maskImm predicate - True if immediate is a run of ones.
238 if (N->getValueType(0) == MVT::i32)
239 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
244 def immSExt16 : PatLeaf<(imm), [{
245 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
246 // field. Used by instructions like 'addi'.
247 if (N->getValueType(0) == MVT::i32)
248 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
250 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
252 def immZExt16 : PatLeaf<(imm), [{
253 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
254 // field. Used by instructions like 'ori'.
255 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
258 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
259 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
260 // identical in 32-bit mode, but in 64-bit mode, they return true if the
261 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
263 def imm16ShiftedZExt : PatLeaf<(imm), [{
264 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
265 // immediate are set. Used by instructions like 'xoris'.
266 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
269 def imm16ShiftedSExt : PatLeaf<(imm), [{
270 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
271 // immediate are set. Used by instructions like 'addis'. Identical to
272 // imm16ShiftedZExt in 32-bit mode.
273 if (N->getZExtValue() & 0xFFFF) return false;
274 if (N->getValueType(0) == MVT::i32)
276 // For 64-bit, make sure it is sext right.
277 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
280 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
281 // restricted memrix (offset/4) constants are alignment sensitive. If these
282 // offsets are hidden behind TOC entries than the values of the lower-order
283 // bits cannot be checked directly. As a result, we need to also incorporate
284 // an alignment check into the relevant patterns.
286 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
287 return cast<LoadSDNode>(N)->getAlignment() >= 4;
289 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
290 (store node:$val, node:$ptr), [{
291 return cast<StoreSDNode>(N)->getAlignment() >= 4;
293 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
294 return cast<LoadSDNode>(N)->getAlignment() >= 4;
296 def aligned4pre_store : PatFrag<
297 (ops node:$val, node:$base, node:$offset),
298 (pre_store node:$val, node:$base, node:$offset), [{
299 return cast<StoreSDNode>(N)->getAlignment() >= 4;
302 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
303 return cast<LoadSDNode>(N)->getAlignment() < 4;
305 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
306 (store node:$val, node:$ptr), [{
307 return cast<StoreSDNode>(N)->getAlignment() < 4;
309 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
310 return cast<LoadSDNode>(N)->getAlignment() < 4;
313 //===----------------------------------------------------------------------===//
314 // PowerPC Flag Definitions.
316 class isPPC64 { bit PPC64 = 1; }
318 list<Register> Defs = [CR0];
322 class RegConstraint<string C> {
323 string Constraints = C;
325 class NoEncode<string E> {
326 string DisableEncoding = E;
330 //===----------------------------------------------------------------------===//
331 // PowerPC Operand Definitions.
333 def s5imm : Operand<i32> {
334 let PrintMethod = "printS5ImmOperand";
336 def u5imm : Operand<i32> {
337 let PrintMethod = "printU5ImmOperand";
339 def u6imm : Operand<i32> {
340 let PrintMethod = "printU6ImmOperand";
342 def s16imm : Operand<i32> {
343 let PrintMethod = "printS16ImmOperand";
345 def u16imm : Operand<i32> {
346 let PrintMethod = "printU16ImmOperand";
348 def directbrtarget : Operand<OtherVT> {
349 let PrintMethod = "printBranchOperand";
350 let EncoderMethod = "getDirectBrEncoding";
352 def condbrtarget : Operand<OtherVT> {
353 let PrintMethod = "printBranchOperand";
354 let EncoderMethod = "getCondBrEncoding";
356 def calltarget : Operand<iPTR> {
357 let EncoderMethod = "getDirectBrEncoding";
359 def aaddr : Operand<iPTR> {
360 let PrintMethod = "printAbsAddrOperand";
362 def symbolHi: Operand<i32> {
363 let PrintMethod = "printSymbolHi";
364 let EncoderMethod = "getHA16Encoding";
366 def symbolLo: Operand<i32> {
367 let PrintMethod = "printSymbolLo";
368 let EncoderMethod = "getLO16Encoding";
370 def crbitm: Operand<i8> {
371 let PrintMethod = "printcrbitm";
372 let EncoderMethod = "get_crbitm_encoding";
375 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
376 def ptr_rc_nor0 : PointerLikeRegClass<1>;
378 def dispRI : Operand<iPTR>;
379 def dispRIX : Operand<iPTR>;
381 def memri : Operand<iPTR> {
382 let PrintMethod = "printMemRegImm";
383 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
384 let EncoderMethod = "getMemRIEncoding";
386 def memrr : Operand<iPTR> {
387 let PrintMethod = "printMemRegReg";
388 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc:$offreg);
390 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
391 let PrintMethod = "printMemRegImmShifted";
392 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
393 let EncoderMethod = "getMemRIXEncoding";
396 // A single-register address. This is used with the SjLj
397 // pseudo-instructions.
398 def memr : Operand<iPTR> {
399 let MIOperandInfo = (ops ptr_rc:$ptrreg);
402 // PowerPC Predicate operand.
403 def pred : Operand<OtherVT> {
404 let PrintMethod = "printPredicateOperand";
405 let MIOperandInfo = (ops i32imm:$bibo, CRRC:$reg);
408 // Define PowerPC specific addressing mode.
409 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
410 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
411 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
412 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
414 // The address in a single register. This is used with the SjLj
415 // pseudo-instructions.
416 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
418 /// This is just the offset part of iaddr, used for preinc.
419 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
421 //===----------------------------------------------------------------------===//
422 // PowerPC Instruction Predicate Definitions.
423 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
424 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
425 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
427 //===----------------------------------------------------------------------===//
428 // PowerPC Instruction Definitions.
430 // Pseudo-instructions:
432 let hasCtrlDep = 1 in {
433 let Defs = [R1], Uses = [R1] in {
434 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
435 [(callseq_start timm:$amt)]>;
436 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
437 [(callseq_end timm:$amt1, timm:$amt2)]>;
440 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
441 "UPDATE_VRSAVE $rD, $rS", []>;
444 let Defs = [R1], Uses = [R1] in
445 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "#DYNALLOC",
447 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
449 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
450 // instruction selection into a branch sequence.
451 let usesCustomInserter = 1, // Expanded after instruction selection.
452 PPC970_Single = 1 in {
453 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
454 i32imm:$BROPC), "#SELECT_CC_I4",
456 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
457 i32imm:$BROPC), "#SELECT_CC_I8",
459 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
460 i32imm:$BROPC), "#SELECT_CC_F4",
462 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
463 i32imm:$BROPC), "#SELECT_CC_F8",
465 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
466 i32imm:$BROPC), "#SELECT_CC_VRRC",
470 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
471 // scavenge a register for it.
473 def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F),
476 // RESTORE_CR - Indicate that we're restoring the CR register (previously
477 // spilled), so we'll need to scavenge a register for it.
479 def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F),
482 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
483 let isReturn = 1, Uses = [LR, RM] in
484 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", BrB,
486 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in
487 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
491 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
494 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
495 let isBarrier = 1 in {
496 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
501 // BCC represents an arbitrary conditional branch on a predicate.
502 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
503 // a two-value operand where a dag node expects two operands. :(
504 let isCodeGenOnly = 1 in
505 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
506 "b${cond:cc} ${cond:reg}, $dst"
507 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
509 let Defs = [CTR], Uses = [CTR] in {
510 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
512 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
517 // The direct BCL used by the SjLj setjmp code.
518 let isCall = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
519 let Defs = [LR], Uses = [RM] in {
520 def BCL : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
525 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
526 // Convenient aliases for call instructions
528 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
529 "bl $func", BrB, []>; // See Pat patterns below.
530 def BLA : IForm<18, 1, 1, (outs), (ins aaddr:$func),
531 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>;
533 let Uses = [CTR, RM] in {
534 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
535 "bctrl", BrB, [(PPCbctrl)]>,
536 Requires<[In32BitMode]>;
540 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
541 def TCRETURNdi :Pseudo< (outs),
542 (ins calltarget:$dst, i32imm:$offset),
543 "#TC_RETURNd $dst $offset",
547 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
548 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
549 "#TC_RETURNa $func $offset",
550 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
552 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
553 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
554 "#TC_RETURNr $dst $offset",
558 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
559 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
560 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
561 Requires<[In32BitMode]>;
565 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
566 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
567 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
572 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
573 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
574 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
578 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
579 usesCustomInserter = 1 in {
580 def EH_SjLj_SetJmp32 : Pseudo<(outs GPRC:$dst), (ins memr:$buf),
582 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
583 Requires<[In32BitMode]>;
584 let isTerminator = 1 in
585 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
586 "#EH_SJLJ_LONGJMP32",
587 [(PPCeh_sjlj_longjmp addr:$buf)]>,
588 Requires<[In32BitMode]>;
591 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
592 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
593 "#EH_SjLj_Setup\t$dst", []>;
596 // DCB* instructions.
597 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
598 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
599 PPC970_DGroup_Single;
600 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
601 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
602 PPC970_DGroup_Single;
603 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
604 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
605 PPC970_DGroup_Single;
606 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
607 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
608 PPC970_DGroup_Single;
609 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
610 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
611 PPC970_DGroup_Single;
612 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
613 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
614 PPC970_DGroup_Single;
615 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
616 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
617 PPC970_DGroup_Single;
618 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
619 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
620 PPC970_DGroup_Single;
622 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
626 let usesCustomInserter = 1 in {
627 let Defs = [CR0] in {
628 def ATOMIC_LOAD_ADD_I8 : Pseudo<
629 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I8",
630 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
631 def ATOMIC_LOAD_SUB_I8 : Pseudo<
632 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I8",
633 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
634 def ATOMIC_LOAD_AND_I8 : Pseudo<
635 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I8",
636 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
637 def ATOMIC_LOAD_OR_I8 : Pseudo<
638 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I8",
639 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
640 def ATOMIC_LOAD_XOR_I8 : Pseudo<
641 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "ATOMIC_LOAD_XOR_I8",
642 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
643 def ATOMIC_LOAD_NAND_I8 : Pseudo<
644 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I8",
645 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
646 def ATOMIC_LOAD_ADD_I16 : Pseudo<
647 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I16",
648 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
649 def ATOMIC_LOAD_SUB_I16 : Pseudo<
650 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I16",
651 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
652 def ATOMIC_LOAD_AND_I16 : Pseudo<
653 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I16",
654 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
655 def ATOMIC_LOAD_OR_I16 : Pseudo<
656 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I16",
657 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
658 def ATOMIC_LOAD_XOR_I16 : Pseudo<
659 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I16",
660 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
661 def ATOMIC_LOAD_NAND_I16 : Pseudo<
662 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I16",
663 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
664 def ATOMIC_LOAD_ADD_I32 : Pseudo<
665 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I32",
666 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
667 def ATOMIC_LOAD_SUB_I32 : Pseudo<
668 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I32",
669 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
670 def ATOMIC_LOAD_AND_I32 : Pseudo<
671 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I32",
672 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
673 def ATOMIC_LOAD_OR_I32 : Pseudo<
674 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I32",
675 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
676 def ATOMIC_LOAD_XOR_I32 : Pseudo<
677 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I32",
678 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
679 def ATOMIC_LOAD_NAND_I32 : Pseudo<
680 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I32",
681 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
683 def ATOMIC_CMP_SWAP_I8 : Pseudo<
684 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I8",
685 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
686 def ATOMIC_CMP_SWAP_I16 : Pseudo<
687 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
688 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
689 def ATOMIC_CMP_SWAP_I32 : Pseudo<
690 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
691 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
693 def ATOMIC_SWAP_I8 : Pseudo<
694 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_i8",
695 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
696 def ATOMIC_SWAP_I16 : Pseudo<
697 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I16",
698 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
699 def ATOMIC_SWAP_I32 : Pseudo<
700 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I32",
701 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
705 // Instructions to support atomic operations
706 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
707 "lwarx $rD, $src", LdStLWARX,
708 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
711 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
712 "stwcx. $rS, $dst", LdStSTWCX,
713 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
716 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
717 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>;
719 //===----------------------------------------------------------------------===//
720 // PPC32 Load Instructions.
723 // Unindexed (r+i) Loads.
724 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
725 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
726 "lbz $rD, $src", LdStLoad,
727 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
728 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
729 "lha $rD, $src", LdStLHA,
730 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
731 PPC970_DGroup_Cracked;
732 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
733 "lhz $rD, $src", LdStLoad,
734 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
735 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
736 "lwz $rD, $src", LdStLoad,
737 [(set i32:$rD, (load iaddr:$src))]>;
739 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
740 "lfs $rD, $src", LdStLFD,
741 [(set f32:$rD, (load iaddr:$src))]>;
742 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
743 "lfd $rD, $src", LdStLFD,
744 [(set f64:$rD, (load iaddr:$src))]>;
747 // Unindexed (r+i) Loads with Update (preinc).
749 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
750 "lbzu $rD, $addr", LdStLoadUpd,
751 []>, RegConstraint<"$addr.reg = $ea_result">,
752 NoEncode<"$ea_result">;
754 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
755 "lhau $rD, $addr", LdStLHAU,
756 []>, RegConstraint<"$addr.reg = $ea_result">,
757 NoEncode<"$ea_result">;
759 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
760 "lhzu $rD, $addr", LdStLoadUpd,
761 []>, RegConstraint<"$addr.reg = $ea_result">,
762 NoEncode<"$ea_result">;
764 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
765 "lwzu $rD, $addr", LdStLoadUpd,
766 []>, RegConstraint<"$addr.reg = $ea_result">,
767 NoEncode<"$ea_result">;
769 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
770 "lfsu $rD, $addr", LdStLFDU,
771 []>, RegConstraint<"$addr.reg = $ea_result">,
772 NoEncode<"$ea_result">;
774 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
775 "lfdu $rD, $addr", LdStLFDU,
776 []>, RegConstraint<"$addr.reg = $ea_result">,
777 NoEncode<"$ea_result">;
780 // Indexed (r+r) Loads with Update (preinc).
781 def LBZUX : XForm_1<31, 119, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
783 "lbzux $rD, $addr", LdStLoadUpd,
784 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
785 NoEncode<"$ea_result">;
787 def LHAUX : XForm_1<31, 375, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
789 "lhaux $rD, $addr", LdStLHAU,
790 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
791 NoEncode<"$ea_result">;
793 def LHZUX : XForm_1<31, 311, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
795 "lhzux $rD, $addr", LdStLoadUpd,
796 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
797 NoEncode<"$ea_result">;
799 def LWZUX : XForm_1<31, 55, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
801 "lwzux $rD, $addr", LdStLoadUpd,
802 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
803 NoEncode<"$ea_result">;
805 def LFSUX : XForm_1<31, 567, (outs F4RC:$rD, ptr_rc_nor0:$ea_result),
807 "lfsux $rD, $addr", LdStLFDU,
808 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
809 NoEncode<"$ea_result">;
811 def LFDUX : XForm_1<31, 631, (outs F8RC:$rD, ptr_rc_nor0:$ea_result),
813 "lfdux $rD, $addr", LdStLFDU,
814 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
815 NoEncode<"$ea_result">;
819 // Indexed (r+r) Loads.
821 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
822 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
823 "lbzx $rD, $src", LdStLoad,
824 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
825 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
826 "lhax $rD, $src", LdStLHA,
827 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
828 PPC970_DGroup_Cracked;
829 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
830 "lhzx $rD, $src", LdStLoad,
831 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
832 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
833 "lwzx $rD, $src", LdStLoad,
834 [(set i32:$rD, (load xaddr:$src))]>;
837 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
838 "lhbrx $rD, $src", LdStLoad,
839 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
840 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
841 "lwbrx $rD, $src", LdStLoad,
842 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
844 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
845 "lfsx $frD, $src", LdStLFD,
846 [(set f32:$frD, (load xaddr:$src))]>;
847 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
848 "lfdx $frD, $src", LdStLFD,
849 [(set f64:$frD, (load xaddr:$src))]>;
852 //===----------------------------------------------------------------------===//
853 // PPC32 Store Instructions.
856 // Unindexed (r+i) Stores.
857 let PPC970_Unit = 2 in {
858 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
859 "stb $rS, $src", LdStStore,
860 [(truncstorei8 i32:$rS, iaddr:$src)]>;
861 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
862 "sth $rS, $src", LdStStore,
863 [(truncstorei16 i32:$rS, iaddr:$src)]>;
864 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
865 "stw $rS, $src", LdStStore,
866 [(store i32:$rS, iaddr:$src)]>;
867 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
868 "stfs $rS, $dst", LdStSTFD,
869 [(store f32:$rS, iaddr:$dst)]>;
870 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
871 "stfd $rS, $dst", LdStSTFD,
872 [(store f64:$rS, iaddr:$dst)]>;
875 // Unindexed (r+i) Stores with Update (preinc).
876 let PPC970_Unit = 2, mayStore = 1 in {
877 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
878 "stbu $rS, $dst", LdStStoreUpd, []>,
879 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
880 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
881 "sthu $rS, $dst", LdStStoreUpd, []>,
882 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
883 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
884 "stwu $rS, $dst", LdStStoreUpd, []>,
885 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
886 def STFSU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memri:$dst),
887 "stfsu $rS, $dst", LdStSTFDU, []>,
888 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
889 def STFDU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memri:$dst),
890 "stfdu $rS, $dst", LdStSTFDU, []>,
891 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
894 // Patterns to match the pre-inc stores. We can't put the patterns on
895 // the instruction definitions directly as ISel wants the address base
896 // and offset to be separate operands, not a single complex operand.
897 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
898 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
899 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
900 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
901 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
902 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
903 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
904 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
905 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
906 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
908 // Indexed (r+r) Stores.
909 let PPC970_Unit = 2 in {
910 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
911 "stbx $rS, $dst", LdStStore,
912 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
913 PPC970_DGroup_Cracked;
914 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
915 "sthx $rS, $dst", LdStStore,
916 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
917 PPC970_DGroup_Cracked;
918 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
919 "stwx $rS, $dst", LdStStore,
920 [(store i32:$rS, xaddr:$dst)]>,
921 PPC970_DGroup_Cracked;
923 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
924 "sthbrx $rS, $dst", LdStStore,
925 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
926 PPC970_DGroup_Cracked;
927 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
928 "stwbrx $rS, $dst", LdStStore,
929 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
930 PPC970_DGroup_Cracked;
932 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
933 "stfiwx $frS, $dst", LdStSTFD,
934 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
936 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
937 "stfsx $frS, $dst", LdStSTFD,
938 [(store f32:$frS, xaddr:$dst)]>;
939 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
940 "stfdx $frS, $dst", LdStSTFD,
941 [(store f64:$frS, xaddr:$dst)]>;
944 // Indexed (r+r) Stores with Update (preinc).
945 let PPC970_Unit = 2, mayStore = 1 in {
946 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
947 "stbux $rS, $dst", LdStStoreUpd, []>,
948 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
949 PPC970_DGroup_Cracked;
950 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
951 "sthux $rS, $dst", LdStStoreUpd, []>,
952 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
953 PPC970_DGroup_Cracked;
954 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
955 "stwux $rS, $dst", LdStStoreUpd, []>,
956 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
957 PPC970_DGroup_Cracked;
958 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memrr:$dst),
959 "stfsux $rS, $dst", LdStSTFDU, []>,
960 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
961 PPC970_DGroup_Cracked;
962 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memrr:$dst),
963 "stfdux $rS, $dst", LdStSTFDU, []>,
964 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
965 PPC970_DGroup_Cracked;
968 // Patterns to match the pre-inc stores. We can't put the patterns on
969 // the instruction definitions directly as ISel wants the address base
970 // and offset to be separate operands, not a single complex operand.
971 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
972 (STBUX $rS, $ptrreg, $ptroff)>;
973 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
974 (STHUX $rS, $ptrreg, $ptroff)>;
975 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
976 (STWUX $rS, $ptrreg, $ptroff)>;
977 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
978 (STFSUX $rS, $ptrreg, $ptroff)>;
979 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
980 (STFDUX $rS, $ptrreg, $ptroff)>;
982 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
986 //===----------------------------------------------------------------------===//
987 // PPC32 Arithmetic Instructions.
990 let PPC970_Unit = 1 in { // FXU Operations.
991 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolLo:$imm),
992 "addi $rD, $rA, $imm", IntSimple,
993 [(set i32:$rD, (add i32:$rA, immSExt16:$imm))]>;
994 let Defs = [CARRY] in {
995 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
996 "addic $rD, $rA, $imm", IntGeneral,
997 [(set i32:$rD, (addc i32:$rA, immSExt16:$imm))]>,
998 PPC970_DGroup_Cracked;
999 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1000 "addic. $rD, $rA, $imm", IntGeneral,
1003 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolHi:$imm),
1004 "addis $rD, $rA, $imm", IntSimple,
1005 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1006 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolLo:$sym),
1007 "la $rD, $sym($rA)", IntGeneral,
1008 [(set i32:$rD, (add i32:$rA,
1009 (PPClo tglobaladdr:$sym, 0)))]>;
1010 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1011 "mulli $rD, $rA, $imm", IntMulLI,
1012 [(set i32:$rD, (mul i32:$rA, immSExt16:$imm))]>;
1013 let Defs = [CARRY] in {
1014 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1015 "subfic $rD, $rA, $imm", IntGeneral,
1016 [(set i32:$rD, (subc immSExt16:$imm, i32:$rA))]>;
1019 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1020 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
1021 "li $rD, $imm", IntSimple,
1022 [(set i32:$rD, immSExt16:$imm)]>;
1023 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
1024 "lis $rD, $imm", IntSimple,
1025 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1029 let PPC970_Unit = 1 in { // FXU Operations.
1030 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1031 "andi. $dst, $src1, $src2", IntGeneral,
1032 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1034 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1035 "andis. $dst, $src1, $src2", IntGeneral,
1036 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1038 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1039 "ori $dst, $src1, $src2", IntSimple,
1040 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1041 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1042 "oris $dst, $src1, $src2", IntSimple,
1043 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1044 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1045 "xori $dst, $src1, $src2", IntSimple,
1046 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1047 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1048 "xoris $dst, $src1, $src2", IntSimple,
1049 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1050 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple,
1052 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
1053 "cmpwi $crD, $rA, $imm", IntCompare>;
1054 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1055 "cmplwi $dst, $src1, $src2", IntCompare>;
1059 let PPC970_Unit = 1 in { // FXU Operations.
1060 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1061 "nand $rA, $rS, $rB", IntSimple,
1062 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1063 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1064 "and $rA, $rS, $rB", IntSimple,
1065 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1066 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1067 "andc $rA, $rS, $rB", IntSimple,
1068 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1069 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1070 "or $rA, $rS, $rB", IntSimple,
1071 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1072 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1073 "nor $rA, $rS, $rB", IntSimple,
1074 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1075 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1076 "orc $rA, $rS, $rB", IntSimple,
1077 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1078 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1079 "eqv $rA, $rS, $rB", IntSimple,
1080 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1081 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1082 "xor $rA, $rS, $rB", IntSimple,
1083 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1084 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1085 "slw $rA, $rS, $rB", IntGeneral,
1086 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1087 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1088 "srw $rA, $rS, $rB", IntGeneral,
1089 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1090 let Defs = [CARRY] in {
1091 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1092 "sraw $rA, $rS, $rB", IntShift,
1093 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1097 let PPC970_Unit = 1 in { // FXU Operations.
1098 let Defs = [CARRY] in {
1099 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
1100 "srawi $rA, $rS, $SH", IntShift,
1101 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1103 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
1104 "cntlzw $rA, $rS", IntGeneral,
1105 [(set i32:$rA, (ctlz i32:$rS))]>;
1106 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
1107 "extsb $rA, $rS", IntSimple,
1108 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1109 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
1110 "extsh $rA, $rS", IntSimple,
1111 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1113 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1114 "cmpw $crD, $rA, $rB", IntCompare>;
1115 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1116 "cmplw $crD, $rA, $rB", IntCompare>;
1118 let PPC970_Unit = 3 in { // FPU Operations.
1119 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1120 // "fcmpo $crD, $fA, $fB", FPCompare>;
1121 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
1122 "fcmpu $crD, $fA, $fB", FPCompare>;
1123 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
1124 "fcmpu $crD, $fA, $fB", FPCompare>;
1126 let Uses = [RM] in {
1127 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
1128 "fctiwz $frD, $frB", FPGeneral,
1129 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1130 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
1131 "frsp $frD, $frB", FPGeneral,
1132 [(set f32:$frD, (fround f64:$frB))]>;
1133 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
1134 "fsqrt $frD, $frB", FPSqrt,
1135 [(set f64:$frD, (fsqrt f64:$frB))]>;
1136 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
1137 "fsqrts $frD, $frB", FPSqrt,
1138 [(set f32:$frD, (fsqrt f32:$frB))]>;
1142 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1143 /// often coalesced away and we don't want the dispatch group builder to think
1144 /// that they will fill slots (which could cause the load of a LSU reject to
1145 /// sneak into a d-group with a store).
1146 def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
1147 "fmr $frD, $frB", FPGeneral,
1148 []>, // (set f32:$frD, f32:$frB)
1151 let PPC970_Unit = 3 in { // FPU Operations.
1152 // These are artificially split into two different forms, for 4/8 byte FP.
1153 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
1154 "fabs $frD, $frB", FPGeneral,
1155 [(set f32:$frD, (fabs f32:$frB))]>;
1156 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
1157 "fabs $frD, $frB", FPGeneral,
1158 [(set f64:$frD, (fabs f64:$frB))]>;
1159 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
1160 "fnabs $frD, $frB", FPGeneral,
1161 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1162 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
1163 "fnabs $frD, $frB", FPGeneral,
1164 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1165 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
1166 "fneg $frD, $frB", FPGeneral,
1167 [(set f32:$frD, (fneg f32:$frB))]>;
1168 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
1169 "fneg $frD, $frB", FPGeneral,
1170 [(set f64:$frD, (fneg f64:$frB))]>;
1174 // XL-Form instructions. condition register logical ops.
1176 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
1177 "mcrf $BF, $BFA", BrMCR>,
1178 PPC970_DGroup_First, PPC970_Unit_CRU;
1180 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
1181 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1182 "creqv $CRD, $CRA, $CRB", BrCR,
1185 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
1186 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1187 "cror $CRD, $CRA, $CRB", BrCR,
1190 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
1191 "creqv $dst, $dst, $dst", BrCR,
1194 def CRUNSET: XLForm_1_ext<19, 193, (outs CRBITRC:$dst), (ins),
1195 "crxor $dst, $dst, $dst", BrCR,
1198 let Defs = [CR1EQ], CRD = 6 in {
1199 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1200 "creqv 6, 6, 6", BrCR,
1203 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
1204 "crxor 6, 6, 6", BrCR,
1208 // XFX-Form instructions. Instructions that deal with SPRs.
1210 let Uses = [CTR] in {
1211 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
1212 "mfctr $rT", SprMFSPR>,
1213 PPC970_DGroup_First, PPC970_Unit_FXU;
1215 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
1216 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
1217 "mtctr $rS", SprMTSPR>,
1218 PPC970_DGroup_First, PPC970_Unit_FXU;
1221 let Defs = [LR] in {
1222 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1223 "mtlr $rS", SprMTSPR>,
1224 PPC970_DGroup_First, PPC970_Unit_FXU;
1226 let Uses = [LR] in {
1227 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1228 "mflr $rT", SprMFSPR>,
1229 PPC970_DGroup_First, PPC970_Unit_FXU;
1232 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1233 // a GPR on the PPC970. As such, copies in and out have the same performance
1234 // characteristics as an OR instruction.
1235 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1236 "mtspr 256, $rS", IntGeneral>,
1237 PPC970_DGroup_Single, PPC970_Unit_FXU;
1238 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1239 "mfspr $rT, 256", IntGeneral>,
1240 PPC970_DGroup_First, PPC970_Unit_FXU;
1242 let isCodeGenOnly = 1 in {
1243 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
1244 (outs VRSAVERC:$reg), (ins GPRC:$rS),
1245 "mtspr 256, $rS", IntGeneral>,
1246 PPC970_DGroup_Single, PPC970_Unit_FXU;
1247 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT),
1248 (ins VRSAVERC:$reg),
1249 "mfspr $rT, 256", IntGeneral>,
1250 PPC970_DGroup_First, PPC970_Unit_FXU;
1253 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
1254 // so we'll need to scavenge a register for it.
1256 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
1257 "#SPILL_VRSAVE", []>;
1259 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
1260 // spilled), so we'll need to scavenge a register for it.
1262 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
1263 "#RESTORE_VRSAVE", []>;
1265 def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS),
1266 "mtcrf $FXM, $rS", BrMCRX>,
1267 PPC970_MicroCode, PPC970_Unit_CRU;
1269 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
1270 // declaring that here gives the local register allocator problems with this:
1272 // MFCR <kill of whatever preg got assigned to vreg>
1273 // while not declaring it breaks DeadMachineInstructionElimination.
1274 // As it turns out, in all cases where we currently use this,
1275 // we're only interested in one subregister of it. Represent this in the
1276 // instruction to keep the register allocator from becoming confused.
1278 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
1279 def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1280 "#MFCRpseud", SprMFCR>,
1281 PPC970_MicroCode, PPC970_Unit_CRU;
1283 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
1284 "mfcr $rT", SprMFCR>,
1285 PPC970_MicroCode, PPC970_Unit_CRU;
1287 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1288 "mfocrf $rT, $FXM", SprMFCR>,
1289 PPC970_DGroup_First, PPC970_Unit_CRU;
1291 // Instructions to manipulate FPSCR. Only long double handling uses these.
1292 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
1294 let Uses = [RM], Defs = [RM] in {
1295 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1296 "mtfsb0 $FM", IntMTFSB0,
1297 [(PPCmtfsb0 (i32 imm:$FM))]>,
1298 PPC970_DGroup_Single, PPC970_Unit_FPU;
1299 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1300 "mtfsb1 $FM", IntMTFSB0,
1301 [(PPCmtfsb1 (i32 imm:$FM))]>,
1302 PPC970_DGroup_Single, PPC970_Unit_FPU;
1303 // MTFSF does not actually produce an FP result. We pretend it copies
1304 // input reg B to the output. If we didn't do this it would look like the
1305 // instruction had no outputs (because we aren't modelling the FPSCR) and
1306 // it would be deleted.
1307 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
1308 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
1309 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
1310 [(set f64:$FRA, (PPCmtfsf (i32 imm:$FM),
1311 f64:$rT, f64:$FRB))]>,
1312 PPC970_DGroup_Single, PPC970_Unit_FPU;
1314 let Uses = [RM] in {
1315 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1316 "mffs $rT", IntMFFS,
1317 [(set f64:$rT, (PPCmffs))]>,
1318 PPC970_DGroup_Single, PPC970_Unit_FPU;
1319 def FADDrtz: AForm_2<63, 21,
1320 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1321 "fadd $FRT, $FRA, $FRB", FPAddSub,
1322 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>,
1323 PPC970_DGroup_Single, PPC970_Unit_FPU;
1327 let PPC970_Unit = 1 in { // FXU Operations.
1329 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1331 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1332 "add $rT, $rA, $rB", IntSimple,
1333 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
1334 let Defs = [CARRY] in {
1335 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1336 "addc $rT, $rA, $rB", IntGeneral,
1337 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
1338 PPC970_DGroup_Cracked;
1340 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1341 "divw $rT, $rA, $rB", IntDivW,
1342 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
1343 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1344 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1345 "divwu $rT, $rA, $rB", IntDivW,
1346 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
1347 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1348 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1349 "mulhw $rT, $rA, $rB", IntMulHW,
1350 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
1351 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1352 "mulhwu $rT, $rA, $rB", IntMulHWU,
1353 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
1354 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1355 "mullw $rT, $rA, $rB", IntMulHW,
1356 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
1357 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1358 "subf $rT, $rA, $rB", IntGeneral,
1359 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
1360 let Defs = [CARRY] in {
1361 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1362 "subfc $rT, $rA, $rB", IntGeneral,
1363 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
1364 PPC970_DGroup_Cracked;
1366 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1367 "neg $rT, $rA", IntSimple,
1368 [(set i32:$rT, (ineg i32:$rA))]>;
1369 let Uses = [CARRY], Defs = [CARRY] in {
1370 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1371 "adde $rT, $rA, $rB", IntGeneral,
1372 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
1373 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1374 "addme $rT, $rA", IntGeneral,
1375 [(set i32:$rT, (adde i32:$rA, -1))]>;
1376 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1377 "addze $rT, $rA", IntGeneral,
1378 [(set i32:$rT, (adde i32:$rA, 0))]>;
1379 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1380 "subfe $rT, $rA, $rB", IntGeneral,
1381 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
1382 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1383 "subfme $rT, $rA", IntGeneral,
1384 [(set i32:$rT, (sube -1, i32:$rA))]>;
1385 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1386 "subfze $rT, $rA", IntGeneral,
1387 [(set i32:$rT, (sube 0, i32:$rA))]>;
1391 // A-Form instructions. Most of the instructions executed in the FPU are of
1394 let PPC970_Unit = 3 in { // FPU Operations.
1395 let Uses = [RM] in {
1396 def FMADD : AForm_1<63, 29,
1397 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1398 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1399 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
1400 def FMADDS : AForm_1<59, 29,
1401 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1402 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1403 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
1404 def FMSUB : AForm_1<63, 28,
1405 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1406 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1408 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
1409 def FMSUBS : AForm_1<59, 28,
1410 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1411 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1413 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
1414 def FNMADD : AForm_1<63, 31,
1415 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1416 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1418 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
1419 def FNMADDS : AForm_1<59, 31,
1420 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1421 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1423 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
1424 def FNMSUB : AForm_1<63, 30,
1425 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1426 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1427 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
1428 (fneg f64:$FRB))))]>;
1429 def FNMSUBS : AForm_1<59, 30,
1430 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1431 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1432 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
1433 (fneg f32:$FRB))))]>;
1435 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1436 // having 4 of these, force the comparison to always be an 8-byte double (code
1437 // should use an FMRSD if the input comparison value really wants to be a float)
1438 // and 4/8 byte forms for the result and operand type..
1439 def FSELD : AForm_1<63, 23,
1440 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1441 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1442 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
1443 def FSELS : AForm_1<63, 23,
1444 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1445 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1446 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
1447 let Uses = [RM] in {
1448 def FADD : AForm_2<63, 21,
1449 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1450 "fadd $FRT, $FRA, $FRB", FPAddSub,
1451 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
1452 def FADDS : AForm_2<59, 21,
1453 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1454 "fadds $FRT, $FRA, $FRB", FPGeneral,
1455 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
1456 def FDIV : AForm_2<63, 18,
1457 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1458 "fdiv $FRT, $FRA, $FRB", FPDivD,
1459 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
1460 def FDIVS : AForm_2<59, 18,
1461 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1462 "fdivs $FRT, $FRA, $FRB", FPDivS,
1463 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
1464 def FMUL : AForm_3<63, 25,
1465 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC),
1466 "fmul $FRT, $FRA, $FRC", FPFused,
1467 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
1468 def FMULS : AForm_3<59, 25,
1469 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC),
1470 "fmuls $FRT, $FRA, $FRC", FPGeneral,
1471 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
1472 def FSUB : AForm_2<63, 20,
1473 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1474 "fsub $FRT, $FRA, $FRB", FPAddSub,
1475 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
1476 def FSUBS : AForm_2<59, 20,
1477 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1478 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1479 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
1483 let PPC970_Unit = 1 in { // FXU Operations.
1484 def ISEL : AForm_4<31, 15,
1485 (outs GPRC:$rT), (ins GPRC_NOR0:$rA, GPRC:$rB, CRBITRC:$cond),
1486 "isel $rT, $rA, $rB, $cond", IntGeneral,
1490 let PPC970_Unit = 1 in { // FXU Operations.
1491 // M-Form instructions. rotate and mask instructions.
1493 let isCommutable = 1 in {
1494 // RLWIMI can be commuted if the rotate amount is zero.
1495 def RLWIMI : MForm_2<20,
1496 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1497 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1498 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1501 def RLWINM : MForm_2<21,
1502 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1503 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1505 def RLWINMo : MForm_2<21,
1506 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1507 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1508 []>, isDOT, PPC970_DGroup_Cracked;
1509 def RLWNM : MForm_2<23,
1510 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1511 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1516 //===----------------------------------------------------------------------===//
1517 // PowerPC Instruction Patterns
1520 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1521 def : Pat<(i32 imm:$imm),
1522 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1524 // Implement the 'not' operation with the NOR instruction.
1525 def NOT : Pat<(not i32:$in),
1528 // ADD an arbitrary immediate.
1529 def : Pat<(add i32:$in, imm:$imm),
1530 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1531 // OR an arbitrary immediate.
1532 def : Pat<(or i32:$in, imm:$imm),
1533 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1534 // XOR an arbitrary immediate.
1535 def : Pat<(xor i32:$in, imm:$imm),
1536 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1538 def : Pat<(sub immSExt16:$imm, i32:$in),
1539 (SUBFIC $in, imm:$imm)>;
1542 def : Pat<(shl i32:$in, (i32 imm:$imm)),
1543 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
1544 def : Pat<(srl i32:$in, (i32 imm:$imm)),
1545 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
1548 def : Pat<(rotl i32:$in, i32:$sh),
1549 (RLWNM $in, $sh, 0, 31)>;
1550 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
1551 (RLWINM $in, imm:$imm, 0, 31)>;
1554 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
1555 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1558 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
1559 (BL tglobaladdr:$dst)>;
1560 def : Pat<(PPCcall (i32 texternalsym:$dst)),
1561 (BL texternalsym:$dst)>;
1564 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1565 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1567 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1568 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1570 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1571 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1575 // Hi and Lo for Darwin Global Addresses.
1576 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1577 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1578 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1579 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1580 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1581 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1582 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
1583 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
1584 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
1585 (ADDIS $in, tglobaltlsaddr:$g)>;
1586 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
1587 (ADDI $in, tglobaltlsaddr:$g)>;
1588 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
1589 (ADDIS $in, tglobaladdr:$g)>;
1590 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
1591 (ADDIS $in, tconstpool:$g)>;
1592 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
1593 (ADDIS $in, tjumptable:$g)>;
1594 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
1595 (ADDIS $in, tblockaddress:$g)>;
1597 // Standard shifts. These are represented separately from the real shifts above
1598 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1600 def : Pat<(sra i32:$rS, i32:$rB),
1602 def : Pat<(srl i32:$rS, i32:$rB),
1604 def : Pat<(shl i32:$rS, i32:$rB),
1607 def : Pat<(zextloadi1 iaddr:$src),
1609 def : Pat<(zextloadi1 xaddr:$src),
1611 def : Pat<(extloadi1 iaddr:$src),
1613 def : Pat<(extloadi1 xaddr:$src),
1615 def : Pat<(extloadi8 iaddr:$src),
1617 def : Pat<(extloadi8 xaddr:$src),
1619 def : Pat<(extloadi16 iaddr:$src),
1621 def : Pat<(extloadi16 xaddr:$src),
1623 def : Pat<(f64 (extloadf32 iaddr:$src)),
1624 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
1625 def : Pat<(f64 (extloadf32 xaddr:$src)),
1626 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
1628 def : Pat<(f64 (fextend f32:$src)),
1629 (COPY_TO_REGCLASS $src, F8RC)>;
1632 def : Pat<(membarrier (i32 imm /*ll*/),
1636 (i32 imm /*device*/)),
1639 def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
1641 include "PPCInstrAltivec.td"
1642 include "PPCInstr64Bit.td"