1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific DAG Nodes.
21 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
22 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
23 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
25 def PPCfsel : SDNode<"PPCISD::FSEL",
26 // Type constraint for fsel.
27 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
28 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
30 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
31 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
33 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
34 // amounts. These nodes are generated by the multi-precision shift code.
35 def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
36 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
38 def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
39 def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
40 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
42 // These are target-independent nodes, but have target-specific formats.
43 def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
44 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>;
45 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>;
47 //===----------------------------------------------------------------------===//
48 // PowerPC specific transformation functions and pattern fragments.
51 def SHL32 : SDNodeXForm<imm, [{
52 // Transformation function: 31 - imm
53 return getI32Imm(31 - N->getValue());
56 def SHL64 : SDNodeXForm<imm, [{
57 // Transformation function: 63 - imm
58 return getI32Imm(63 - N->getValue());
61 def SRL32 : SDNodeXForm<imm, [{
62 // Transformation function: 32 - imm
63 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
66 def SRL64 : SDNodeXForm<imm, [{
67 // Transformation function: 64 - imm
68 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
71 def LO16 : SDNodeXForm<imm, [{
72 // Transformation function: get the low 16 bits.
73 return getI32Imm((unsigned short)N->getValue());
76 def HI16 : SDNodeXForm<imm, [{
77 // Transformation function: shift the immediate value down into the low bits.
78 return getI32Imm((unsigned)N->getValue() >> 16);
81 def HA16 : SDNodeXForm<imm, [{
82 // Transformation function: shift the immediate value down into the low bits.
83 signed int Val = N->getValue();
84 return getI32Imm((Val - (signed short)Val) >> 16);
88 def immSExt16 : PatLeaf<(imm), [{
89 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
90 // field. Used by instructions like 'addi'.
91 return (int)N->getValue() == (short)N->getValue();
93 def immZExt16 : PatLeaf<(imm), [{
94 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
95 // field. Used by instructions like 'ori'.
96 return (unsigned)N->getValue() == (unsigned short)N->getValue();
99 def imm16Shifted : PatLeaf<(imm), [{
100 // imm16Shifted predicate - True if only bits in the top 16-bits of the
101 // immediate are set. Used by instructions like 'addis'.
102 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
106 // Example of a legalize expander: Only for PPC64.
107 def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
108 [(set f64:$tmp , (FCTIDZ f64:$src)),
109 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
110 (store f64:$tmp, i32:$tmpFI),
111 (set i64:$dst, (load i32:$tmpFI))],
115 //===----------------------------------------------------------------------===//
116 // PowerPC Flag Definitions.
118 class isPPC64 { bit PPC64 = 1; }
119 class isVMX { bit VMX = 1; }
121 list<Register> Defs = [CR0];
127 //===----------------------------------------------------------------------===//
128 // PowerPC Operand Definitions.
130 def u5imm : Operand<i32> {
131 let PrintMethod = "printU5ImmOperand";
133 def u6imm : Operand<i32> {
134 let PrintMethod = "printU6ImmOperand";
136 def s16imm : Operand<i32> {
137 let PrintMethod = "printS16ImmOperand";
139 def u16imm : Operand<i32> {
140 let PrintMethod = "printU16ImmOperand";
142 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
143 let PrintMethod = "printS16X4ImmOperand";
145 def target : Operand<OtherVT> {
146 let PrintMethod = "printBranchOperand";
148 def calltarget : Operand<i32> {
149 let PrintMethod = "printCallOperand";
151 def aaddr : Operand<i32> {
152 let PrintMethod = "printAbsAddrOperand";
154 def piclabel: Operand<i32> {
155 let PrintMethod = "printPICLabel";
157 def symbolHi: Operand<i32> {
158 let PrintMethod = "printSymbolHi";
160 def symbolLo: Operand<i32> {
161 let PrintMethod = "printSymbolLo";
163 def crbitm: Operand<i8> {
164 let PrintMethod = "printcrbitm";
169 //===----------------------------------------------------------------------===//
170 // PowerPC Instruction Definitions.
172 // Pseudo-instructions:
173 def PHI : Pseudo<(ops variable_ops), "; PHI", []>;
175 let isLoad = 1, hasCtrlDep = 1 in {
176 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
177 "; ADJCALLSTACKDOWN",
178 [(callseq_start imm:$amt)]>;
179 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
181 [(callseq_end imm:$amt)]>;
183 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
184 [(set GPRC:$rD, (undef))]>;
185 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8",
186 [(set F8RC:$rD, (undef))]>;
187 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4",
188 [(set F4RC:$rD, (undef))]>;
190 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
191 // scheduler into a branch sequence.
192 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
193 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
194 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
195 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
196 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
197 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
198 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
202 let isTerminator = 1 in {
204 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB>;
205 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB>;
209 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>;
211 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
212 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
213 target:$true, target:$false),
214 "; COND_BRANCH", []>;
215 def B : IForm<18, 0, 0, (ops target:$dst),
219 // FIXME: 4*CR# needs to be added to the BI field!
220 // This will only work for CR0 as it stands now
221 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
222 "blt $crS, $block", BrB>;
223 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
224 "ble $crS, $block", BrB>;
225 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
226 "beq $crS, $block", BrB>;
227 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
228 "bge $crS, $block", BrB>;
229 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
230 "bgt $crS, $block", BrB>;
231 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
232 "bne $crS, $block", BrB>;
233 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
234 "bun $crS, $block", BrB>;
235 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
236 "bnu $crS, $block", BrB>;
240 // All calls clobber the non-callee saved registers...
241 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
242 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
244 CR0,CR1,CR5,CR6,CR7] in {
245 // Convenient aliases for call instructions
246 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
247 "bl $func", BrB, []>;
248 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
249 "bla $func", BrB, []>;
250 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB>;
253 // D-Form instructions. Most instructions that perform an operation on a
254 // register and an immediate are of this type.
257 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
258 "lbz $rD, $disp($rA)", LdStGeneral>;
259 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
260 "lha $rD, $disp($rA)", LdStLHA>;
261 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
262 "lhz $rD, $disp($rA)", LdStGeneral>;
263 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
264 "lmw $rD, $disp($rA)", LdStLMW>;
265 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
266 "lwz $rD, $disp($rA)", LdStGeneral>;
267 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
268 "lwzu $rD, $disp($rA)", LdStGeneral>;
270 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
271 "addi $rD, $rA, $imm", IntGeneral,
272 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
273 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
274 "addic $rD, $rA, $imm", IntGeneral,
276 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
277 "addic. $rD, $rA, $imm", IntGeneral,
279 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
280 "addis $rD, $rA, $imm", IntGeneral,
281 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
282 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
283 "la $rD, $sym($rA)", IntGeneral,
284 [(set GPRC:$rD, (add GPRC:$rA,
285 (PPClo tglobaladdr:$sym, 0)))]>;
286 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
287 "mulli $rD, $rA, $imm", IntMulLI,
288 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
289 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
290 "subfic $rD, $rA, $imm", IntGeneral,
291 [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>;
292 def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
293 "li $rD, $imm", IntGeneral,
294 [(set GPRC:$rD, immSExt16:$imm)]>;
295 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
296 "lis $rD, $imm", IntGeneral,
297 [(set GPRC:$rD, imm16Shifted:$imm)]>;
299 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
300 "stmw $rS, $disp($rA)", LdStLMW>;
301 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
302 "stb $rS, $disp($rA)", LdStGeneral>;
303 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
304 "sth $rS, $disp($rA)", LdStGeneral>;
305 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
306 "stw $rS, $disp($rA)", LdStGeneral>;
307 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
308 "stwu $rS, $disp($rA)", LdStGeneral>;
310 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
311 "andi. $dst, $src1, $src2", IntGeneral,
313 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
314 "andis. $dst, $src1, $src2", IntGeneral,
316 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
317 "ori $dst, $src1, $src2", IntGeneral,
318 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
319 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
320 "oris $dst, $src1, $src2", IntGeneral,
321 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
322 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
323 "xori $dst, $src1, $src2", IntGeneral,
324 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
325 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
326 "xoris $dst, $src1, $src2", IntGeneral,
327 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
328 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral>;
329 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
330 "cmpi $crD, $L, $rA, $imm", IntCompare>;
331 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
332 "cmpwi $crD, $rA, $imm", IntCompare>;
333 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
334 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
335 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
336 "cmpli $dst, $size, $src1, $src2", IntCompare>;
337 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
338 "cmplwi $dst, $src1, $src2", IntCompare>;
339 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
340 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
342 def LFS : DForm_8<48, (ops F4RC:$rD, symbolLo:$disp, GPRC:$rA),
343 "lfs $rD, $disp($rA)", LdStLFDU>;
344 def LFD : DForm_8<50, (ops F8RC:$rD, symbolLo:$disp, GPRC:$rA),
345 "lfd $rD, $disp($rA)", LdStLFD>;
348 def STFS : DForm_9<52, (ops F4RC:$rS, symbolLo:$disp, GPRC:$rA),
349 "stfs $rS, $disp($rA)", LdStUX>;
350 def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA),
351 "stfd $rS, $disp($rA)", LdStUX>;
354 // DS-Form instructions. Load/Store instructions available in PPC-64
357 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
358 "lwa $rT, $DS($rA)", LdStLWA>, isPPC64;
359 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
360 "ld $rT, $DS($rA)", LdStLD>, isPPC64;
363 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
364 "std $rT, $DS($rA)", LdStSTD>, isPPC64;
365 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
366 "stdu $rT, $DS($rA)", LdStSTD>, isPPC64;
369 // X-Form instructions. Most instructions that perform an operation on a
370 // register and another register are of this type.
373 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
374 "lbzx $dst, $base, $index", LdStGeneral>;
375 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
376 "lhax $dst, $base, $index", LdStLHA>;
377 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
378 "lhzx $dst, $base, $index", LdStGeneral>;
379 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
380 "lwax $dst, $base, $index", LdStLHA>, isPPC64;
381 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
382 "lwzx $dst, $base, $index", LdStGeneral>;
383 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
384 "ldx $dst, $base, $index", LdStLD>, isPPC64;
385 def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
386 "lvebx $vD, $base, $rA", LdStGeneral>;
387 def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
388 "lvehx $vD, $base, $rA", LdStGeneral>;
389 def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
390 "lvewx $vD, $base, $rA", LdStGeneral>;
391 def LVX : XForm_1<31, 103, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
392 "lvx $vD, $base, $rA", LdStGeneral>;
393 def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
394 "lvsl $vD, $base, $rA", LdStGeneral>;
395 def LVSR : XForm_1<31, 38, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
396 "lvsl $vD, $base, $rA", LdStGeneral>;
398 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
399 "nand $rA, $rS, $rB", IntGeneral,
400 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
401 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
402 "and $rA, $rS, $rB", IntGeneral,
403 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
404 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
405 "and. $rA, $rS, $rB", IntGeneral,
407 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
408 "andc $rA, $rS, $rB", IntGeneral,
409 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
410 def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
411 "or $rA, $rS, $rB", IntGeneral,
412 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
413 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
414 "or $rA, $rS, $rB", IntGeneral,
415 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
416 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
417 "or $rA, $rS, $rB", IntGeneral,
419 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
420 "or $rA, $rS, $rB", IntGeneral,
422 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
423 "nor $rA, $rS, $rB", IntGeneral,
424 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
425 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
426 "or. $rA, $rS, $rB", IntGeneral,
428 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
429 "orc $rA, $rS, $rB", IntGeneral,
430 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
431 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
432 "eqv $rA, $rS, $rB", IntGeneral,
433 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
434 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
435 "xor $rA, $rS, $rB", IntGeneral,
436 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
437 def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
438 "sld $rA, $rS, $rB", IntRotateD,
439 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
440 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
441 "slw $rA, $rS, $rB", IntGeneral,
442 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
443 def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
444 "srd $rA, $rS, $rB", IntRotateD,
445 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
446 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
447 "srw $rA, $rS, $rB", IntGeneral,
448 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
449 def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
450 "srad $rA, $rS, $rB", IntRotateD,
451 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
452 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
453 "sraw $rA, $rS, $rB", IntShift,
454 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
456 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
457 "stbx $rS, $rA, $rB", LdStGeneral>;
458 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
459 "sthx $rS, $rA, $rB", LdStGeneral>;
460 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
461 "stwx $rS, $rA, $rB", LdStGeneral>;
462 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
463 "stwux $rS, $rA, $rB", LdStGeneral>;
464 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
465 "stdx $rS, $rA, $rB", LdStSTD>, isPPC64;
466 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
467 "stdux $rS, $rA, $rB", LdStSTD>, isPPC64;
468 def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
469 "stvebx $rS, $rA, $rB", LdStGeneral>;
470 def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
471 "stvehx $rS, $rA, $rB", LdStGeneral>;
472 def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
473 "stvewx $rS, $rA, $rB", LdStGeneral>;
474 def STVX : XForm_8<31, 231, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
475 "stvx $rS, $rA, $rB", LdStGeneral>;
477 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
478 "srawi $rA, $rS, $SH", IntShift,
479 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
480 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
481 "cntlzw $rA, $rS", IntGeneral,
482 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
483 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
484 "extsb $rA, $rS", IntGeneral,
485 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
486 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
487 "extsh $rA, $rS", IntGeneral,
488 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
489 def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
490 "extsw $rA, $rS", IntGeneral,
491 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
492 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
493 "cmp $crD, $long, $rA, $rB", IntCompare>;
494 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
495 "cmpl $crD, $long, $rA, $rB", IntCompare>;
496 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
497 "cmpw $crD, $rA, $rB", IntCompare>;
498 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
499 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
500 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
501 "cmplw $crD, $rA, $rB", IntCompare>;
502 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
503 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
504 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
505 // "fcmpo $crD, $fA, $fB", FPCompare>;
506 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
507 "fcmpu $crD, $fA, $fB", FPCompare>;
508 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
509 "fcmpu $crD, $fA, $fB", FPCompare>;
512 def LFSX : XForm_25<31, 535, (ops F4RC:$dst, GPRC:$base, GPRC:$index),
513 "lfsx $dst, $base, $index", LdStLFDU>;
514 def LFDX : XForm_25<31, 599, (ops F8RC:$dst, GPRC:$base, GPRC:$index),
515 "lfdx $dst, $base, $index", LdStLFDU>;
517 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
518 "fcfid $frD, $frB", FPGeneral,
519 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
520 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
521 "fctidz $frD, $frB", FPGeneral,
522 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
523 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
524 "fctiwz $frD, $frB", FPGeneral,
525 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
526 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
527 "frsp $frD, $frB", FPGeneral,
528 [(set F4RC:$frD, (fround F8RC:$frB))]>;
529 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
530 "fsqrt $frD, $frB", FPSqrt,
531 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
532 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
533 "fsqrts $frD, $frB", FPSqrt,
534 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
536 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
537 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
538 "fmr $frD, $frB", FPGeneral,
539 []>; // (set F4RC:$frD, F4RC:$frB)
540 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
541 "fmr $frD, $frB", FPGeneral,
542 []>; // (set F8RC:$frD, F8RC:$frB)
543 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
544 "fmr $frD, $frB", FPGeneral,
545 [(set F8RC:$frD, (fextend F4RC:$frB))]>;
547 // These are artificially split into two different forms, for 4/8 byte FP.
548 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
549 "fabs $frD, $frB", FPGeneral,
550 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
551 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
552 "fabs $frD, $frB", FPGeneral,
553 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
554 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
555 "fnabs $frD, $frB", FPGeneral,
556 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
557 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
558 "fnabs $frD, $frB", FPGeneral,
559 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
560 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
561 "fneg $frD, $frB", FPGeneral,
562 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
563 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
564 "fneg $frD, $frB", FPGeneral,
565 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
569 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, GPRC:$rA, GPRC:$rB),
570 "stfsx $frS, $rA, $rB", LdStUX>;
571 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, GPRC:$rA, GPRC:$rB),
572 "stfdx $frS, $rA, $rB", LdStUX>;
575 // XL-Form instructions. condition register logical ops.
577 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
578 "mcrf $BF, $BFA", BrMCR>;
580 // XFX-Form instructions. Instructions that deal with SPRs
582 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
583 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
584 // which means the SPR value needs to be multiplied by a factor of 32.
585 def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>;
586 def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>;
587 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>;
588 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
589 "mtcrf $FXM, $rS", BrMCRX>;
590 def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
591 "mfcr $rT, $FXM", SprMFCR>;
592 def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>;
593 def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>;
594 def MTSPR : XFXForm_7<31, 467, (ops GPRC:$rS, u16imm:$UIMM), "mtspr $UIMM, $rS",
597 // XS-Form instructions. Just 'sradi'
599 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
600 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
602 // XO-Form instructions. Arithmetic instructions that can set overflow bit
604 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
605 "add $rT, $rA, $rB", IntGeneral,
606 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
607 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
608 "add $rT, $rA, $rB", IntGeneral,
609 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
610 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
611 "addc $rT, $rA, $rB", IntGeneral,
613 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
614 "adde $rT, $rA, $rB", IntGeneral,
616 def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
617 "divd $rT, $rA, $rB", IntDivD,
618 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
619 def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
620 "divdu $rT, $rA, $rB", IntDivD,
621 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
622 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
623 "divw $rT, $rA, $rB", IntDivW,
624 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
625 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
626 "divwu $rT, $rA, $rB", IntDivW,
627 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
628 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
629 "mulhd $rT, $rA, $rB", IntMulHW,
630 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
631 def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
632 "mulhdu $rT, $rA, $rB", IntMulHWU,
633 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
634 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
635 "mulhw $rT, $rA, $rB", IntMulHW,
636 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
637 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
638 "mulhwu $rT, $rA, $rB", IntMulHWU,
639 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
640 def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
641 "mulld $rT, $rA, $rB", IntMulHD,
642 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
643 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
644 "mullw $rT, $rA, $rB", IntMulHW,
645 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
646 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
647 "subf $rT, $rA, $rB", IntGeneral,
648 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
649 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
650 "subfc $rT, $rA, $rB", IntGeneral,
652 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
653 "subfe $rT, $rA, $rB", IntGeneral,
655 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
656 "addme $rT, $rA", IntGeneral,
658 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
659 "addze $rT, $rA", IntGeneral,
661 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
662 "neg $rT, $rA", IntGeneral,
663 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
664 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
665 "subfze $rT, $rA", IntGeneral,
668 // A-Form instructions. Most of the instructions executed in the FPU are of
671 def FMADD : AForm_1<63, 29,
672 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
673 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
674 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
676 def FMADDS : AForm_1<59, 29,
677 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
678 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
679 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
681 def FMSUB : AForm_1<63, 28,
682 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
683 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
684 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
686 def FMSUBS : AForm_1<59, 28,
687 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
688 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
689 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
691 def FNMADD : AForm_1<63, 31,
692 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
693 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
694 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
696 def FNMADDS : AForm_1<59, 31,
697 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
698 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
699 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
701 def FNMSUB : AForm_1<63, 30,
702 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
703 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
704 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
706 def FNMSUBS : AForm_1<59, 30,
707 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
708 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
709 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
711 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
712 // having 4 of these, force the comparison to always be an 8-byte double (code
713 // should use an FMRSD if the input comparison value really wants to be a float)
714 // and 4/8 byte forms for the result and operand type..
715 def FSELD : AForm_1<63, 23,
716 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
717 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
718 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
719 def FSELS : AForm_1<63, 23,
720 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
721 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
722 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
723 def FADD : AForm_2<63, 21,
724 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
725 "fadd $FRT, $FRA, $FRB", FPGeneral,
726 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
727 def FADDS : AForm_2<59, 21,
728 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
729 "fadds $FRT, $FRA, $FRB", FPGeneral,
730 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
731 def FDIV : AForm_2<63, 18,
732 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
733 "fdiv $FRT, $FRA, $FRB", FPDivD,
734 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
735 def FDIVS : AForm_2<59, 18,
736 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
737 "fdivs $FRT, $FRA, $FRB", FPDivS,
738 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
739 def FMUL : AForm_3<63, 25,
740 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
741 "fmul $FRT, $FRA, $FRB", FPFused,
742 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
743 def FMULS : AForm_3<59, 25,
744 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
745 "fmuls $FRT, $FRA, $FRB", FPGeneral,
746 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
747 def FSUB : AForm_2<63, 20,
748 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
749 "fsub $FRT, $FRA, $FRB", FPGeneral,
750 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
751 def FSUBS : AForm_2<59, 20,
752 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
753 "fsubs $FRT, $FRA, $FRB", FPGeneral,
754 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
756 // M-Form instructions. rotate and mask instructions.
758 let isTwoAddress = 1, isCommutable = 1 in {
759 // RLWIMI can be commuted if the rotate amount is zero.
760 def RLWIMI : MForm_2<20,
761 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
762 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
764 def RLDIMI : MDForm_1<30, 3,
765 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
766 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
769 def RLWINM : MForm_2<21,
770 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
771 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
773 def RLWINMo : MForm_2<21,
774 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
775 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
777 def RLWNM : MForm_2<23,
778 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
779 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
782 // MD-Form instructions. 64 bit rotate instructions.
784 def RLDICL : MDForm_1<30, 0,
785 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
786 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
788 def RLDICR : MDForm_1<30, 1,
789 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
790 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
793 // VA-Form instructions. 3-input AltiVec ops.
794 def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
795 "vmaddfp $vD, $vA, $vC, $vB", VecFP,
796 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
798 def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
799 "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
800 [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA,
804 // VX-Form instructions. AltiVec arithmetic ops.
805 def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
806 "vaddfp $vD, $vA, $vB", VecFP,
807 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
808 def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
809 "vcfsx $vD, $vB, $UIMM", VecFP,
811 def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
812 "vcfux $vD, $vB, $UIMM", VecFP,
814 def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
815 "vctsxs $vD, $vB, $UIMM", VecFP,
817 def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
818 "vctuxs $vD, $vB, $UIMM", VecFP,
820 def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB),
821 "vexptefp $vD, $vB", VecFP,
823 def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB),
824 "vlogefp $vD, $vB", VecFP,
826 def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
827 "vmaxfp $vD, $vA, $vB", VecFP,
829 def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
830 "vminfp $vD, $vA, $vB", VecFP,
832 def VREFP : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
833 "vrefp $vD, $vB", VecFP,
835 def VRFIM : VXForm_2<714, (ops VRRC:$vD, VRRC:$vB),
836 "vrfim $vD, $vB", VecFP,
838 def VRFIN : VXForm_2<522, (ops VRRC:$vD, VRRC:$vB),
839 "vrfin $vD, $vB", VecFP,
841 def VRFIP : VXForm_2<650, (ops VRRC:$vD, VRRC:$vB),
842 "vrfip $vD, $vB", VecFP,
844 def VRFIZ : VXForm_2<586, (ops VRRC:$vD, VRRC:$vB),
845 "vrfiz $vD, $vB", VecFP,
847 def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB),
848 "vrsqrtefp $vD, $vB", VecFP,
850 def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
851 "vsubfp $vD, $vA, $vB", VecFP,
852 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
854 //===----------------------------------------------------------------------===//
855 // PowerPC Instruction Patterns
858 // Arbitrary immediate support. Implement in terms of LIS/ORI.
859 def : Pat<(i32 imm:$imm),
860 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
862 // Implement the 'not' operation with the NOR instruction.
863 def NOT : Pat<(not GPRC:$in),
864 (NOR GPRC:$in, GPRC:$in)>;
866 // ADD an arbitrary immediate.
867 def : Pat<(add GPRC:$in, imm:$imm),
868 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
869 // OR an arbitrary immediate.
870 def : Pat<(or GPRC:$in, imm:$imm),
871 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
872 // XOR an arbitrary immediate.
873 def : Pat<(xor GPRC:$in, imm:$imm),
874 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
875 def : Pat<(or (shl GPRC:$rS, GPRC:$rB),
876 (srl GPRC:$rS, (sub 32, GPRC:$rB))),
877 (RLWNM GPRC:$rS, GPRC:$rB, 0, 31)>;
879 def : Pat<(zext GPRC:$in),
880 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
881 def : Pat<(anyext GPRC:$in),
882 (OR4To8 GPRC:$in, GPRC:$in)>;
883 def : Pat<(trunc G8RC:$in),
884 (OR8To4 G8RC:$in, G8RC:$in)>;
887 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
888 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
889 def : Pat<(shl G8RC:$in, (i64 imm:$imm)),
890 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
892 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
893 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
894 def : Pat<(srl G8RC:$in, (i64 imm:$imm)),
895 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
897 // Hi and Lo for Darwin Global Addresses.
898 def : Pat<(PPChi tglobaladdr:$in, (i32 0)), (LIS tglobaladdr:$in)>;
899 def : Pat<(PPClo tglobaladdr:$in, (i32 0)), (LI tglobaladdr:$in)>;
900 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
901 (ADDIS GPRC:$in, tglobaladdr:$g)>;
903 // Standard shifts. These are represented separately from the real shifts above
904 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
906 def : Pat<(sra GPRC:$rS, GPRC:$rB),
907 (SRAW GPRC:$rS, GPRC:$rB)>;
908 def : Pat<(srl GPRC:$rS, GPRC:$rB),
909 (SRW GPRC:$rS, GPRC:$rB)>;
910 def : Pat<(shl GPRC:$rS, GPRC:$rB),
911 (SLW GPRC:$rS, GPRC:$rB)>;
913 // Same as above, but using a temporary. FIXME: implement temporaries :)
915 def : Pattern<(xor GPRC:$in, imm:$imm),
916 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
917 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>;
920 //===----------------------------------------------------------------------===//
921 // PowerPCInstrInfo Definition
923 def PowerPCInstrInfo : InstrInfo {
926 let TSFlagsFields = [ "VMX", "PPC64" ];
927 let TSFlagsShifts = [ 0, 1 ];
929 let isLittleEndianEncoding = 1;