1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
26 def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
38 def SDT_PPClbrx : SDTypeProfile<1, 2, [
39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
41 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPClarx : SDTypeProfile<1, 1, [
46 SDTCisInt<0>, SDTCisPtrTy<1>
48 def SDT_PPCstcx : SDTypeProfile<0, 2, [
49 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
53 SDTCisPtrTy<0>, SDTCisVT<1, i32>
56 def SDT_PPCnop : SDTypeProfile<0, 0, []>;
58 //===----------------------------------------------------------------------===//
59 // PowerPC specific DAG Nodes.
62 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
63 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
64 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
65 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
66 [SDNPHasChain, SDNPMayStore]>;
68 // This sequence is used for long double->int conversions. It changes the
69 // bits in the FPSCR which is not modelled.
70 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
72 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
73 [SDNPInGlue, SDNPOutGlue]>;
74 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
75 [SDNPInGlue, SDNPOutGlue]>;
76 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
77 [SDNPInGlue, SDNPOutGlue]>;
78 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
79 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
83 def PPCfsel : SDNode<"PPCISD::FSEL",
84 // Type constraint for fsel.
85 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
86 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
88 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
89 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
90 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
91 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
92 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
94 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
96 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
97 // amounts. These nodes are generated by the multi-precision shift code.
98 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
99 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
100 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
102 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
103 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
104 [SDNPHasChain, SDNPMayStore]>;
106 // These are target-independent nodes, but have target-specific formats.
107 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
108 [SDNPHasChain, SDNPOutGlue]>;
109 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
110 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
112 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
113 def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall,
114 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
116 def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall,
117 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 def PPCcall_nop_SVR4 : SDNode<"PPCISD::CALL_NOP_SVR4", SDT_PPCCall,
120 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
122 def PPCnop : SDNode<"PPCISD::NOP", SDT_PPCnop, [SDNPInGlue, SDNPOutGlue]>;
123 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
124 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
125 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
126 [SDNPHasChain, SDNPSideEffect,
127 SDNPInGlue, SDNPOutGlue]>;
128 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
129 [SDNPHasChain, SDNPSideEffect,
130 SDNPInGlue, SDNPOutGlue]>;
131 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
132 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
133 def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone,
134 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
137 def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone,
138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
141 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
142 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
144 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
145 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
147 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
148 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
150 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
151 [SDNPHasChain, SDNPOptInGlue]>;
153 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
154 [SDNPHasChain, SDNPMayLoad]>;
155 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
156 [SDNPHasChain, SDNPMayStore]>;
158 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
159 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
160 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
161 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
162 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
164 // Instructions to support atomic operations
165 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
166 [SDNPHasChain, SDNPMayLoad]>;
167 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
168 [SDNPHasChain, SDNPMayStore]>;
170 // Instructions to support dynamic alloca.
171 def SDTDynOp : SDTypeProfile<1, 2, []>;
172 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
174 //===----------------------------------------------------------------------===//
175 // PowerPC specific transformation functions and pattern fragments.
178 def SHL32 : SDNodeXForm<imm, [{
179 // Transformation function: 31 - imm
180 return getI32Imm(31 - N->getZExtValue());
183 def SRL32 : SDNodeXForm<imm, [{
184 // Transformation function: 32 - imm
185 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
188 def LO16 : SDNodeXForm<imm, [{
189 // Transformation function: get the low 16 bits.
190 return getI32Imm((unsigned short)N->getZExtValue());
193 def HI16 : SDNodeXForm<imm, [{
194 // Transformation function: shift the immediate value down into the low bits.
195 return getI32Imm((unsigned)N->getZExtValue() >> 16);
198 def HA16 : SDNodeXForm<imm, [{
199 // Transformation function: shift the immediate value down into the low bits.
200 signed int Val = N->getZExtValue();
201 return getI32Imm((Val - (signed short)Val) >> 16);
203 def MB : SDNodeXForm<imm, [{
204 // Transformation function: get the start bit of a mask
206 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
207 return getI32Imm(mb);
210 def ME : SDNodeXForm<imm, [{
211 // Transformation function: get the end bit of a mask
213 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
214 return getI32Imm(me);
216 def maskimm32 : PatLeaf<(imm), [{
217 // maskImm predicate - True if immediate is a run of ones.
219 if (N->getValueType(0) == MVT::i32)
220 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
225 def immSExt16 : PatLeaf<(imm), [{
226 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
227 // field. Used by instructions like 'addi'.
228 if (N->getValueType(0) == MVT::i32)
229 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
231 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
233 def immZExt16 : PatLeaf<(imm), [{
234 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
235 // field. Used by instructions like 'ori'.
236 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
239 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
240 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
241 // identical in 32-bit mode, but in 64-bit mode, they return true if the
242 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
244 def imm16ShiftedZExt : PatLeaf<(imm), [{
245 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
246 // immediate are set. Used by instructions like 'xoris'.
247 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
250 def imm16ShiftedSExt : PatLeaf<(imm), [{
251 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
252 // immediate are set. Used by instructions like 'addis'. Identical to
253 // imm16ShiftedZExt in 32-bit mode.
254 if (N->getZExtValue() & 0xFFFF) return false;
255 if (N->getValueType(0) == MVT::i32)
257 // For 64-bit, make sure it is sext right.
258 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
262 //===----------------------------------------------------------------------===//
263 // PowerPC Flag Definitions.
265 class isPPC64 { bit PPC64 = 1; }
267 list<Register> Defs = [CR0];
271 class RegConstraint<string C> {
272 string Constraints = C;
274 class NoEncode<string E> {
275 string DisableEncoding = E;
279 //===----------------------------------------------------------------------===//
280 // PowerPC Operand Definitions.
282 def s5imm : Operand<i32> {
283 let PrintMethod = "printS5ImmOperand";
285 def u5imm : Operand<i32> {
286 let PrintMethod = "printU5ImmOperand";
288 def u6imm : Operand<i32> {
289 let PrintMethod = "printU6ImmOperand";
291 def s16imm : Operand<i32> {
292 let PrintMethod = "printS16ImmOperand";
294 def u16imm : Operand<i32> {
295 let PrintMethod = "printU16ImmOperand";
297 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
298 let PrintMethod = "printS16X4ImmOperand";
300 def directbrtarget : Operand<OtherVT> {
301 let PrintMethod = "printBranchOperand";
302 let EncoderMethod = "getDirectBrEncoding";
304 def condbrtarget : Operand<OtherVT> {
305 let PrintMethod = "printBranchOperand";
306 let EncoderMethod = "getCondBrEncoding";
308 def calltarget : Operand<iPTR> {
309 let EncoderMethod = "getDirectBrEncoding";
311 def aaddr : Operand<iPTR> {
312 let PrintMethod = "printAbsAddrOperand";
314 def symbolHi: Operand<i32> {
315 let PrintMethod = "printSymbolHi";
316 let EncoderMethod = "getHA16Encoding";
318 def symbolLo: Operand<i32> {
319 let PrintMethod = "printSymbolLo";
320 let EncoderMethod = "getLO16Encoding";
322 def crbitm: Operand<i8> {
323 let PrintMethod = "printcrbitm";
324 let EncoderMethod = "get_crbitm_encoding";
327 def memri : Operand<iPTR> {
328 let PrintMethod = "printMemRegImm";
329 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
330 let EncoderMethod = "getMemRIEncoding";
332 def memrr : Operand<iPTR> {
333 let PrintMethod = "printMemRegReg";
334 let MIOperandInfo = (ops ptr_rc:$offreg, ptr_rc:$ptrreg);
336 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
337 let PrintMethod = "printMemRegImmShifted";
338 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
339 let EncoderMethod = "getMemRIXEncoding";
341 def tocentry : Operand<iPTR> {
342 let MIOperandInfo = (ops i32imm:$imm);
345 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
346 // that doesn't matter.
347 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
348 (ops (i32 20), (i32 zero_reg))> {
349 let PrintMethod = "printPredicateOperand";
352 // Define PowerPC specific addressing mode.
353 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
354 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
355 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
356 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
358 /// This is just the offset part of iaddr, used for preinc.
359 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
360 def xaddroff : ComplexPattern<iPTR, 1, "SelectAddrIdxOffs", [], []>;
362 //===----------------------------------------------------------------------===//
363 // PowerPC Instruction Predicate Definitions.
364 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
365 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
366 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
368 //===----------------------------------------------------------------------===//
369 // PowerPC Instruction Definitions.
371 // Pseudo-instructions:
373 let hasCtrlDep = 1 in {
374 let Defs = [R1], Uses = [R1] in {
375 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "",
376 [(callseq_start timm:$amt)]>;
377 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "",
378 [(callseq_end timm:$amt1, timm:$amt2)]>;
381 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
382 "UPDATE_VRSAVE $rD, $rS", []>;
385 let Defs = [R1], Uses = [R1] in
386 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "",
388 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
390 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
391 // instruction selection into a branch sequence.
392 let usesCustomInserter = 1, // Expanded after instruction selection.
393 PPC970_Single = 1 in {
394 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
397 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
400 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
403 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
406 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
411 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
412 // scavenge a register for it.
414 def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F),
417 // RESTORE_CR - Indicate that we're restoring the CR register (previously
418 // spilled), so we'll need to scavenge a register for it.
420 def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F),
423 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
424 let isReturn = 1, Uses = [LR, RM] in
425 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
426 "b${p:cc}lr ${p:reg}", BrB,
428 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in
429 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
433 def MovePCtoLR : Pseudo<(outs), (ins), "", []>,
436 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
437 let isBarrier = 1 in {
438 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
443 // BCC represents an arbitrary conditional branch on a predicate.
444 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
445 // a two-value operand where a dag node expects two operands. :(
446 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
447 "b${cond:cc} ${cond:reg}, $dst"
448 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
450 let Defs = [CTR], Uses = [CTR] in {
451 def BDZ : IForm_ext<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
452 "bdz $dst", BrB, []>;
453 def BDNZ : IForm_ext<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
454 "bdnz $dst", BrB, []>;
459 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
460 // Convenient aliases for call instructions
462 def BL_Darwin : IForm<18, 0, 1,
463 (outs), (ins calltarget:$func),
464 "bl $func", BrB, []>; // See Pat patterns below.
465 def BLA_Darwin : IForm<18, 1, 1,
466 (outs), (ins aaddr:$func),
467 "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>;
469 let Uses = [CTR, RM] in {
470 def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1,
473 [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>;
478 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
479 // Convenient aliases for call instructions
481 def BL_SVR4 : IForm<18, 0, 1,
482 (outs), (ins calltarget:$func),
483 "bl $func", BrB, []>; // See Pat patterns below.
484 def BLA_SVR4 : IForm<18, 1, 1,
485 (outs), (ins aaddr:$func),
487 [(PPCcall_SVR4 (i32 imm:$func))]>;
489 let Uses = [CTR, RM] in {
490 def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1,
493 [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>;
498 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
499 def TCRETURNdi :Pseudo< (outs),
500 (ins calltarget:$dst, i32imm:$offset),
501 "#TC_RETURNd $dst $offset",
505 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
506 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
507 "#TC_RETURNa $func $offset",
508 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
510 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
511 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
512 "#TC_RETURNr $dst $offset",
516 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
517 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
518 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
519 Requires<[In32BitMode]>;
523 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
524 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
525 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
530 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
531 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
532 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
537 // DCB* instructions.
538 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
539 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
540 PPC970_DGroup_Single;
541 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
542 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
543 PPC970_DGroup_Single;
544 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
545 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
546 PPC970_DGroup_Single;
547 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
548 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
549 PPC970_DGroup_Single;
550 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
551 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
552 PPC970_DGroup_Single;
553 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
554 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
555 PPC970_DGroup_Single;
556 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
557 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
558 PPC970_DGroup_Single;
559 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
560 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
561 PPC970_DGroup_Single;
563 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
567 let usesCustomInserter = 1 in {
568 let Defs = [CR0] in {
569 def ATOMIC_LOAD_ADD_I8 : Pseudo<
570 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
571 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>;
572 def ATOMIC_LOAD_SUB_I8 : Pseudo<
573 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
574 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>;
575 def ATOMIC_LOAD_AND_I8 : Pseudo<
576 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
577 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>;
578 def ATOMIC_LOAD_OR_I8 : Pseudo<
579 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
580 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>;
581 def ATOMIC_LOAD_XOR_I8 : Pseudo<
582 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
583 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>;
584 def ATOMIC_LOAD_NAND_I8 : Pseudo<
585 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
586 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>;
587 def ATOMIC_LOAD_ADD_I16 : Pseudo<
588 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
589 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>;
590 def ATOMIC_LOAD_SUB_I16 : Pseudo<
591 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
592 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>;
593 def ATOMIC_LOAD_AND_I16 : Pseudo<
594 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
595 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>;
596 def ATOMIC_LOAD_OR_I16 : Pseudo<
597 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
598 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>;
599 def ATOMIC_LOAD_XOR_I16 : Pseudo<
600 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
601 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>;
602 def ATOMIC_LOAD_NAND_I16 : Pseudo<
603 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
604 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>;
605 def ATOMIC_LOAD_ADD_I32 : Pseudo<
606 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
607 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>;
608 def ATOMIC_LOAD_SUB_I32 : Pseudo<
609 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
610 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>;
611 def ATOMIC_LOAD_AND_I32 : Pseudo<
612 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
613 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>;
614 def ATOMIC_LOAD_OR_I32 : Pseudo<
615 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
616 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>;
617 def ATOMIC_LOAD_XOR_I32 : Pseudo<
618 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
619 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>;
620 def ATOMIC_LOAD_NAND_I32 : Pseudo<
621 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
622 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>;
624 def ATOMIC_CMP_SWAP_I8 : Pseudo<
625 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
627 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
628 def ATOMIC_CMP_SWAP_I16 : Pseudo<
629 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
631 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
632 def ATOMIC_CMP_SWAP_I32 : Pseudo<
633 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
635 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
637 def ATOMIC_SWAP_I8 : Pseudo<
638 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
639 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>;
640 def ATOMIC_SWAP_I16 : Pseudo<
641 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
642 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>;
643 def ATOMIC_SWAP_I32 : Pseudo<
644 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
645 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>;
649 // Instructions to support atomic operations
650 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
651 "lwarx $rD, $src", LdStLWARX,
652 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>;
655 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
656 "stwcx. $rS, $dst", LdStSTWCX,
657 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>,
660 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
661 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>;
663 //===----------------------------------------------------------------------===//
664 // PPC32 Load Instructions.
667 // Unindexed (r+i) Loads.
668 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
669 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
670 "lbz $rD, $src", LdStLoad,
671 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
672 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
673 "lha $rD, $src", LdStLHA,
674 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
675 PPC970_DGroup_Cracked;
676 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
677 "lhz $rD, $src", LdStLoad,
678 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
679 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
680 "lwz $rD, $src", LdStLoad,
681 [(set GPRC:$rD, (load iaddr:$src))]>;
683 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
684 "lfs $rD, $src", LdStLFDU,
685 [(set F4RC:$rD, (load iaddr:$src))]>;
686 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
687 "lfd $rD, $src", LdStLFD,
688 [(set F8RC:$rD, (load iaddr:$src))]>;
691 // Unindexed (r+i) Loads with Update (preinc).
693 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
694 "lbzu $rD, $addr", LdStLoad,
695 []>, RegConstraint<"$addr.reg = $ea_result">,
696 NoEncode<"$ea_result">;
698 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
699 "lhau $rD, $addr", LdStLoad,
700 []>, RegConstraint<"$addr.reg = $ea_result">,
701 NoEncode<"$ea_result">;
703 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
704 "lhzu $rD, $addr", LdStLoad,
705 []>, RegConstraint<"$addr.reg = $ea_result">,
706 NoEncode<"$ea_result">;
708 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
709 "lwzu $rD, $addr", LdStLoad,
710 []>, RegConstraint<"$addr.reg = $ea_result">,
711 NoEncode<"$ea_result">;
713 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
714 "lfs $rD, $addr", LdStLFDU,
715 []>, RegConstraint<"$addr.reg = $ea_result">,
716 NoEncode<"$ea_result">;
718 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
719 "lfd $rD, $addr", LdStLFD,
720 []>, RegConstraint<"$addr.reg = $ea_result">,
721 NoEncode<"$ea_result">;
724 // Indexed (r+r) Loads with Update (preinc).
725 def LBZUX : XForm_1<31, 119, (outs GPRC:$rD, ptr_rc:$ea_result),
727 "lbzux $rD, $addr", LdStLoad,
728 []>, RegConstraint<"$addr.offreg = $ea_result">,
729 NoEncode<"$ea_result">;
731 def LHAUX : XForm_1<31, 375, (outs GPRC:$rD, ptr_rc:$ea_result),
733 "lhaux $rD, $addr", LdStLoad,
734 []>, RegConstraint<"$addr.offreg = $ea_result">,
735 NoEncode<"$ea_result">;
737 def LHZUX : XForm_1<31, 331, (outs GPRC:$rD, ptr_rc:$ea_result),
739 "lhzux $rD, $addr", LdStLoad,
740 []>, RegConstraint<"$addr.offreg = $ea_result">,
741 NoEncode<"$ea_result">;
743 def LWZUX : XForm_1<31, 55, (outs GPRC:$rD, ptr_rc:$ea_result),
745 "lwzux $rD, $addr", LdStLoad,
746 []>, RegConstraint<"$addr.offreg = $ea_result">,
747 NoEncode<"$ea_result">;
749 def LFSUX : XForm_1<31, 567, (outs F4RC:$rD, ptr_rc:$ea_result),
751 "lfsux $rD, $addr", LdStLoad,
752 []>, RegConstraint<"$addr.offreg = $ea_result">,
753 NoEncode<"$ea_result">;
755 def LFDUX : XForm_1<31, 631, (outs F8RC:$rD, ptr_rc:$ea_result),
757 "lfdux $rD, $addr", LdStLoad,
758 []>, RegConstraint<"$addr.offreg = $ea_result">,
759 NoEncode<"$ea_result">;
763 // Indexed (r+r) Loads.
765 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
766 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
767 "lbzx $rD, $src", LdStLoad,
768 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
769 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
770 "lhax $rD, $src", LdStLHA,
771 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
772 PPC970_DGroup_Cracked;
773 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
774 "lhzx $rD, $src", LdStLoad,
775 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
776 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
777 "lwzx $rD, $src", LdStLoad,
778 [(set GPRC:$rD, (load xaddr:$src))]>;
781 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
782 "lhbrx $rD, $src", LdStLoad,
783 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i16))]>;
784 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
785 "lwbrx $rD, $src", LdStLoad,
786 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>;
788 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
789 "lfsx $frD, $src", LdStLFDU,
790 [(set F4RC:$frD, (load xaddr:$src))]>;
791 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
792 "lfdx $frD, $src", LdStLFDU,
793 [(set F8RC:$frD, (load xaddr:$src))]>;
796 //===----------------------------------------------------------------------===//
797 // PPC32 Store Instructions.
800 // Unindexed (r+i) Stores.
801 let PPC970_Unit = 2 in {
802 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
803 "stb $rS, $src", LdStStore,
804 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
805 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
806 "sth $rS, $src", LdStStore,
807 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
808 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
809 "stw $rS, $src", LdStStore,
810 [(store GPRC:$rS, iaddr:$src)]>;
811 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
812 "stfs $rS, $dst", LdStUX,
813 [(store F4RC:$rS, iaddr:$dst)]>;
814 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
815 "stfd $rS, $dst", LdStUX,
816 [(store F8RC:$rS, iaddr:$dst)]>;
819 // Unindexed (r+i) Stores with Update (preinc).
820 let PPC970_Unit = 2 in {
821 def STBU : DForm_1a<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
822 symbolLo:$ptroff, ptr_rc:$ptrreg),
823 "stbu $rS, $ptroff($ptrreg)", LdStStore,
824 [(set ptr_rc:$ea_res,
825 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
826 iaddroff:$ptroff))]>,
827 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
828 def STHU : DForm_1a<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
829 symbolLo:$ptroff, ptr_rc:$ptrreg),
830 "sthu $rS, $ptroff($ptrreg)", LdStStore,
831 [(set ptr_rc:$ea_res,
832 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
833 iaddroff:$ptroff))]>,
834 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
835 def STWU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
836 symbolLo:$ptroff, ptr_rc:$ptrreg),
837 "stwu $rS, $ptroff($ptrreg)", LdStStore,
838 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
839 iaddroff:$ptroff))]>,
840 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
841 def STFSU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
842 symbolLo:$ptroff, ptr_rc:$ptrreg),
843 "stfsu $rS, $ptroff($ptrreg)", LdStStore,
844 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
845 iaddroff:$ptroff))]>,
846 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
847 def STFDU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
848 symbolLo:$ptroff, ptr_rc:$ptrreg),
849 "stfdu $rS, $ptroff($ptrreg)", LdStStore,
850 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
851 iaddroff:$ptroff))]>,
852 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
856 // Indexed (r+r) Stores.
858 let PPC970_Unit = 2 in {
859 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
860 "stbx $rS, $dst", LdStStore,
861 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
862 PPC970_DGroup_Cracked;
863 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
864 "sthx $rS, $dst", LdStStore,
865 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
866 PPC970_DGroup_Cracked;
867 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
868 "stwx $rS, $dst", LdStStore,
869 [(store GPRC:$rS, xaddr:$dst)]>,
870 PPC970_DGroup_Cracked;
872 def STBUX : XForm_8<31, 247, (outs ptr_rc:$ea_res),
873 (ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
874 "stbux $rS, $ptroff, $ptrreg", LdStStore,
875 [(set ptr_rc:$ea_res,
876 (pre_truncsti8 GPRC:$rS,
877 ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
878 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
879 PPC970_DGroup_Cracked;
881 def STHUX : XForm_8<31, 439, (outs ptr_rc:$ea_res),
882 (ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
883 "sthux $rS, $ptroff, $ptrreg", LdStStore,
884 [(set ptr_rc:$ea_res,
885 (pre_truncsti16 GPRC:$rS,
886 ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
887 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
888 PPC970_DGroup_Cracked;
890 def STWUX : XForm_8<31, 183, (outs ptr_rc:$ea_res),
891 (ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
892 "stwux $rS, $ptroff, $ptrreg", LdStStore,
893 [(set ptr_rc:$ea_res,
894 (pre_store GPRC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
895 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
896 PPC970_DGroup_Cracked;
898 def STFSUX : XForm_8<31, 695, (outs ptr_rc:$ea_res),
899 (ins F4RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
900 "stfsux $rS, $ptroff, $ptrreg", LdStStore,
901 [(set ptr_rc:$ea_res,
902 (pre_store F4RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
903 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
904 PPC970_DGroup_Cracked;
906 def STFDUX : XForm_8<31, 759, (outs ptr_rc:$ea_res),
907 (ins F8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
908 "stfdux $rS, $ptroff, $ptrreg", LdStStore,
909 [(set ptr_rc:$ea_res,
910 (pre_store F8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
911 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
912 PPC970_DGroup_Cracked;
914 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
915 "sthbrx $rS, $dst", LdStStore,
916 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>,
917 PPC970_DGroup_Cracked;
918 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
919 "stwbrx $rS, $dst", LdStStore,
920 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i32)]>,
921 PPC970_DGroup_Cracked;
923 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
924 "stfiwx $frS, $dst", LdStUX,
925 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
927 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
928 "stfsx $frS, $dst", LdStUX,
929 [(store F4RC:$frS, xaddr:$dst)]>;
930 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
931 "stfdx $frS, $dst", LdStUX,
932 [(store F8RC:$frS, xaddr:$dst)]>;
935 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
939 //===----------------------------------------------------------------------===//
940 // PPC32 Arithmetic Instructions.
943 let PPC970_Unit = 1 in { // FXU Operations.
944 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
945 "addi $rD, $rA, $imm", IntSimple,
946 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
947 def ADDIL : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$imm),
948 "addi $rD, $rA, $imm", IntSimple,
949 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
950 let Defs = [CARRY] in {
951 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
952 "addic $rD, $rA, $imm", IntGeneral,
953 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
954 PPC970_DGroup_Cracked;
955 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
956 "addic. $rD, $rA, $imm", IntGeneral,
959 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
960 "addis $rD, $rA, $imm", IntSimple,
961 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
962 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
963 "la $rD, $sym($rA)", IntGeneral,
964 [(set GPRC:$rD, (add GPRC:$rA,
965 (PPClo tglobaladdr:$sym, 0)))]>;
966 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
967 "mulli $rD, $rA, $imm", IntMulLI,
968 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
969 let Defs = [CARRY] in {
970 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
971 "subfic $rD, $rA, $imm", IntGeneral,
972 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
975 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
976 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
977 "li $rD, $imm", IntSimple,
978 [(set GPRC:$rD, immSExt16:$imm)]>;
979 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
980 "lis $rD, $imm", IntSimple,
981 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
985 let PPC970_Unit = 1 in { // FXU Operations.
986 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
987 "andi. $dst, $src1, $src2", IntGeneral,
988 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
990 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
991 "andis. $dst, $src1, $src2", IntGeneral,
992 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
994 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
995 "ori $dst, $src1, $src2", IntSimple,
996 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
997 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
998 "oris $dst, $src1, $src2", IntSimple,
999 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
1000 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1001 "xori $dst, $src1, $src2", IntSimple,
1002 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
1003 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1004 "xoris $dst, $src1, $src2", IntSimple,
1005 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
1006 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple,
1008 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
1009 "cmpwi $crD, $rA, $imm", IntCompare>;
1010 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1011 "cmplwi $dst, $src1, $src2", IntCompare>;
1015 let PPC970_Unit = 1 in { // FXU Operations.
1016 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1017 "nand $rA, $rS, $rB", IntSimple,
1018 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
1019 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1020 "and $rA, $rS, $rB", IntSimple,
1021 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
1022 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1023 "andc $rA, $rS, $rB", IntSimple,
1024 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
1025 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1026 "or $rA, $rS, $rB", IntSimple,
1027 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
1028 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1029 "nor $rA, $rS, $rB", IntSimple,
1030 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
1031 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1032 "orc $rA, $rS, $rB", IntSimple,
1033 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
1034 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1035 "eqv $rA, $rS, $rB", IntSimple,
1036 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
1037 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1038 "xor $rA, $rS, $rB", IntSimple,
1039 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
1040 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1041 "slw $rA, $rS, $rB", IntGeneral,
1042 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
1043 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1044 "srw $rA, $rS, $rB", IntGeneral,
1045 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
1046 let Defs = [CARRY] in {
1047 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1048 "sraw $rA, $rS, $rB", IntShift,
1049 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
1053 let PPC970_Unit = 1 in { // FXU Operations.
1054 let Defs = [CARRY] in {
1055 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
1056 "srawi $rA, $rS, $SH", IntShift,
1057 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
1059 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
1060 "cntlzw $rA, $rS", IntGeneral,
1061 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
1062 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
1063 "extsb $rA, $rS", IntSimple,
1064 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
1065 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
1066 "extsh $rA, $rS", IntSimple,
1067 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
1069 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1070 "cmpw $crD, $rA, $rB", IntCompare>;
1071 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1072 "cmplw $crD, $rA, $rB", IntCompare>;
1074 let PPC970_Unit = 3 in { // FPU Operations.
1075 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1076 // "fcmpo $crD, $fA, $fB", FPCompare>;
1077 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
1078 "fcmpu $crD, $fA, $fB", FPCompare>;
1079 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
1080 "fcmpu $crD, $fA, $fB", FPCompare>;
1082 let Uses = [RM] in {
1083 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
1084 "fctiwz $frD, $frB", FPGeneral,
1085 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
1086 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
1087 "frsp $frD, $frB", FPGeneral,
1088 [(set F4RC:$frD, (fround F8RC:$frB))]>;
1089 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
1090 "fsqrt $frD, $frB", FPSqrt,
1091 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
1092 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
1093 "fsqrts $frD, $frB", FPSqrt,
1094 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
1098 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1099 /// often coalesced away and we don't want the dispatch group builder to think
1100 /// that they will fill slots (which could cause the load of a LSU reject to
1101 /// sneak into a d-group with a store).
1102 def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
1103 "fmr $frD, $frB", FPGeneral,
1104 []>, // (set F4RC:$frD, F4RC:$frB)
1107 let PPC970_Unit = 3 in { // FPU Operations.
1108 // These are artificially split into two different forms, for 4/8 byte FP.
1109 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
1110 "fabs $frD, $frB", FPGeneral,
1111 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
1112 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
1113 "fabs $frD, $frB", FPGeneral,
1114 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
1115 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
1116 "fnabs $frD, $frB", FPGeneral,
1117 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
1118 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
1119 "fnabs $frD, $frB", FPGeneral,
1120 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
1121 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
1122 "fneg $frD, $frB", FPGeneral,
1123 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
1124 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
1125 "fneg $frD, $frB", FPGeneral,
1126 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
1130 // XL-Form instructions. condition register logical ops.
1132 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
1133 "mcrf $BF, $BFA", BrMCR>,
1134 PPC970_DGroup_First, PPC970_Unit_CRU;
1136 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
1137 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1138 "creqv $CRD, $CRA, $CRB", BrCR,
1141 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
1142 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1143 "cror $CRD, $CRA, $CRB", BrCR,
1146 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
1147 "creqv $dst, $dst, $dst", BrCR,
1150 def CRUNSET: XLForm_1_ext<19, 193, (outs CRBITRC:$dst), (ins),
1151 "crxor $dst, $dst, $dst", BrCR,
1154 let Defs = [CR1EQ], CRD = 6 in {
1155 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1156 "creqv 6, 6, 6", BrCR,
1159 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
1160 "crxor 6, 6, 6", BrCR,
1164 // XFX-Form instructions. Instructions that deal with SPRs.
1166 let Uses = [CTR] in {
1167 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
1168 "mfctr $rT", SprMFSPR>,
1169 PPC970_DGroup_First, PPC970_Unit_FXU;
1171 let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in {
1172 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
1173 "mtctr $rS", SprMTSPR>,
1174 PPC970_DGroup_First, PPC970_Unit_FXU;
1177 let Defs = [LR] in {
1178 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1179 "mtlr $rS", SprMTSPR>,
1180 PPC970_DGroup_First, PPC970_Unit_FXU;
1182 let Uses = [LR] in {
1183 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1184 "mflr $rT", SprMFSPR>,
1185 PPC970_DGroup_First, PPC970_Unit_FXU;
1188 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1189 // a GPR on the PPC970. As such, copies in and out have the same performance
1190 // characteristics as an OR instruction.
1191 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1192 "mtspr 256, $rS", IntGeneral>,
1193 PPC970_DGroup_Single, PPC970_Unit_FXU;
1194 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1195 "mfspr $rT, 256", IntGeneral>,
1196 PPC970_DGroup_First, PPC970_Unit_FXU;
1198 def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS),
1199 "mtcrf $FXM, $rS", BrMCRX>,
1200 PPC970_MicroCode, PPC970_Unit_CRU;
1202 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
1203 // declaring that here gives the local register allocator problems with this:
1205 // MFCR <kill of whatever preg got assigned to vreg>
1206 // while not declaring it breaks DeadMachineInstructionElimination.
1207 // As it turns out, in all cases where we currently use this,
1208 // we're only interested in one subregister of it. Represent this in the
1209 // instruction to keep the register allocator from becoming confused.
1211 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
1212 def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1214 PPC970_MicroCode, PPC970_Unit_CRU;
1216 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
1217 "mfcr $rT", SprMFCR>,
1218 PPC970_MicroCode, PPC970_Unit_CRU;
1220 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1221 "mfocrf $rT, $FXM", SprMFCR>,
1222 PPC970_DGroup_First, PPC970_Unit_CRU;
1224 // Instructions to manipulate FPSCR. Only long double handling uses these.
1225 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
1227 let Uses = [RM], Defs = [RM] in {
1228 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1229 "mtfsb0 $FM", IntMTFSB0,
1230 [(PPCmtfsb0 (i32 imm:$FM))]>,
1231 PPC970_DGroup_Single, PPC970_Unit_FPU;
1232 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1233 "mtfsb1 $FM", IntMTFSB0,
1234 [(PPCmtfsb1 (i32 imm:$FM))]>,
1235 PPC970_DGroup_Single, PPC970_Unit_FPU;
1236 // MTFSF does not actually produce an FP result. We pretend it copies
1237 // input reg B to the output. If we didn't do this it would look like the
1238 // instruction had no outputs (because we aren't modelling the FPSCR) and
1239 // it would be deleted.
1240 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
1241 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
1242 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
1243 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM),
1244 F8RC:$rT, F8RC:$FRB))]>,
1245 PPC970_DGroup_Single, PPC970_Unit_FPU;
1247 let Uses = [RM] in {
1248 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1249 "mffs $rT", IntMFFS,
1250 [(set F8RC:$rT, (PPCmffs))]>,
1251 PPC970_DGroup_Single, PPC970_Unit_FPU;
1252 def FADDrtz: AForm_2<63, 21,
1253 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1254 "fadd $FRT, $FRA, $FRB", FPGeneral,
1255 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>,
1256 PPC970_DGroup_Single, PPC970_Unit_FPU;
1260 let PPC970_Unit = 1 in { // FXU Operations.
1262 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1264 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1265 "add $rT, $rA, $rB", IntSimple,
1266 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
1267 let Defs = [CARRY] in {
1268 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1269 "addc $rT, $rA, $rB", IntGeneral,
1270 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
1271 PPC970_DGroup_Cracked;
1273 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1274 "divw $rT, $rA, $rB", IntDivW,
1275 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
1276 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1277 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1278 "divwu $rT, $rA, $rB", IntDivW,
1279 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
1280 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1281 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1282 "mulhw $rT, $rA, $rB", IntMulHW,
1283 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
1284 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1285 "mulhwu $rT, $rA, $rB", IntMulHWU,
1286 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
1287 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1288 "mullw $rT, $rA, $rB", IntMulHW,
1289 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
1290 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1291 "subf $rT, $rA, $rB", IntGeneral,
1292 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
1293 let Defs = [CARRY] in {
1294 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1295 "subfc $rT, $rA, $rB", IntGeneral,
1296 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
1297 PPC970_DGroup_Cracked;
1299 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1300 "neg $rT, $rA", IntSimple,
1301 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
1302 let Uses = [CARRY], Defs = [CARRY] in {
1303 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1304 "adde $rT, $rA, $rB", IntGeneral,
1305 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
1306 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1307 "addme $rT, $rA", IntGeneral,
1308 [(set GPRC:$rT, (adde GPRC:$rA, -1))]>;
1309 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1310 "addze $rT, $rA", IntGeneral,
1311 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
1312 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1313 "subfe $rT, $rA, $rB", IntGeneral,
1314 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
1315 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1316 "subfme $rT, $rA", IntGeneral,
1317 [(set GPRC:$rT, (sube -1, GPRC:$rA))]>;
1318 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1319 "subfze $rT, $rA", IntGeneral,
1320 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
1324 // A-Form instructions. Most of the instructions executed in the FPU are of
1327 let PPC970_Unit = 3 in { // FPU Operations.
1328 let Uses = [RM] in {
1329 def FMADD : AForm_1<63, 29,
1330 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1331 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1333 (fma F8RC:$FRA, F8RC:$FRC, F8RC:$FRB))]>;
1334 def FMADDS : AForm_1<59, 29,
1335 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1336 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1338 (fma F4RC:$FRA, F4RC:$FRC, F4RC:$FRB))]>;
1339 def FMSUB : AForm_1<63, 28,
1340 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1341 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1343 (fma F8RC:$FRA, F8RC:$FRC, (fneg F8RC:$FRB)))]>;
1344 def FMSUBS : AForm_1<59, 28,
1345 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1346 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1348 (fma F4RC:$FRA, F4RC:$FRC, (fneg F4RC:$FRB)))]>;
1349 def FNMADD : AForm_1<63, 31,
1350 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1351 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1353 (fneg (fma F8RC:$FRA, F8RC:$FRC, F8RC:$FRB)))]>;
1354 def FNMADDS : AForm_1<59, 31,
1355 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1356 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1358 (fneg (fma F4RC:$FRA, F4RC:$FRC, F4RC:$FRB)))]>;
1359 def FNMSUB : AForm_1<63, 30,
1360 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1361 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1362 [(set F8RC:$FRT, (fneg (fma F8RC:$FRA, F8RC:$FRC,
1363 (fneg F8RC:$FRB))))]>;
1364 def FNMSUBS : AForm_1<59, 30,
1365 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1366 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1367 [(set F4RC:$FRT, (fneg (fma F4RC:$FRA, F4RC:$FRC,
1368 (fneg F4RC:$FRB))))]>;
1370 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1371 // having 4 of these, force the comparison to always be an 8-byte double (code
1372 // should use an FMRSD if the input comparison value really wants to be a float)
1373 // and 4/8 byte forms for the result and operand type..
1374 def FSELD : AForm_1<63, 23,
1375 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1376 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1377 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
1378 def FSELS : AForm_1<63, 23,
1379 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1380 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1381 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
1382 let Uses = [RM] in {
1383 def FADD : AForm_2<63, 21,
1384 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1385 "fadd $FRT, $FRA, $FRB", FPGeneral,
1386 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
1387 def FADDS : AForm_2<59, 21,
1388 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1389 "fadds $FRT, $FRA, $FRB", FPGeneral,
1390 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
1391 def FDIV : AForm_2<63, 18,
1392 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1393 "fdiv $FRT, $FRA, $FRB", FPDivD,
1394 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1395 def FDIVS : AForm_2<59, 18,
1396 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1397 "fdivs $FRT, $FRA, $FRB", FPDivS,
1398 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1399 def FMUL : AForm_3<63, 25,
1400 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1401 "fmul $FRT, $FRA, $FRB", FPFused,
1402 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
1403 def FMULS : AForm_3<59, 25,
1404 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1405 "fmuls $FRT, $FRA, $FRB", FPGeneral,
1406 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
1407 def FSUB : AForm_2<63, 20,
1408 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1409 "fsub $FRT, $FRA, $FRB", FPGeneral,
1410 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1411 def FSUBS : AForm_2<59, 20,
1412 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1413 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1414 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1418 let PPC970_Unit = 1 in { // FXU Operations.
1419 def ISEL : AForm_1<31, 15,
1420 (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB, pred:$cond),
1421 "isel $rT, $rA, $rB, $cond", IntGeneral,
1425 let PPC970_Unit = 1 in { // FXU Operations.
1426 // M-Form instructions. rotate and mask instructions.
1428 let isCommutable = 1 in {
1429 // RLWIMI can be commuted if the rotate amount is zero.
1430 def RLWIMI : MForm_2<20,
1431 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1432 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1433 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1436 def RLWINM : MForm_2<21,
1437 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1438 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1440 def RLWINMo : MForm_2<21,
1441 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1442 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1443 []>, isDOT, PPC970_DGroup_Cracked;
1444 def RLWNM : MForm_2<23,
1445 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1446 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1451 //===----------------------------------------------------------------------===//
1452 // PowerPC Instruction Patterns
1455 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1456 def : Pat<(i32 imm:$imm),
1457 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1459 // Implement the 'not' operation with the NOR instruction.
1460 def NOT : Pat<(not GPRC:$in),
1461 (NOR GPRC:$in, GPRC:$in)>;
1463 // ADD an arbitrary immediate.
1464 def : Pat<(add GPRC:$in, imm:$imm),
1465 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1466 // OR an arbitrary immediate.
1467 def : Pat<(or GPRC:$in, imm:$imm),
1468 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1469 // XOR an arbitrary immediate.
1470 def : Pat<(xor GPRC:$in, imm:$imm),
1471 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1473 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1474 (SUBFIC GPRC:$in, imm:$imm)>;
1477 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1478 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1479 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1480 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1483 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1484 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1485 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1486 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1489 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1490 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1493 def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)),
1494 (BL_Darwin tglobaladdr:$dst)>;
1495 def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)),
1496 (BL_Darwin texternalsym:$dst)>;
1497 def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)),
1498 (BL_SVR4 tglobaladdr:$dst)>;
1499 def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)),
1500 (BL_SVR4 texternalsym:$dst)>;
1503 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1504 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1506 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1507 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1509 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1510 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1514 // Hi and Lo for Darwin Global Addresses.
1515 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1516 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1517 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1518 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1519 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1520 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1521 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
1522 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
1523 def : Pat<(PPChi tglobaltlsaddr:$g, GPRC:$in),
1524 (ADDIS GPRC:$in, tglobaltlsaddr:$g)>;
1525 def : Pat<(PPClo tglobaltlsaddr:$g, GPRC:$in),
1526 (ADDIL GPRC:$in, tglobaltlsaddr:$g)>;
1527 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1528 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1529 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1530 (ADDIS GPRC:$in, tconstpool:$g)>;
1531 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1532 (ADDIS GPRC:$in, tjumptable:$g)>;
1533 def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)),
1534 (ADDIS GPRC:$in, tblockaddress:$g)>;
1536 // Standard shifts. These are represented separately from the real shifts above
1537 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1539 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1540 (SRAW GPRC:$rS, GPRC:$rB)>;
1541 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1542 (SRW GPRC:$rS, GPRC:$rB)>;
1543 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1544 (SLW GPRC:$rS, GPRC:$rB)>;
1546 def : Pat<(zextloadi1 iaddr:$src),
1548 def : Pat<(zextloadi1 xaddr:$src),
1550 def : Pat<(extloadi1 iaddr:$src),
1552 def : Pat<(extloadi1 xaddr:$src),
1554 def : Pat<(extloadi8 iaddr:$src),
1556 def : Pat<(extloadi8 xaddr:$src),
1558 def : Pat<(extloadi16 iaddr:$src),
1560 def : Pat<(extloadi16 xaddr:$src),
1562 def : Pat<(f64 (extloadf32 iaddr:$src)),
1563 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
1564 def : Pat<(f64 (extloadf32 xaddr:$src)),
1565 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
1567 def : Pat<(f64 (fextend F4RC:$src)),
1568 (COPY_TO_REGCLASS F4RC:$src, F8RC)>;
1571 def : Pat<(membarrier (i32 imm /*ll*/),
1575 (i32 imm /*device*/)),
1578 def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
1580 include "PPCInstrAltivec.td"
1581 include "PPCInstr64Bit.td"