1 //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PowerPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // Selection DAG Type Constraint definitions.
20 // Note that the semantics of these constraints are hard coded into tblgen. To
21 // modify or add constraints, you have to hack tblgen.
24 class SDTypeConstraint<int opnum> {
25 int OperandNum = opnum;
28 // SDTCisVT - The specified operand has exactly this VT.
29 class SDTCisVT <int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
33 // SDTCisInt - The specified operand is has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand is has floating point type.
37 class SDTCisFP <int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisSameAs - The two specified operands have identical types.
40 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
41 int OtherOperandNum = OtherOp;
44 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
45 // smaller than the 'Other' operand.
46 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
47 int OtherOperandNum = OtherOp;
50 //===----------------------------------------------------------------------===//
51 // Selection DAG Type Profile definitions.
53 // These use the constraints defined above to describe the type requirements of
54 // the various nodes. These are not hard coded into tblgen, allowing targets to
55 // add their own if needed.
58 // SDTypeProfile - This profile describes the type requirements of a Selection
60 class SDTypeProfile<int numresults, int numoperands,
61 list<SDTypeConstraint> constraints> {
62 int NumResults = numresults;
63 int NumOperands = numoperands;
64 list<SDTypeConstraint> Constraints = constraints;
68 def SDTImm : SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
69 def SDTVT : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'
70 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
71 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
73 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
74 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
76 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
77 SDTCisSameAs<0, 1>, SDTCisInt<0>
79 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
80 SDTCisSameAs<0, 1>, SDTCisFP<0>
82 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
83 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
84 SDTCisVTSmallerThanOp<2, 1>
87 //===----------------------------------------------------------------------===//
88 // Selection DAG Node Properties.
90 // Note: These are hard coded into tblgen.
93 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
94 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
96 //===----------------------------------------------------------------------===//
97 // Selection DAG Node definitions.
99 class SDNode<string opcode, SDTypeProfile typeprof,
100 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
101 string Opcode = opcode;
102 string SDClass = sdclass;
103 list<SDNodeProperty> Properties = props;
104 SDTypeProfile TypeProfile = typeprof;
110 def imm : SDNode<"ISD::Constant" , SDTImm , [], "ConstantSDNode">;
111 def vt : SDNode<"ISD::VALUETYPE" , SDTVT , [], "VTSDNode">;
112 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
113 [SDNPCommutative, SDNPAssociative]>;
114 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
115 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
116 [SDNPCommutative, SDNPAssociative]>;
117 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
118 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
119 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
120 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
121 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
122 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
123 def srl : SDNode<"ISD::SRL" , SDTIntBinOp>;
124 def sra : SDNode<"ISD::SRA" , SDTIntBinOp>;
125 def shl : SDNode<"ISD::SHL" , SDTIntBinOp>;
126 def and : SDNode<"ISD::AND" , SDTIntBinOp,
127 [SDNPCommutative, SDNPAssociative]>;
128 def or : SDNode<"ISD::OR" , SDTIntBinOp,
129 [SDNPCommutative, SDNPAssociative]>;
130 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
131 [SDNPCommutative, SDNPAssociative]>;
132 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
133 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
134 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
135 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
136 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
137 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
138 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
139 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
141 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
142 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
144 //===----------------------------------------------------------------------===//
145 // Selection DAG Node Transformation Functions.
147 // This mechanism allows targets to manipulate nodes in the output DAG once a
148 // match has been formed. This is typically used to manipulate immediate
151 class SDNodeXForm<SDNode opc, code xformFunction> {
153 code XFormFunction = xformFunction;
156 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
159 //===----------------------------------------------------------------------===//
160 // Selection DAG Pattern Fragments.
162 // Pattern fragments are reusable chunks of dags that match specific things.
163 // They can take arguments and have C++ predicates that control whether they
164 // match. They are intended to make the patterns for common instructions more
165 // compact and readable.
168 /// PatFrag - Represents a pattern fragment. This can match something on the
169 /// DAG, frame a single node to multiply nested other fragments.
171 class PatFrag<dag ops, dag frag, code pred = [{}],
172 SDNodeXForm xform = NOOP_SDNodeXForm> {
175 code Predicate = pred;
176 SDNodeXForm OperandTransform = xform;
179 // PatLeaf's are pattern fragments that have no operands. This is just a helper
180 // to define immediates and other common things concisely.
181 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
182 : PatFrag<(ops), frag, pred, xform>;
186 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
187 def immZero : PatLeaf<(imm), [{ return N->isNullValue(); }]>;
189 def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
190 def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
192 // Other helper fragments.
194 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
195 def ineg : PatFrag<(ops node:$in), (sub immZero, node:$in)>;
197 //===----------------------------------------------------------------------===//
198 // Selection DAG Pattern Support.
200 // Patterns are what are actually matched against the target-flavored
201 // instruction selection DAG. Instructions defined by the target implicitly
202 // define patterns in most cases, but patterns can also be explicitly added when
203 // an operation is defined by a sequence of instructions (e.g. loading a large
204 // immediate value on RISC targets that do not support immediates as large as
208 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
209 dag PatternToMatch = patternToMatch;
210 list<dag> ResultInstrs = resultInstrs;
213 // Pat - A simple (but common) form of a pattern, which produces a simple result
214 // not needing a full list.
215 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
217 //===----------------------------------------------------------------------===//
218 // PowerPC specific transformation functions and pattern fragments.
220 def LO16 : SDNodeXForm<imm, [{
221 // Transformation function: get the low 16 bits.
222 return getI32Imm((unsigned short)N->getValue());
225 def HI16 : SDNodeXForm<imm, [{
226 // Transformation function: shift the immediate value down into the low bits.
227 return getI32Imm((unsigned)N->getValue() >> 16);
230 def HA16 : SDNodeXForm<imm, [{
231 // Transformation function: shift the immediate value down into the low bits.
232 signed int Val = N->getValue();
233 return getI32Imm((Val - (signed short)Val) >> 16);
237 def immSExt16 : PatLeaf<(imm), [{
238 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
239 // field. Used by instructions like 'addi'.
240 return (int)N->getValue() == (short)N->getValue();
242 def immZExt16 : PatLeaf<(imm), [{
243 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
244 // field. Used by instructions like 'ori'.
245 return (unsigned)N->getValue() == (unsigned short)N->getValue();
248 def imm16Shifted : PatLeaf<(imm), [{
249 // imm16Shifted predicate - True if only bits in the top 16-bits of the
250 // immediate are set. Used by instructions like 'addis'.
251 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
255 // Example of a legalize expander: Only for PPC64.
256 def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
257 [(set f64:$tmp , (FCTIDZ f64:$src)),
258 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
259 (store f64:$tmp, i32:$tmpFI),
260 (set i64:$dst, (load i32:$tmpFI))],
264 //===----------------------------------------------------------------------===//
265 // PowerPC Flag Definitions.
267 class isPPC64 { bit PPC64 = 1; }
268 class isVMX { bit VMX = 1; }
270 list<Register> Defs = [CR0];
276 //===----------------------------------------------------------------------===//
277 // PowerPC Operand Definitions.
279 def u5imm : Operand<i32> {
280 let PrintMethod = "printU5ImmOperand";
282 def u6imm : Operand<i32> {
283 let PrintMethod = "printU6ImmOperand";
285 def s16imm : Operand<i32> {
286 let PrintMethod = "printS16ImmOperand";
288 def u16imm : Operand<i32> {
289 let PrintMethod = "printU16ImmOperand";
291 def target : Operand<i32> {
292 let PrintMethod = "printBranchOperand";
294 def piclabel: Operand<i32> {
295 let PrintMethod = "printPICLabel";
297 def symbolHi: Operand<i32> {
298 let PrintMethod = "printSymbolHi";
300 def symbolLo: Operand<i32> {
301 let PrintMethod = "printSymbolLo";
303 def crbitm: Operand<i8> {
304 let PrintMethod = "printcrbitm";
309 //===----------------------------------------------------------------------===//
310 // PowerPC Instruction Definitions.
312 // Pseudo-instructions:
313 def PHI : Pseudo<(ops variable_ops), "; PHI">;
316 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN">;
317 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP">;
319 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
320 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8">;
321 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4">;
323 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
324 // scheduler into a branch sequence.
325 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
326 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
327 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
328 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
329 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
330 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
331 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
335 let isTerminator = 1 in {
337 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr">;
338 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr">;
342 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
344 let isBranch = 1, isTerminator = 1 in {
345 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
346 target:$true, target:$false),
348 def B : IForm<18, 0, 0, (ops target:$func), "b $func">;
349 //def BA : IForm<18, 1, 0, (ops target:$func), "ba $func">;
350 def BL : IForm<18, 0, 1, (ops target:$func), "bl $func">;
351 //def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func">;
353 // FIXME: 4*CR# needs to be added to the BI field!
354 // This will only work for CR0 as it stands now
355 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
357 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
359 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
361 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
363 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
365 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
370 // All calls clobber the non-callee saved registers...
371 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
372 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
374 CR0,CR1,CR5,CR6,CR7] in {
375 // Convenient aliases for call instructions
376 def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops), "bl $func">;
377 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1,
378 (ops variable_ops), "bctrl">;
381 // D-Form instructions. Most instructions that perform an operation on a
382 // register and an immediate are of this type.
385 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
386 "lbz $rD, $disp($rA)">;
387 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
388 "lha $rD, $disp($rA)">;
389 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
390 "lhz $rD, $disp($rA)">;
391 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
392 "lmw $rD, $disp($rA)">;
393 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
394 "lwz $rD, $disp($rA)">;
395 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
396 "lwzu $rD, $disp($rA)">;
398 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
399 "addi $rD, $rA, $imm",
400 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
401 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
402 "addic $rD, $rA, $imm",
404 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
405 "addic. $rD, $rA, $imm",
407 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
408 "addis $rD, $rA, $imm",
409 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
410 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
413 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
414 "mulli $rD, $rA, $imm",
415 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
416 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
417 "subfic $rD, $rA, $imm",
418 [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>;
419 def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
421 [(set GPRC:$rD, immSExt16:$imm)]>;
422 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
424 [(set GPRC:$rD, imm16Shifted:$imm)]>;
426 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
427 "stmw $rS, $disp($rA)">;
428 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
429 "stb $rS, $disp($rA)">;
430 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
431 "sth $rS, $disp($rA)">;
432 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
433 "stw $rS, $disp($rA)">;
434 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
435 "stwu $rS, $disp($rA)">;
437 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
438 "andi. $dst, $src1, $src2",
440 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
441 "andis. $dst, $src1, $src2",
443 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
444 "ori $dst, $src1, $src2",
445 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
446 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
447 "oris $dst, $src1, $src2",
448 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
449 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
450 "xori $dst, $src1, $src2",
451 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
452 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
453 "xoris $dst, $src1, $src2",
454 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
455 def NOP : DForm_4_zero<24, (ops), "nop">;
456 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
457 "cmpi $crD, $L, $rA, $imm">;
458 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
459 "cmpwi $crD, $rA, $imm">;
460 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
461 "cmpdi $crD, $rA, $imm">, isPPC64;
462 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
463 "cmpli $dst, $size, $src1, $src2">;
464 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
465 "cmplwi $dst, $src1, $src2">;
466 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
467 "cmpldi $dst, $src1, $src2">, isPPC64;
469 def LFS : DForm_8<48, (ops F4RC:$rD, symbolLo:$disp, GPRC:$rA),
470 "lfs $rD, $disp($rA)">;
471 def LFD : DForm_8<50, (ops F8RC:$rD, symbolLo:$disp, GPRC:$rA),
472 "lfd $rD, $disp($rA)">;
475 def STFS : DForm_9<52, (ops F4RC:$rS, symbolLo:$disp, GPRC:$rA),
476 "stfs $rS, $disp($rA)">;
477 def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA),
478 "stfd $rS, $disp($rA)">;
481 // DS-Form instructions. Load/Store instructions available in PPC-64
484 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
485 "lwa $rT, $DS($rA)">, isPPC64;
486 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
487 "ld $rT, $DS($rA)">, isPPC64;
490 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
491 "std $rT, $DS($rA)">, isPPC64;
492 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
493 "stdu $rT, $DS($rA)">, isPPC64;
496 // X-Form instructions. Most instructions that perform an operation on a
497 // register and another register are of this type.
500 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
501 "lbzx $dst, $base, $index">;
502 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
503 "lhax $dst, $base, $index">;
504 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
505 "lhzx $dst, $base, $index">;
506 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
507 "lwax $dst, $base, $index">, isPPC64;
508 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
509 "lwzx $dst, $base, $index">;
510 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
511 "ldx $dst, $base, $index">, isPPC64;
513 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
514 "nand $rA, $rS, $rB",
515 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
516 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
518 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
519 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
520 "and. $rA, $rS, $rB",
522 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
523 "andc $rA, $rS, $rB",
524 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
525 def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
527 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
528 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
530 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
531 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
534 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
536 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
537 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
539 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
540 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
542 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
543 def SLD : XForm_6<31, 27, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
546 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
548 [(set GPRC:$rA, (shl GPRC:$rS, GPRC:$rB))]>;
549 def SRD : XForm_6<31, 539, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
552 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
554 [(set GPRC:$rA, (srl GPRC:$rS, GPRC:$rB))]>;
555 def SRAD : XForm_6<31, 794, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
556 "srad $rA, $rS, $rB",
558 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
559 "sraw $rA, $rS, $rB",
560 [(set GPRC:$rA, (sra GPRC:$rS, GPRC:$rB))]>;
562 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
563 "stbx $rS, $rA, $rB">;
564 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
565 "sthx $rS, $rA, $rB">;
566 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
567 "stwx $rS, $rA, $rB">;
568 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
569 "stwux $rS, $rA, $rB">;
570 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
571 "stdx $rS, $rA, $rB">, isPPC64;
572 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
573 "stdux $rS, $rA, $rB">, isPPC64;
575 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
576 "srawi $rA, $rS, $SH",
577 [(set GPRC:$rA, (sra GPRC:$rS, imm:$SH))]>;
578 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
580 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
581 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
583 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
584 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
586 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
587 def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
590 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
591 "cmp $crD, $long, $rA, $rB">;
592 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
593 "cmpl $crD, $long, $rA, $rB">;
594 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
595 "cmpw $crD, $rA, $rB">;
596 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
597 "cmpd $crD, $rA, $rB">, isPPC64;
598 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
599 "cmplw $crD, $rA, $rB">;
600 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
601 "cmpld $crD, $rA, $rB">, isPPC64;
602 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
603 // "fcmpo $crD, $fA, $fB">;
604 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
605 "fcmpu $crD, $fA, $fB">;
606 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
607 "fcmpu $crD, $fA, $fB">;
610 def LFSX : XForm_25<31, 535, (ops F4RC:$dst, GPRC:$base, GPRC:$index),
611 "lfsx $dst, $base, $index">;
612 def LFDX : XForm_25<31, 599, (ops F8RC:$dst, GPRC:$base, GPRC:$index),
613 "lfdx $dst, $base, $index">;
615 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
618 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
621 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
624 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
627 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
629 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
630 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
634 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
635 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
637 []>; // (set F4RC:$frD, F4RC:$frB)
638 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
640 []>; // (set F8RC:$frD, F8RC:$frB)
641 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
643 []>; // (set F8RC:$frD, (fpextend F4RC:$frB))
645 // These are artificially split into two different forms, for 4/8 byte FP.
646 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
648 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
649 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
651 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
652 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
654 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
655 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
657 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
658 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
660 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
661 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
663 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
667 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, GPRC:$rA, GPRC:$rB),
668 "stfsx $frS, $rA, $rB">;
669 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, GPRC:$rA, GPRC:$rB),
670 "stfdx $frS, $rA, $rB">;
673 // XL-Form instructions. condition register logical ops.
675 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
678 // XFX-Form instructions. Instructions that deal with SPRs
680 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
681 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
682 // which means the SPR value needs to be multiplied by a factor of 32.
683 def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT">;
684 def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT">;
685 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT">;
686 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
688 def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
690 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS">;
691 def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS">;
693 // XS-Form instructions. Just 'sradi'
695 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
696 "sradi $rA, $rS, $SH">, isPPC64;
698 // XO-Form instructions. Arithmetic instructions that can set overflow bit
700 def ADD : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
702 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
703 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
704 "addc $rT, $rA, $rB",
706 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
707 "adde $rT, $rA, $rB",
709 def DIVD : XOForm_1<31, 489, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
710 "divd $rT, $rA, $rB",
712 def DIVDU : XOForm_1<31, 457, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
713 "divdu $rT, $rA, $rB",
715 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
716 "divw $rT, $rA, $rB",
717 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
718 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
719 "divwu $rT, $rA, $rB",
720 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
721 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
722 "mulhw $rT, $rA, $rB",
723 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
724 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
725 "mulhwu $rT, $rA, $rB",
726 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
727 def MULLD : XOForm_1<31, 233, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
728 "mulld $rT, $rA, $rB",
730 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
731 "mullw $rT, $rA, $rB",
732 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
733 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
734 "subf $rT, $rA, $rB",
735 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
736 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
737 "subfc $rT, $rA, $rB",
739 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
740 "subfe $rT, $rA, $rB",
742 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
745 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
748 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
750 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
751 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
755 // A-Form instructions. Most of the instructions executed in the FPU are of
758 def FMADD : AForm_1<63, 29,
759 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
760 "fmadd $FRT, $FRA, $FRC, $FRB",
761 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
763 def FMADDS : AForm_1<59, 29,
764 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
765 "fmadds $FRT, $FRA, $FRC, $FRB",
767 def FMSUB : AForm_1<63, 28,
768 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
769 "fmsub $FRT, $FRA, $FRC, $FRB",
770 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
772 def FMSUBS : AForm_1<59, 28,
773 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
774 "fmsubs $FRT, $FRA, $FRC, $FRB",
776 def FNMADD : AForm_1<63, 31,
777 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
778 "fnmadd $FRT, $FRA, $FRC, $FRB",
779 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
781 def FNMADDS : AForm_1<59, 31,
782 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
783 "fnmadds $FRT, $FRA, $FRC, $FRB",
785 def FNMSUB : AForm_1<63, 30,
786 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
787 "fnmsub $FRT, $FRA, $FRC, $FRB",
788 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
790 def FNMSUBS : AForm_1<59, 30,
791 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
792 "fnmsubs $FRT, $FRA, $FRC, $FRB",
794 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
795 // having 4 of these, force the comparison to always be an 8-byte double (code
796 // should use an FMRSD if the input comparison value really wants to be a float)
797 // and 4/8 byte forms for the result and operand type..
798 def FSELD : AForm_1<63, 23,
799 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
800 "fsel $FRT, $FRA, $FRC, $FRB",
802 def FSELS : AForm_1<63, 23,
803 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
804 "fsel $FRT, $FRA, $FRC, $FRB",
806 def FADD : AForm_2<63, 21,
807 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
808 "fadd $FRT, $FRA, $FRB",
809 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
810 def FADDS : AForm_2<59, 21,
811 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
812 "fadds $FRT, $FRA, $FRB",
814 def FDIV : AForm_2<63, 18,
815 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
816 "fdiv $FRT, $FRA, $FRB",
817 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
818 def FDIVS : AForm_2<59, 18,
819 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
820 "fdivs $FRT, $FRA, $FRB",
822 def FMUL : AForm_3<63, 25,
823 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
824 "fmul $FRT, $FRA, $FRB",
825 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
826 def FMULS : AForm_3<59, 25,
827 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
828 "fmuls $FRT, $FRA, $FRB",
830 def FSUB : AForm_2<63, 20,
831 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
832 "fsub $FRT, $FRA, $FRB",
833 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
834 def FSUBS : AForm_2<59, 20,
835 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
836 "fsubs $FRT, $FRA, $FRB",
839 // M-Form instructions. rotate and mask instructions.
841 let isTwoAddress = 1, isCommutable = 1 in {
842 // RLWIMI can be commuted if the rotate amount is zero.
843 def RLWIMI : MForm_2<20,
844 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
845 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
847 def RLWINM : MForm_2<21,
848 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
849 "rlwinm $rA, $rS, $SH, $MB, $ME">;
850 def RLWINMo : MForm_2<21,
851 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
852 "rlwinm. $rA, $rS, $SH, $MB, $ME">, isDOT;
853 def RLWNM : MForm_2<23,
854 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
855 "rlwnm $rA, $rS, $rB, $MB, $ME">;
857 // MD-Form instructions. 64 bit rotate instructions.
859 def RLDICL : MDForm_1<30, 0,
860 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
861 "rldicl $rA, $rS, $SH, $MB">, isPPC64;
862 def RLDICR : MDForm_1<30, 1,
863 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
864 "rldicr $rA, $rS, $SH, $ME">, isPPC64;
866 //===----------------------------------------------------------------------===//
867 // PowerPC Instruction Patterns
870 // Arbitrary immediate support. Implement in terms of LIS/ORI.
871 def : Pat<(i32 imm:$imm),
872 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
874 // Implement the 'not' operation with the NOR instruction.
875 def NOT : Pat<(not GPRC:$in),
876 (NOR GPRC:$in, GPRC:$in)>;
878 // ADD an arbitrary immediate.
879 def : Pat<(add GPRC:$in, imm:$imm),
880 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
881 // OR an arbitrary immediate.
882 def : Pat<(or GPRC:$in, imm:$imm),
883 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
884 // XOR an arbitrary immediate.
885 def : Pat<(xor GPRC:$in, imm:$imm),
886 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
890 // Same as above, but using a temporary. FIXME: implement temporaries :)
892 def : Pattern<(xor GPRC:$in, imm:$imm),
893 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
894 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>;
898 //===----------------------------------------------------------------------===//
899 // PowerPCInstrInfo Definition
901 def PowerPCInstrInfo : InstrInfo {
904 let TSFlagsFields = [ "VMX", "PPC64" ];
905 let TSFlagsShifts = [ 0, 1 ];
907 let isLittleEndianEncoding = 1;