1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific DAG Nodes.
21 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
22 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
23 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
25 def PPCfsel : SDNode<"PPCISD::FSEL",
26 // Type constraint for fsel.
27 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
28 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
30 //===----------------------------------------------------------------------===//
31 // PowerPC specific transformation functions and pattern fragments.
34 def SHL32 : SDNodeXForm<imm, [{
35 // Transformation function: 31 - imm
36 return getI32Imm(31 - N->getValue());
39 def SHL64 : SDNodeXForm<imm, [{
40 // Transformation function: 63 - imm
41 return getI32Imm(63 - N->getValue());
44 def SRL32 : SDNodeXForm<imm, [{
45 // Transformation function: 32 - imm
46 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
49 def SRL64 : SDNodeXForm<imm, [{
50 // Transformation function: 64 - imm
51 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
54 def LO16 : SDNodeXForm<imm, [{
55 // Transformation function: get the low 16 bits.
56 return getI32Imm((unsigned short)N->getValue());
59 def HI16 : SDNodeXForm<imm, [{
60 // Transformation function: shift the immediate value down into the low bits.
61 return getI32Imm((unsigned)N->getValue() >> 16);
64 def HA16 : SDNodeXForm<imm, [{
65 // Transformation function: shift the immediate value down into the low bits.
66 signed int Val = N->getValue();
67 return getI32Imm((Val - (signed short)Val) >> 16);
71 def immSExt16 : PatLeaf<(imm), [{
72 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
73 // field. Used by instructions like 'addi'.
74 return (int)N->getValue() == (short)N->getValue();
76 def immZExt16 : PatLeaf<(imm), [{
77 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
78 // field. Used by instructions like 'ori'.
79 return (unsigned)N->getValue() == (unsigned short)N->getValue();
82 def imm16Shifted : PatLeaf<(imm), [{
83 // imm16Shifted predicate - True if only bits in the top 16-bits of the
84 // immediate are set. Used by instructions like 'addis'.
85 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
89 // Example of a legalize expander: Only for PPC64.
90 def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
91 [(set f64:$tmp , (FCTIDZ f64:$src)),
92 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
93 (store f64:$tmp, i32:$tmpFI),
94 (set i64:$dst, (load i32:$tmpFI))],
98 //===----------------------------------------------------------------------===//
99 // PowerPC Flag Definitions.
101 class isPPC64 { bit PPC64 = 1; }
102 class isVMX { bit VMX = 1; }
104 list<Register> Defs = [CR0];
110 //===----------------------------------------------------------------------===//
111 // PowerPC Operand Definitions.
113 def u5imm : Operand<i32> {
114 let PrintMethod = "printU5ImmOperand";
116 def u6imm : Operand<i32> {
117 let PrintMethod = "printU6ImmOperand";
119 def s16imm : Operand<i32> {
120 let PrintMethod = "printS16ImmOperand";
122 def u16imm : Operand<i32> {
123 let PrintMethod = "printU16ImmOperand";
125 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
126 let PrintMethod = "printS16X4ImmOperand";
128 def target : Operand<i32> {
129 let PrintMethod = "printBranchOperand";
131 def aaddr : Operand<i32> {
132 let PrintMethod = "printAbsAddrOperand";
134 def piclabel: Operand<i32> {
135 let PrintMethod = "printPICLabel";
137 def symbolHi: Operand<i32> {
138 let PrintMethod = "printSymbolHi";
140 def symbolLo: Operand<i32> {
141 let PrintMethod = "printSymbolLo";
143 def crbitm: Operand<i8> {
144 let PrintMethod = "printcrbitm";
149 //===----------------------------------------------------------------------===//
150 // PowerPC Instruction Definitions.
152 // Pseudo-instructions:
153 def PHI : Pseudo<(ops variable_ops), "; PHI", []>;
156 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN", []>;
157 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP", []>;
159 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
160 [(set GPRC:$rD, (undef))]>;
161 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8",
162 [(set F8RC:$rD, (undef))]>;
163 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4",
164 [(set F4RC:$rD, (undef))]>;
166 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
167 // scheduler into a branch sequence.
168 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
169 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
170 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
171 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
172 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
173 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
174 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
178 let isTerminator = 1 in {
180 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB>;
181 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB>;
185 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>;
187 let isBranch = 1, isTerminator = 1 in {
188 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
189 target:$true, target:$false),
190 "; COND_BRANCH", []>;
191 def B : IForm<18, 0, 0, (ops target:$func), "b $func", BrB>;
193 // FIXME: 4*CR# needs to be added to the BI field!
194 // This will only work for CR0 as it stands now
195 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
196 "blt $crS, $block", BrB>;
197 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
198 "ble $crS, $block", BrB>;
199 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
200 "beq $crS, $block", BrB>;
201 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
202 "bge $crS, $block", BrB>;
203 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
204 "bgt $crS, $block", BrB>;
205 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
206 "bne $crS, $block", BrB>;
207 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
208 "bun $crS, $block", BrB>;
209 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
210 "bnu $crS, $block", BrB>;
214 // All calls clobber the non-callee saved registers...
215 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
216 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
218 CR0,CR1,CR5,CR6,CR7] in {
219 // Convenient aliases for call instructions
220 def BL : IForm<18, 0, 1, (ops target:$func, variable_ops), "bl $func", BrB>;
221 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops), "bla $func", BrB>;
222 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB>;
225 // D-Form instructions. Most instructions that perform an operation on a
226 // register and an immediate are of this type.
229 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
230 "lbz $rD, $disp($rA)", LdStGeneral>;
231 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
232 "lha $rD, $disp($rA)", LdStLHA>;
233 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
234 "lhz $rD, $disp($rA)", LdStGeneral>;
235 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
236 "lmw $rD, $disp($rA)", LdStLMW>;
237 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
238 "lwz $rD, $disp($rA)", LdStGeneral>;
239 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
240 "lwzu $rD, $disp($rA)", LdStGeneral>;
242 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
243 "addi $rD, $rA, $imm", IntGeneral,
244 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
245 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
246 "addic $rD, $rA, $imm", IntGeneral,
248 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
249 "addic. $rD, $rA, $imm", IntGeneral,
251 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
252 "addis $rD, $rA, $imm", IntGeneral,
253 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
254 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
255 "la $rD, $sym($rA)", IntGeneral,
257 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
258 "mulli $rD, $rA, $imm", IntMulLI,
259 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
260 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
261 "subfic $rD, $rA, $imm", IntGeneral,
262 [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>;
263 def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
264 "li $rD, $imm", IntGeneral,
265 [(set GPRC:$rD, immSExt16:$imm)]>;
266 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
267 "lis $rD, $imm", IntGeneral,
268 [(set GPRC:$rD, imm16Shifted:$imm)]>;
270 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
271 "stmw $rS, $disp($rA)", LdStLMW>;
272 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
273 "stb $rS, $disp($rA)", LdStGeneral>;
274 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
275 "sth $rS, $disp($rA)", LdStGeneral>;
276 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
277 "stw $rS, $disp($rA)", LdStGeneral>;
278 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
279 "stwu $rS, $disp($rA)", LdStGeneral>;
281 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
282 "andi. $dst, $src1, $src2", IntGeneral,
284 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
285 "andis. $dst, $src1, $src2", IntGeneral,
287 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
288 "ori $dst, $src1, $src2", IntGeneral,
289 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
290 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
291 "oris $dst, $src1, $src2", IntGeneral,
292 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
293 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
294 "xori $dst, $src1, $src2", IntGeneral,
295 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
296 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
297 "xoris $dst, $src1, $src2", IntGeneral,
298 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
299 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral>;
300 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
301 "cmpi $crD, $L, $rA, $imm", IntCompare>;
302 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
303 "cmpwi $crD, $rA, $imm", IntCompare>;
304 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
305 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
306 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
307 "cmpli $dst, $size, $src1, $src2", IntCompare>;
308 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
309 "cmplwi $dst, $src1, $src2", IntCompare>;
310 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
311 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
313 def LFS : DForm_8<48, (ops F4RC:$rD, symbolLo:$disp, GPRC:$rA),
314 "lfs $rD, $disp($rA)", LdStLFDU>;
315 def LFD : DForm_8<50, (ops F8RC:$rD, symbolLo:$disp, GPRC:$rA),
316 "lfd $rD, $disp($rA)", LdStLFD>;
319 def STFS : DForm_9<52, (ops F4RC:$rS, symbolLo:$disp, GPRC:$rA),
320 "stfs $rS, $disp($rA)", LdStUX>;
321 def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA),
322 "stfd $rS, $disp($rA)", LdStUX>;
325 // DS-Form instructions. Load/Store instructions available in PPC-64
328 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
329 "lwa $rT, $DS($rA)", LdStLWA>, isPPC64;
330 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
331 "ld $rT, $DS($rA)", LdStLD>, isPPC64;
334 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
335 "std $rT, $DS($rA)", LdStSTD>, isPPC64;
336 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
337 "stdu $rT, $DS($rA)", LdStSTD>, isPPC64;
340 // X-Form instructions. Most instructions that perform an operation on a
341 // register and another register are of this type.
344 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
345 "lbzx $dst, $base, $index", LdStGeneral>;
346 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
347 "lhax $dst, $base, $index", LdStLHA>;
348 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
349 "lhzx $dst, $base, $index", LdStGeneral>;
350 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
351 "lwax $dst, $base, $index", LdStLHA>, isPPC64;
352 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
353 "lwzx $dst, $base, $index", LdStGeneral>;
354 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
355 "ldx $dst, $base, $index", LdStLD>, isPPC64;
357 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
358 "nand $rA, $rS, $rB", IntGeneral,
359 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
360 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
361 "and $rA, $rS, $rB", IntGeneral,
362 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
363 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
364 "and. $rA, $rS, $rB", IntGeneral,
366 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
367 "andc $rA, $rS, $rB", IntGeneral,
368 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
369 def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
370 "or $rA, $rS, $rB", IntGeneral,
371 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
372 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
373 "or $rA, $rS, $rB", IntGeneral,
374 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
375 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
376 "or $rA, $rS, $rB", IntGeneral,
378 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
379 "or $rA, $rS, $rB", IntGeneral,
381 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
382 "nor $rA, $rS, $rB", IntGeneral,
383 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
384 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
385 "or. $rA, $rS, $rB", IntGeneral,
387 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
388 "orc $rA, $rS, $rB", IntGeneral,
389 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
390 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
391 "eqv $rA, $rS, $rB", IntGeneral,
392 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
393 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
394 "xor $rA, $rS, $rB", IntGeneral,
395 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
396 def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
397 "sld $rA, $rS, $rB", IntRotateD,
398 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
399 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
400 "slw $rA, $rS, $rB", IntGeneral,
401 [(set GPRC:$rA, (shl GPRC:$rS, GPRC:$rB))]>;
402 def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
403 "srd $rA, $rS, $rB", IntRotateD,
404 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
405 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
406 "srw $rA, $rS, $rB", IntGeneral,
407 [(set GPRC:$rA, (srl GPRC:$rS, GPRC:$rB))]>;
408 def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
409 "srad $rA, $rS, $rB", IntRotateD,
410 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
411 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
412 "sraw $rA, $rS, $rB", IntShift,
413 [(set GPRC:$rA, (sra GPRC:$rS, GPRC:$rB))]>;
415 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
416 "stbx $rS, $rA, $rB", LdStGeneral>;
417 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
418 "sthx $rS, $rA, $rB", LdStGeneral>;
419 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
420 "stwx $rS, $rA, $rB", LdStGeneral>;
421 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
422 "stwux $rS, $rA, $rB", LdStGeneral>;
423 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
424 "stdx $rS, $rA, $rB", LdStSTD>, isPPC64;
425 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
426 "stdux $rS, $rA, $rB", LdStSTD>, isPPC64;
428 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
429 "srawi $rA, $rS, $SH", IntShift,
430 [(set GPRC:$rA, (sra GPRC:$rS, imm:$SH))]>;
431 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
432 "cntlzw $rA, $rS", IntGeneral,
433 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
434 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
435 "extsb $rA, $rS", IntGeneral,
436 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
437 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
438 "extsh $rA, $rS", IntGeneral,
439 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
440 def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
441 "extsw $rA, $rS", IntRotateD,
443 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
444 "cmp $crD, $long, $rA, $rB", IntCompare>;
445 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
446 "cmpl $crD, $long, $rA, $rB", IntCompare>;
447 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
448 "cmpw $crD, $rA, $rB", IntCompare>;
449 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
450 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
451 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
452 "cmplw $crD, $rA, $rB", IntCompare>;
453 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
454 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
455 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
456 // "fcmpo $crD, $fA, $fB", FPCompare>;
457 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
458 "fcmpu $crD, $fA, $fB", FPCompare>;
459 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
460 "fcmpu $crD, $fA, $fB", FPCompare>;
463 def LFSX : XForm_25<31, 535, (ops F4RC:$dst, GPRC:$base, GPRC:$index),
464 "lfsx $dst, $base, $index", LdStLFDU>;
465 def LFDX : XForm_25<31, 599, (ops F8RC:$dst, GPRC:$base, GPRC:$index),
466 "lfdx $dst, $base, $index", LdStLFDU>;
468 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
469 "fcfid $frD, $frB", FPGeneral,
470 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
471 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
472 "fctidz $frD, $frB", FPGeneral,
473 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
474 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
475 "fctiwz $frD, $frB", FPGeneral,
476 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
477 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
478 "frsp $frD, $frB", FPGeneral,
479 [(set F4RC:$frD, (fround F8RC:$frB))]>;
480 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
481 "fsqrt $frD, $frB", FPSqrt,
482 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
483 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
484 "fsqrts $frD, $frB", FPSqrt,
485 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
487 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
488 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
489 "fmr $frD, $frB", FPGeneral,
490 []>; // (set F4RC:$frD, F4RC:$frB)
491 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
492 "fmr $frD, $frB", FPGeneral,
493 []>; // (set F8RC:$frD, F8RC:$frB)
494 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
495 "fmr $frD, $frB", FPGeneral,
496 [(set F8RC:$frD, (fextend F4RC:$frB))]>;
498 // These are artificially split into two different forms, for 4/8 byte FP.
499 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
500 "fabs $frD, $frB", FPGeneral,
501 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
502 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
503 "fabs $frD, $frB", FPGeneral,
504 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
505 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
506 "fnabs $frD, $frB", FPGeneral,
507 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
508 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
509 "fnabs $frD, $frB", FPGeneral,
510 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
511 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
512 "fneg $frD, $frB", FPGeneral,
513 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
514 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
515 "fneg $frD, $frB", FPGeneral,
516 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
520 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, GPRC:$rA, GPRC:$rB),
521 "stfsx $frS, $rA, $rB", LdStUX>;
522 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, GPRC:$rA, GPRC:$rB),
523 "stfdx $frS, $rA, $rB", LdStUX>;
526 // XL-Form instructions. condition register logical ops.
528 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
529 "mcrf $BF, $BFA", BrMCR>;
531 // XFX-Form instructions. Instructions that deal with SPRs
533 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
534 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
535 // which means the SPR value needs to be multiplied by a factor of 32.
536 def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>;
537 def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT", SprMFSPR>;
538 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>;
539 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
540 "mtcrf $FXM, $rS", BrMCRX>;
541 def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
542 "mfcr $rT, $FXM", SprMFCR>;
543 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>;
544 def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>;
546 // XS-Form instructions. Just 'sradi'
548 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
549 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
551 // XO-Form instructions. Arithmetic instructions that can set overflow bit
553 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
554 "add $rT, $rA, $rB", IntGeneral,
555 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
556 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
557 "add $rT, $rA, $rB", IntGeneral,
558 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
559 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
560 "addc $rT, $rA, $rB", IntGeneral,
562 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
563 "adde $rT, $rA, $rB", IntGeneral,
565 def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
566 "divd $rT, $rA, $rB", IntDivD,
567 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
568 def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
569 "divdu $rT, $rA, $rB", IntDivD,
570 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
571 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
572 "divw $rT, $rA, $rB", IntDivW,
573 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
574 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
575 "divwu $rT, $rA, $rB", IntDivW,
576 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
577 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
578 "mulhd $rT, $rA, $rB", IntMulHW,
579 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
580 def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
581 "mulhdu $rT, $rA, $rB", IntMulHWU,
582 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
583 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
584 "mulhw $rT, $rA, $rB", IntMulHW,
585 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
586 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
587 "mulhwu $rT, $rA, $rB", IntMulHWU,
588 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
589 def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
590 "mulld $rT, $rA, $rB", IntMulHD,
591 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
592 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
593 "mullw $rT, $rA, $rB", IntMulHW,
594 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
595 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
596 "subf $rT, $rA, $rB", IntGeneral,
597 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
598 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
599 "subfc $rT, $rA, $rB", IntGeneral,
601 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
602 "subfe $rT, $rA, $rB", IntGeneral,
604 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
605 "addme $rT, $rA", IntGeneral,
607 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
608 "addze $rT, $rA", IntGeneral,
610 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
611 "neg $rT, $rA", IntGeneral,
612 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
613 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
614 "subfze $rT, $rA", IntGeneral,
617 // A-Form instructions. Most of the instructions executed in the FPU are of
620 def FMADD : AForm_1<63, 29,
621 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
622 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
623 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
625 def FMADDS : AForm_1<59, 29,
626 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
627 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
628 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
630 def FMSUB : AForm_1<63, 28,
631 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
632 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
633 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
635 def FMSUBS : AForm_1<59, 28,
636 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
637 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
638 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
640 def FNMADD : AForm_1<63, 31,
641 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
642 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
643 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
645 def FNMADDS : AForm_1<59, 31,
646 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
647 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
648 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
650 def FNMSUB : AForm_1<63, 30,
651 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
652 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
653 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
655 def FNMSUBS : AForm_1<59, 30,
656 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
657 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
658 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
660 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
661 // having 4 of these, force the comparison to always be an 8-byte double (code
662 // should use an FMRSD if the input comparison value really wants to be a float)
663 // and 4/8 byte forms for the result and operand type..
664 def FSELD : AForm_1<63, 23,
665 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
666 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
667 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
668 def FSELS : AForm_1<63, 23,
669 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
670 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
671 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
672 def FADD : AForm_2<63, 21,
673 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
674 "fadd $FRT, $FRA, $FRB", FPGeneral,
675 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
676 def FADDS : AForm_2<59, 21,
677 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
678 "fadds $FRT, $FRA, $FRB", FPGeneral,
679 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
680 def FDIV : AForm_2<63, 18,
681 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
682 "fdiv $FRT, $FRA, $FRB", FPDivD,
683 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
684 def FDIVS : AForm_2<59, 18,
685 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
686 "fdivs $FRT, $FRA, $FRB", FPDivS,
687 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
688 def FMUL : AForm_3<63, 25,
689 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
690 "fmul $FRT, $FRA, $FRB", FPFused,
691 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
692 def FMULS : AForm_3<59, 25,
693 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
694 "fmuls $FRT, $FRA, $FRB", FPGeneral,
695 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
696 def FSUB : AForm_2<63, 20,
697 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
698 "fsub $FRT, $FRA, $FRB", FPGeneral,
699 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
700 def FSUBS : AForm_2<59, 20,
701 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
702 "fsubs $FRT, $FRA, $FRB", FPGeneral,
703 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
705 // M-Form instructions. rotate and mask instructions.
707 let isTwoAddress = 1, isCommutable = 1 in {
708 // RLWIMI can be commuted if the rotate amount is zero.
709 def RLWIMI : MForm_2<20,
710 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
711 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
713 def RLDIMI : MDForm_1<30, 3,
714 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
715 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
718 def RLWINM : MForm_2<21,
719 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
720 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
722 def RLWINMo : MForm_2<21,
723 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
724 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
726 def RLWNM : MForm_2<23,
727 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
728 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
731 // MD-Form instructions. 64 bit rotate instructions.
733 def RLDICL : MDForm_1<30, 0,
734 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
735 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
737 def RLDICR : MDForm_1<30, 1,
738 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
739 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
742 //===----------------------------------------------------------------------===//
743 // PowerPC Instruction Patterns
746 // Arbitrary immediate support. Implement in terms of LIS/ORI.
747 def : Pat<(i32 imm:$imm),
748 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
750 // Implement the 'not' operation with the NOR instruction.
751 def NOT : Pat<(not GPRC:$in),
752 (NOR GPRC:$in, GPRC:$in)>;
754 // ADD an arbitrary immediate.
755 def : Pat<(add GPRC:$in, imm:$imm),
756 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
757 // OR an arbitrary immediate.
758 def : Pat<(or GPRC:$in, imm:$imm),
759 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
760 // XOR an arbitrary immediate.
761 def : Pat<(xor GPRC:$in, imm:$imm),
762 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
763 def : Pat<(or (shl GPRC:$rS, GPRC:$rB),
764 (srl GPRC:$rS, (sub 32, GPRC:$rB))),
765 (RLWNM GPRC:$rS, GPRC:$rB, 0, 31)>;
767 def : Pat<(zext GPRC:$in),
768 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
769 def : Pat<(anyext GPRC:$in),
770 (OR4To8 GPRC:$in, GPRC:$in)>;
771 def : Pat<(trunc G8RC:$in),
772 (OR8To4 G8RC:$in, G8RC:$in)>;
775 def : Pat<(shl GPRC:$in, imm:$imm),
776 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
777 def : Pat<(shl G8RC:$in, imm:$imm),
778 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
780 def : Pat<(srl GPRC:$in, imm:$imm),
781 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
782 def : Pat<(srl G8RC:$in, imm:$imm),
783 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
785 // Same as above, but using a temporary. FIXME: implement temporaries :)
787 def : Pattern<(xor GPRC:$in, imm:$imm),
788 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
789 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>;
792 //===----------------------------------------------------------------------===//
793 // PowerPCInstrInfo Definition
795 def PowerPCInstrInfo : InstrInfo {
798 let TSFlagsFields = [ "VMX", "PPC64" ];
799 let TSFlagsShifts = [ 0, 1 ];
801 let isLittleEndianEncoding = 1;