1 //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PowerPCInstrFormats.td"
17 let isTerminator = 1 in {
19 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, 0, 0, (ops), "blr">;
20 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, 0, 0, (ops), "bctr">;
23 def u5imm : Operand<i8> {
24 let PrintMethod = "printU5ImmOperand";
26 def u6imm : Operand<i8> {
27 let PrintMethod = "printU6ImmOperand";
29 def s16imm : Operand<i16> {
30 let PrintMethod = "printS16ImmOperand";
32 def u16imm : Operand<i16> {
33 let PrintMethod = "printU16ImmOperand";
35 def target : Operand<i32> {
36 let PrintMethod = "printBranchOperand";
38 def piclabel: Operand<i32> {
39 let PrintMethod = "printPICLabel";
41 def symbolHi: Operand<i32> {
42 let PrintMethod = "printSymbolHi";
44 def symbolLo: Operand<i32> {
45 let PrintMethod = "printSymbolLo";
48 // Pseudo-instructions:
49 def PHI : Pseudo<(ops), "; PHI">;
51 def ADJCALLSTACKDOWN : Pseudo<(ops), "; ADJCALLSTACKDOWN">;
52 def ADJCALLSTACKUP : Pseudo<(ops), "; ADJCALLSTACKUP">;
54 def IMPLICIT_DEF : Pseudo<(ops), "; IMPLICIT_DEF">;
57 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
59 let isBranch = 1, isTerminator = 1 in {
60 def COND_BRANCH : Pseudo<(ops), "; COND_BRANCH">;
61 def B : IForm<18, 0, 0, 0, 0, (ops target:$func), "b $func">;
62 //def BA : IForm<18, 1, 0, 0, 0, (ops target:$func), "ba $func">;
63 def BL : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">;
64 //def BLA : IForm<18, 1, 1, 0, 0, (ops target:$func), "bla $func">;
66 // FIXME: 4*CR# needs to be added to the BI field!
67 // This will only work for CR0 as it stands now
68 def BLT : BForm_ext<16, 0, 0, 12, 0, 0, 0, (ops CRRC:$crS, target:$block),
70 def BLE : BForm_ext<16, 0, 0, 4, 1, 0, 0, (ops CRRC:$crS, target:$block),
72 def BEQ : BForm_ext<16, 0, 0, 12, 2, 0, 0, (ops CRRC:$crS, target:$block),
74 def BGE : BForm_ext<16, 0, 0, 4, 0, 0, 0, (ops CRRC:$crS, target:$block),
76 def BGT : BForm_ext<16, 0, 0, 12, 1, 0, 0, (ops CRRC:$crS, target:$block),
78 def BNE : BForm_ext<16, 0, 0, 4, 2, 0, 0, (ops CRRC:$crS, target:$block),
82 let isBranch = 1, isTerminator = 1, isCall = 1,
83 // All calls clobber the non-callee saved registers...
84 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
85 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
87 CR0,CR1,CR5,CR6,CR7] in {
88 // Convenient aliases for call instructions
89 def CALLpcrel : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">;
90 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1, 0, 0, (ops), "bctrl">;
93 // D-Form instructions. Most instructions that perform an operation on a
94 // register and an immediate are of this type.
97 def LBZ : DForm_1<34, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
98 "lbz $rD, $disp($rA)">;
99 def LHA : DForm_1<42, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
100 "lha $rD, $disp($rA)">;
101 def LHZ : DForm_1<40, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
102 "lhz $rD, $disp($rA)">;
103 def LMW : DForm_1<46, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
104 "lmw $rD, $disp($rA)">;
105 def LWZ : DForm_1<32, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
106 "lwz $rD, $disp($rA)">;
107 def LWZU : DForm_1<35, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
108 "lwzu $rD, $disp($rA)">;
110 def ADDI : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
111 "addi $rD, $rA, $imm">;
112 def ADDIC : DForm_2<12, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
113 "addic $rD, $rA, $imm">;
114 def ADDICo : DForm_2<13, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
115 "addic. $rD, $rA, $imm">;
116 def ADDIS : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
117 "addis $rD, $rA, $imm">;
118 def LA : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
119 "la $rD, $sym($rA)">;
120 def LOADHiAddr : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, symbolHi:$sym),
121 "addis $rD, $rA, $sym">;
122 def MULLI : DForm_2< 7, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
123 "mulli $rD, $rA, $imm">;
124 def SUBFIC : DForm_2< 8, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
125 "subfic $rD, $rA, $imm">;
126 def LI : DForm_2_r0<14, 0, 0, (ops GPRC:$rD, s16imm:$imm),
128 def LIS : DForm_2_r0<15, 0, 0, (ops GPRC:$rD, s16imm:$imm),
131 def STMW : DForm_3<47, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
132 "stmw $rS, $disp($rA)">;
133 def STB : DForm_3<38, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
134 "stb $rS, $disp($rA)">;
135 def STH : DForm_3<44, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
136 "sth $rS, $disp($rA)">;
137 def STW : DForm_3<36, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
138 "stw $rS, $disp($rA)">;
139 def STWU : DForm_3<37, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
140 "stwu $rS, $disp($rA)">;
142 let Defs = [CR0] in {
143 def ANDIo : DForm_4<28, 0, 0,
144 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
145 "andi. $dst, $src1, $src2">;
146 def ANDISo : DForm_4<29, 0, 0,
147 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
148 "andis. $dst, $src1, $src2">;
150 def ORI : DForm_4<24, 0, 0,
151 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
152 "ori $dst, $src1, $src2">;
153 def ORIS : DForm_4<25, 0, 0,
154 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
155 "oris $dst, $src1, $src2">;
156 def XORI : DForm_4<26, 0, 0,
157 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
158 "xori $dst, $src1, $src2">;
159 def XORIS : DForm_4<27, 0, 0,
160 (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
161 "xoris $dst, $src1, $src2">;
162 def NOP : DForm_4_zero<24, 0, 0, (ops), "nop">;
163 def CMPI : DForm_5<11, 0, 0, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
164 "cmpi $crD, $L, $rA, $imm">;
165 def CMPWI : DForm_5_ext<11, 0, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
166 "cmpwi $crD, $rA, $imm">;
167 def CMPDI : DForm_5_ext<11, 1, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
168 "cmpdi $crD, $rA, $imm">;
169 def CMPLI : DForm_6<10, 0, 0,
170 (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
171 "cmpli $dst, $size, $src1, $src2">;
172 def CMPLWI : DForm_6_ext<10, 0, 0,
173 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
174 "cmplwi $dst, $src1, $src2">;
175 def CMPLDI : DForm_6_ext<10, 1, 0,
176 (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
177 "cmpldi $dst, $src1, $src2">;
179 def LFS : DForm_8<48, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
180 "lfs $rD, $disp($rA)">;
181 def LFD : DForm_8<50, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
182 "lfd $rD, $disp($rA)">;
185 def STFS : DForm_9<52, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
186 "stfs $rS, $disp($rA)">;
187 def STFD : DForm_9<54, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
188 "stfd $rS, $disp($rA)">;
191 // DS-Form instructions. Load/Store instructions available in PPC-64
194 def LWA : DSForm_1<58, 2, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
195 "lwa $rT, $DS($rA)">;
196 def LD : DSForm_2<58, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
200 def STD : DSForm_2<62, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
201 "std $rT, $DS($rA)">;
202 def STDU : DSForm_2<62, 1, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
203 "stdu $rT, $DS($rA)">;
206 // X-Form instructions. Most instructions that perform an operation on a
207 // register and another register are of this type.
210 def LBZX : XForm_1<31, 87, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
211 "lbzx $dst, $base, $index">;
212 def LHAX : XForm_1<31, 343, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
213 "lhax $dst, $base, $index">;
214 def LHZX : XForm_1<31, 279, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
215 "lhzx $dst, $base, $index">;
216 def LWAX : XForm_1<31, 341, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
217 "lwax $dst, $base, $index">;
218 def LWZX : XForm_1<31, 23, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
219 "lwzx $dst, $base, $index">;
220 def LDX : XForm_1<31, 21, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
221 "ldx $dst, $base, $index">;
223 def MFCR : XForm_5<31, 19, 0, 0, (ops GPRC:$dst), "mfcr $dst">;
224 def AND : XForm_6<31, 28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
225 "and $rA, $rS, $rB">;
227 def ANDo : XForm_6<31, 28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
228 "and. $rA, $rS, $rB">, DOT;
229 def ANDC : XForm_6<31, 60, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
230 "andc $rA, $rS, $rB">;
231 def EQV : XForm_6<31, 284, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
232 "eqv $rA, $rS, $rB">;
233 def NAND : XForm_6<31, 476, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
234 "nand $rA, $rS, $rB">;
235 def NOR : XForm_6<31, 124, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
236 "nor $rA, $rS, $rB">;
237 def OR : XForm_6<31, 444, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
239 def ORo : XForm_6<31, 444, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
240 "or. $rA, $rS, $rB">, DOT;
241 def ORC : XForm_6<31, 412, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
242 "orc $rA, $rS, $rB">;
243 def SLD : XForm_6<31, 27, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
244 "sld $rA, $rS, $rB">;
245 def SLW : XForm_6<31, 24, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
246 "slw $rA, $rS, $rB">;
247 def SRD : XForm_6<31, 539, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
248 "srd $rA, $rS, $rB">;
249 def SRW : XForm_6<31, 536, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
250 "srw $rA, $rS, $rB">;
251 def SRAD : XForm_6<31, 794, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
252 "srad $rA, $rS, $rB">;
253 def SRAW : XForm_6<31, 792, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
254 "sraw $rA, $rS, $rB">;
255 def XOR : XForm_6<31, 316, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
256 "xor $rA, $rS, $rB">;
258 def STBX : XForm_8<31, 215, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
259 "stbx $rS, $rA, $rB">;
260 def STHX : XForm_8<31, 407, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
261 "sthx $rS, $rA, $rB">;
262 def STWX : XForm_8<31, 151, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
263 "stwx $rS, $rA, $rB">;
264 def STWUX : XForm_8<31, 183, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
265 "stwux $rS, $rA, $rB">;
266 def STDX : XForm_8<31, 149, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
267 "stdx $rS, $rA, $rB">;
268 def STDUX : XForm_8<31, 181, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
269 "stdux $rS, $rA, $rB">;
271 def SRAWI : XForm_10<31, 824, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
272 "srawi $rA, $rS, $SH">;
273 def CNTLZW : XForm_11<31, 26, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
275 def EXTSB : XForm_11<31, 954, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
277 def EXTSH : XForm_11<31, 922, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
279 def EXTSW : XForm_11<31, 986, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS),
281 def CMP : XForm_16<31, 0, 0, 0,
282 (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
283 "cmp $crD, $long, $rA, $rB">;
284 def CMPL : XForm_16<31, 32, 0, 0,
285 (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
286 "cmpl $crD, $long, $rA, $rB">;
287 def CMPW : XForm_16_ext<31, 0, 0, 0,
288 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
289 "cmpw $crD, $rA, $rB">;
290 def CMPD : XForm_16_ext<31, 0, 1, 0,
291 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
292 "cmpd $crD, $rA, $rB">;
293 def CMPLW : XForm_16_ext<31, 32, 0, 0,
294 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
295 "cmplw $crD, $rA, $rB">;
296 def CMPLD : XForm_16_ext<31, 32, 1, 0,
297 (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
298 "cmpld $crD, $rA, $rB">;
299 def FCMPO : XForm_17<63, 32, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
300 "fcmpo $crD, $fA, $fB">;
301 def FCMPU : XForm_17<63, 0, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
302 "fcmpu $crD, $fA, $fB">;
304 def LFSX : XForm_25<31, 535, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
305 "lfsx $dst, $base, $index">;
306 def LFDX : XForm_25<31, 599, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
307 "lfdx $dst, $base, $index">;
309 def FCFID : XForm_26<63, 846, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
311 def FCTIDZ : XForm_26<63, 815, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
312 "fctidz $frD, $frB">;
313 def FCTIWZ : XForm_26<63, 15, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
314 "fctiwz $frD, $frB">;
315 def FABS : XForm_26<63, 264, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
317 def FMR : XForm_26<63, 72, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
319 def FNABS : XForm_26<63, 136, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
321 def FNEG : XForm_26<63, 40, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
323 def FRSP : XForm_26<63, 12, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
326 def STFSX : XForm_28<31, 663, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
327 "stfsx $frS, $rA, $rB">;
328 def STFDX : XForm_28<31, 727, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
329 "stfdx $frS, $rA, $rB">;
332 // XL-Form instructions. condition register logical ops.
334 def CRAND : XLForm_1<19, 257, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
336 def CRANDC : XLForm_1<19, 129, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
337 "crandc $D, $A, $B">;
338 def CRNOR : XLForm_1<19, 33, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
340 def CROR : XLForm_1<19, 449, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
343 // XFX-Form instructions. Instructions that deal with SPRs
345 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
346 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
347 // which means the SPR value needs to be multiplied by a factor of 32.
348 def MFCTR : XFXForm_1_ext<31, 339, 288, 0, 0, (ops GPRC:$rT), "mfctr $rT">;
349 def MFLR : XFXForm_1_ext<31, 339, 256, 0, 0, (ops GPRC:$rT), "mflr $rT">;
350 def MTCTR : XFXForm_7_ext<31, 467, 288, 0, 0, (ops GPRC:$rS), "mtctr $rS">;
351 def MTLR : XFXForm_7_ext<31, 467, 256, 0, 0, (ops GPRC:$rS), "mtlr $rS">;
354 // XS-Form instructions. Just 'sradi'
356 def SRADI : XSForm_1<31, 413, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
357 "sradi $rA, $rS, $SH">;
359 // XO-Form instructions. Arithmetic instructions that can set overflow bit
361 def ADD : XOForm_1<31, 266, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
362 "add $rT, $rA, $rB">;
363 def ADDC : XOForm_1<31, 10, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
364 "addc $rT, $rA, $rB">;
365 def ADDE : XOForm_1<31, 138, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
366 "adde $rT, $rA, $rB">;
367 def DIVD : XOForm_1<31, 489, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
368 "divd $rT, $rA, $rB">;
369 def DIVDU : XOForm_1<31, 457, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
370 "divdu $rT, $rA, $rB">;
371 def DIVW : XOForm_1<31, 491, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
372 "divw $rT, $rA, $rB">;
373 def DIVWU : XOForm_1<31, 459, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
374 "divwu $rT, $rA, $rB">;
375 def MULHW : XOForm_1<31, 75, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
376 "mulhw $rT, $rA, $rB">;
377 def MULHWU : XOForm_1<31, 11, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
378 "mulhwu $rT, $rA, $rB">;
379 def MULLD : XOForm_1<31, 233, 0, 0, 1, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
380 "mulld $rT, $rA, $rB">;
381 def MULLW : XOForm_1<31, 235, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
382 "mullw $rT, $rA, $rB">;
383 def SUBF : XOForm_1<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
384 "subf $rT, $rA, $rB">;
385 def SUBFC : XOForm_1<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
386 "subfc $rT, $rA, $rB">;
387 def SUBFE : XOForm_1<31, 136, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
388 "subfe $rT, $rA, $rB">;
389 def SUB : XOForm_1r<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
390 "sub $rT, $rA, $rB">;
391 def ADDME : XOForm_3<31, 234, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
393 def ADDZE : XOForm_3<31, 202, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
395 def NEG : XOForm_3<31, 104, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
397 def SUBFZE : XOForm_3<31, 200, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
400 // A-Form instructions. Most of the instructions executed in the FPU are of
403 def FMADD : AForm_1<63, 29, 0, 0, 0,
404 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
405 "fmadd $FRT, $FRA, $FRC, $FRB">;
406 def FMADDS : AForm_1<59, 29, 0, 0, 0,
407 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
408 "fmadds $FRT, $FRA, $FRC, $FRB">;
409 def FMSUB : AForm_1<63, 28, 0, 0, 0,
410 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
411 "fmsub $FRT, $FRA, $FRC, $FRB">;
412 def FMSUBS : AForm_1<59, 28, 0, 0, 0,
413 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
414 "fmsubs $FRT, $FRA, $FRC, $FRB">;
415 def FNMADD : AForm_1<63, 31, 0, 0, 0,
416 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
417 "fnmadd $FRT, $FRA, $FRC, $FRB">;
418 def FNMADDS : AForm_1<59, 31, 0, 0, 0,
419 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
420 "fnmadds $FRT, $FRA, $FRC, $FRB">;
421 def FNMSUB : AForm_1<63, 30, 0, 0, 0,
422 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
423 "fnmsub $FRT, $FRA, $FRC, $FRB">;
424 def FNMSUBS : AForm_1<59, 30, 0, 0, 0,
425 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
426 "fnmsubs $FRT, $FRA, $FRC, $FRB">;
427 def FSEL : AForm_1<63, 23, 0, 0, 0,
428 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
429 "fsel $FRT, $FRA, $FRC, $FRB">;
430 def FADD : AForm_2<63, 21, 0, 0, 0,
431 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
432 "fadd $FRT, $FRA, $FRB">;
433 def FADDS : AForm_2<59, 21, 0, 0, 0,
434 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
435 "fadds $FRT, $FRA, $FRB">;
436 def FDIV : AForm_2<63, 18, 0, 0, 0,
437 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
438 "fdiv $FRT, $FRA, $FRB">;
439 def FDIVS : AForm_2<59, 18, 0, 0, 0,
440 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
441 "fdivs $FRT, $FRA, $FRB">;
442 def FMUL : AForm_3<63, 25, 0, 0, 0,
443 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
444 "fmul $FRT, $FRA, $FRB">;
445 def FMULS : AForm_3<59, 25, 0, 0, 0,
446 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
447 "fmuls $FRT, $FRA, $FRB">;
448 def FSUB : AForm_2<63, 20, 0, 0, 0,
449 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
450 "fsub $FRT, $FRA, $FRB">;
451 def FSUBS : AForm_2<59, 20, 0, 0, 0,
452 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
453 "fsubs $FRT, $FRA, $FRB">;
455 // M-Form instructions. rotate and mask instructions.
457 let isTwoAddress = 1 in {
458 def RLWIMI : MForm_2<20, 0, 0, 0,
459 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
460 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
462 def RLWINM : MForm_2<21, 0, 0, 0,
463 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
464 "rlwinm $rA, $rS, $SH, $MB, $ME">;
465 def RLWNM : MForm_2<23, 0, 0, 0,
466 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
467 "rlwnm $rA, $rS, $rB, $MB, $ME">;
469 // MD-Form instructions. 64 bit rotate instructions.
471 def RLDICL : MDForm_1<30, 0, 0, 1, 0,
472 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
473 "rldicl $rA, $rS, $SH, $MB">;
474 def RLDICR : MDForm_1<30, 1, 0, 1, 0,
475 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
476 "rldicr $rA, $rS, $SH, $ME">;
478 def PowerPCInstrInfo : InstrInfo {
481 let TSFlagsFields = [ "VMX", "PPC64" ];
482 let TSFlagsShifts = [ 0, 1 ];
484 let isLittleEndianEncoding = 1;