1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
61 //===----------------------------------------------------------------------===//
62 // PowerPC specific DAG Nodes.
65 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
66 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
68 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
69 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
70 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
71 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
72 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
73 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
74 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
75 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
76 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
77 [SDNPHasChain, SDNPMayStore]>;
78 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
79 [SDNPHasChain, SDNPMayLoad]>;
80 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
81 [SDNPHasChain, SDNPMayLoad]>;
83 // Extract FPSCR (not modeled at the DAG level).
84 def PPCmffs : SDNode<"PPCISD::MFFS",
85 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
87 // Perform FADD in round-to-zero mode.
88 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
91 def PPCfsel : SDNode<"PPCISD::FSEL",
92 // Type constraint for fsel.
93 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
94 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
96 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
97 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
98 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
99 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
100 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
102 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
103 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
105 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
106 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
107 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
108 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
109 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
110 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
111 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
112 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
114 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
116 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
118 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
119 // amounts. These nodes are generated by the multi-precision shift code.
120 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
121 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
122 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
124 // These are target-independent nodes, but have target-specific formats.
125 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
126 [SDNPHasChain, SDNPOutGlue]>;
127 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
128 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
130 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
131 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
132 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
134 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
135 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
137 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
139 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
140 [SDNPHasChain, SDNPSideEffect,
141 SDNPInGlue, SDNPOutGlue]>;
142 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
143 [SDNPHasChain, SDNPSideEffect,
144 SDNPInGlue, SDNPOutGlue]>;
145 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
147 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
151 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
152 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
154 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
157 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
158 SDTypeProfile<1, 1, [SDTCisInt<0>,
160 [SDNPHasChain, SDNPSideEffect]>;
161 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
162 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
163 [SDNPHasChain, SDNPSideEffect]>;
165 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
166 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
167 [SDNPHasChain, SDNPSideEffect]>;
169 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
170 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
172 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
173 [SDNPHasChain, SDNPOptInGlue]>;
175 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
176 [SDNPHasChain, SDNPMayLoad]>;
177 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
178 [SDNPHasChain, SDNPMayStore]>;
180 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
181 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
182 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
183 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
184 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
186 // Instructions to support atomic operations
187 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
188 [SDNPHasChain, SDNPMayLoad]>;
189 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
190 [SDNPHasChain, SDNPMayStore]>;
192 // Instructions to support medium and large code model
193 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
194 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
195 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
198 // Instructions to support dynamic alloca.
199 def SDTDynOp : SDTypeProfile<1, 2, []>;
200 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
202 //===----------------------------------------------------------------------===//
203 // PowerPC specific transformation functions and pattern fragments.
206 def SHL32 : SDNodeXForm<imm, [{
207 // Transformation function: 31 - imm
208 return getI32Imm(31 - N->getZExtValue());
211 def SRL32 : SDNodeXForm<imm, [{
212 // Transformation function: 32 - imm
213 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
216 def LO16 : SDNodeXForm<imm, [{
217 // Transformation function: get the low 16 bits.
218 return getI32Imm((unsigned short)N->getZExtValue());
221 def HI16 : SDNodeXForm<imm, [{
222 // Transformation function: shift the immediate value down into the low bits.
223 return getI32Imm((unsigned)N->getZExtValue() >> 16);
226 def HA16 : SDNodeXForm<imm, [{
227 // Transformation function: shift the immediate value down into the low bits.
228 signed int Val = N->getZExtValue();
229 return getI32Imm((Val - (signed short)Val) >> 16);
231 def MB : SDNodeXForm<imm, [{
232 // Transformation function: get the start bit of a mask
234 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
235 return getI32Imm(mb);
238 def ME : SDNodeXForm<imm, [{
239 // Transformation function: get the end bit of a mask
241 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
242 return getI32Imm(me);
244 def maskimm32 : PatLeaf<(imm), [{
245 // maskImm predicate - True if immediate is a run of ones.
247 if (N->getValueType(0) == MVT::i32)
248 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
253 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
254 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
255 // sign extended field. Used by instructions like 'addi'.
256 return (int32_t)Imm == (short)Imm;
258 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
259 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
260 // sign extended field. Used by instructions like 'addi'.
261 return (int64_t)Imm == (short)Imm;
263 def immZExt16 : PatLeaf<(imm), [{
264 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
265 // field. Used by instructions like 'ori'.
266 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
269 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
270 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
271 // identical in 32-bit mode, but in 64-bit mode, they return true if the
272 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
274 def imm16ShiftedZExt : PatLeaf<(imm), [{
275 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
276 // immediate are set. Used by instructions like 'xoris'.
277 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
280 def imm16ShiftedSExt : PatLeaf<(imm), [{
281 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
282 // immediate are set. Used by instructions like 'addis'. Identical to
283 // imm16ShiftedZExt in 32-bit mode.
284 if (N->getZExtValue() & 0xFFFF) return false;
285 if (N->getValueType(0) == MVT::i32)
287 // For 64-bit, make sure it is sext right.
288 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
291 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
292 // restricted memrix (4-aligned) constants are alignment sensitive. If these
293 // offsets are hidden behind TOC entries than the values of the lower-order
294 // bits cannot be checked directly. As a result, we need to also incorporate
295 // an alignment check into the relevant patterns.
297 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
298 return cast<LoadSDNode>(N)->getAlignment() >= 4;
300 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
301 (store node:$val, node:$ptr), [{
302 return cast<StoreSDNode>(N)->getAlignment() >= 4;
304 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
305 return cast<LoadSDNode>(N)->getAlignment() >= 4;
307 def aligned4pre_store : PatFrag<
308 (ops node:$val, node:$base, node:$offset),
309 (pre_store node:$val, node:$base, node:$offset), [{
310 return cast<StoreSDNode>(N)->getAlignment() >= 4;
313 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
314 return cast<LoadSDNode>(N)->getAlignment() < 4;
316 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
317 (store node:$val, node:$ptr), [{
318 return cast<StoreSDNode>(N)->getAlignment() < 4;
320 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
321 return cast<LoadSDNode>(N)->getAlignment() < 4;
324 //===----------------------------------------------------------------------===//
325 // PowerPC Flag Definitions.
327 class isPPC64 { bit PPC64 = 1; }
328 class isDOT { bit RC = 1; }
330 class RegConstraint<string C> {
331 string Constraints = C;
333 class NoEncode<string E> {
334 string DisableEncoding = E;
338 //===----------------------------------------------------------------------===//
339 // PowerPC Operand Definitions.
341 // In the default PowerPC assembler syntax, registers are specified simply
342 // by number, so they cannot be distinguished from immediate values (without
343 // looking at the opcode). This means that the default operand matching logic
344 // for the asm parser does not work, and we need to specify custom matchers.
345 // Since those can only be specified with RegisterOperand classes and not
346 // directly on the RegisterClass, all instructions patterns used by the asm
347 // parser need to use a RegisterOperand (instead of a RegisterClass) for
348 // all their register operands.
349 // For this purpose, we define one RegisterOperand for each RegisterClass,
350 // using the same name as the class, just in lower case.
352 def PPCRegGPRCAsmOperand : AsmOperandClass {
353 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
355 def gprc : RegisterOperand<GPRC> {
356 let ParserMatchClass = PPCRegGPRCAsmOperand;
358 def PPCRegG8RCAsmOperand : AsmOperandClass {
359 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
361 def g8rc : RegisterOperand<G8RC> {
362 let ParserMatchClass = PPCRegG8RCAsmOperand;
364 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
365 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
367 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
368 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
370 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
371 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
373 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
374 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
376 def PPCRegF8RCAsmOperand : AsmOperandClass {
377 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
379 def f8rc : RegisterOperand<F8RC> {
380 let ParserMatchClass = PPCRegF8RCAsmOperand;
382 def PPCRegF4RCAsmOperand : AsmOperandClass {
383 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
385 def f4rc : RegisterOperand<F4RC> {
386 let ParserMatchClass = PPCRegF4RCAsmOperand;
388 def PPCRegVRRCAsmOperand : AsmOperandClass {
389 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
391 def vrrc : RegisterOperand<VRRC> {
392 let ParserMatchClass = PPCRegVRRCAsmOperand;
394 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
395 let Name = "RegCRBITRC"; let PredicateMethod = "isRegNumber";
397 def crbitrc : RegisterOperand<CRBITRC> {
398 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
400 def PPCRegCRRCAsmOperand : AsmOperandClass {
401 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
403 def crrc : RegisterOperand<CRRC> {
404 let ParserMatchClass = PPCRegCRRCAsmOperand;
407 def PPCS5ImmAsmOperand : AsmOperandClass {
408 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
409 let RenderMethod = "addImmOperands";
411 def s5imm : Operand<i32> {
412 let PrintMethod = "printS5ImmOperand";
413 let ParserMatchClass = PPCS5ImmAsmOperand;
415 def PPCU5ImmAsmOperand : AsmOperandClass {
416 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
417 let RenderMethod = "addImmOperands";
419 def u5imm : Operand<i32> {
420 let PrintMethod = "printU5ImmOperand";
421 let ParserMatchClass = PPCU5ImmAsmOperand;
423 def PPCU6ImmAsmOperand : AsmOperandClass {
424 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
425 let RenderMethod = "addImmOperands";
427 def u6imm : Operand<i32> {
428 let PrintMethod = "printU6ImmOperand";
429 let ParserMatchClass = PPCU6ImmAsmOperand;
431 def PPCS16ImmAsmOperand : AsmOperandClass {
432 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
433 let RenderMethod = "addImmOperands";
435 def s16imm : Operand<i32> {
436 let PrintMethod = "printS16ImmOperand";
437 let EncoderMethod = "getS16ImmEncoding";
438 let ParserMatchClass = PPCS16ImmAsmOperand;
440 def PPCU16ImmAsmOperand : AsmOperandClass {
441 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
442 let RenderMethod = "addImmOperands";
444 def u16imm : Operand<i32> {
445 let PrintMethod = "printU16ImmOperand";
446 let ParserMatchClass = PPCU16ImmAsmOperand;
448 def PPCDirectBrAsmOperand : AsmOperandClass {
449 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
450 let RenderMethod = "addBranchTargetOperands";
452 def directbrtarget : Operand<OtherVT> {
453 let PrintMethod = "printBranchOperand";
454 let EncoderMethod = "getDirectBrEncoding";
455 let ParserMatchClass = PPCDirectBrAsmOperand;
457 def absdirectbrtarget : Operand<OtherVT> {
458 let PrintMethod = "printAbsBranchOperand";
459 let EncoderMethod = "getAbsDirectBrEncoding";
460 let ParserMatchClass = PPCDirectBrAsmOperand;
462 def PPCCondBrAsmOperand : AsmOperandClass {
463 let Name = "CondBr"; let PredicateMethod = "isCondBr";
464 let RenderMethod = "addBranchTargetOperands";
466 def condbrtarget : Operand<OtherVT> {
467 let PrintMethod = "printBranchOperand";
468 let EncoderMethod = "getCondBrEncoding";
469 let ParserMatchClass = PPCCondBrAsmOperand;
471 def abscondbrtarget : Operand<OtherVT> {
472 let PrintMethod = "printAbsBranchOperand";
473 let EncoderMethod = "getAbsCondBrEncoding";
474 let ParserMatchClass = PPCCondBrAsmOperand;
476 def calltarget : Operand<iPTR> {
477 let PrintMethod = "printBranchOperand";
478 let EncoderMethod = "getDirectBrEncoding";
479 let ParserMatchClass = PPCDirectBrAsmOperand;
481 def abscalltarget : Operand<iPTR> {
482 let PrintMethod = "printAbsBranchOperand";
483 let EncoderMethod = "getAbsDirectBrEncoding";
484 let ParserMatchClass = PPCDirectBrAsmOperand;
486 def PPCCRBitMaskOperand : AsmOperandClass {
487 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
489 def crbitm: Operand<i8> {
490 let PrintMethod = "printcrbitm";
491 let EncoderMethod = "get_crbitm_encoding";
492 let ParserMatchClass = PPCCRBitMaskOperand;
495 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
496 def PPCRegGxRCNoR0Operand : AsmOperandClass {
497 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
499 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
500 let ParserMatchClass = PPCRegGxRCNoR0Operand;
502 // A version of ptr_rc usable with the asm parser.
503 def PPCRegGxRCOperand : AsmOperandClass {
504 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
506 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
507 let ParserMatchClass = PPCRegGxRCOperand;
510 def PPCDispRIOperand : AsmOperandClass {
511 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
512 let RenderMethod = "addImmOperands";
514 def dispRI : Operand<iPTR> {
515 let ParserMatchClass = PPCDispRIOperand;
517 def PPCDispRIXOperand : AsmOperandClass {
518 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
519 let RenderMethod = "addImmOperands";
521 def dispRIX : Operand<iPTR> {
522 let ParserMatchClass = PPCDispRIXOperand;
525 def memri : Operand<iPTR> {
526 let PrintMethod = "printMemRegImm";
527 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
528 let EncoderMethod = "getMemRIEncoding";
530 def memrr : Operand<iPTR> {
531 let PrintMethod = "printMemRegReg";
532 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
534 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
535 let PrintMethod = "printMemRegImm";
536 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
537 let EncoderMethod = "getMemRIXEncoding";
540 // A single-register address. This is used with the SjLj
541 // pseudo-instructions.
542 def memr : Operand<iPTR> {
543 let MIOperandInfo = (ops ptr_rc:$ptrreg);
546 // PowerPC Predicate operand.
547 def pred : Operand<OtherVT> {
548 let PrintMethod = "printPredicateOperand";
549 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
552 // Define PowerPC specific addressing mode.
553 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
554 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
555 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
556 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
558 // The address in a single register. This is used with the SjLj
559 // pseudo-instructions.
560 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
562 /// This is just the offset part of iaddr, used for preinc.
563 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
565 //===----------------------------------------------------------------------===//
566 // PowerPC Instruction Predicate Definitions.
567 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
568 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
569 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
571 //===----------------------------------------------------------------------===//
572 // PowerPC Multiclass Definitions.
574 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
575 string asmbase, string asmstr, InstrItinClass itin,
577 let BaseName = asmbase in {
578 def NAME : XForm_6<opcode, xo, OOL, IOL,
579 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
580 pattern>, RecFormRel;
582 def o : XForm_6<opcode, xo, OOL, IOL,
583 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
584 []>, isDOT, RecFormRel;
588 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
589 string asmbase, string asmstr, InstrItinClass itin,
591 let BaseName = asmbase in {
592 let Defs = [CARRY] in
593 def NAME : XForm_6<opcode, xo, OOL, IOL,
594 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
595 pattern>, RecFormRel;
596 let Defs = [CARRY, CR0] in
597 def o : XForm_6<opcode, xo, OOL, IOL,
598 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
599 []>, isDOT, RecFormRel;
603 multiclass XForm_10r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
604 string asmbase, string asmstr, InstrItinClass itin,
606 let BaseName = asmbase in {
607 def NAME : XForm_10<opcode, xo, OOL, IOL,
608 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
609 pattern>, RecFormRel;
611 def o : XForm_10<opcode, xo, OOL, IOL,
612 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
613 []>, isDOT, RecFormRel;
617 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
618 string asmbase, string asmstr, InstrItinClass itin,
620 let BaseName = asmbase in {
621 let Defs = [CARRY] in
622 def NAME : XForm_10<opcode, xo, OOL, IOL,
623 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
624 pattern>, RecFormRel;
625 let Defs = [CARRY, CR0] in
626 def o : XForm_10<opcode, xo, OOL, IOL,
627 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
628 []>, isDOT, RecFormRel;
632 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
633 string asmbase, string asmstr, InstrItinClass itin,
635 let BaseName = asmbase in {
636 def NAME : XForm_11<opcode, xo, OOL, IOL,
637 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
638 pattern>, RecFormRel;
640 def o : XForm_11<opcode, xo, OOL, IOL,
641 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
642 []>, isDOT, RecFormRel;
646 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
647 string asmbase, string asmstr, InstrItinClass itin,
649 let BaseName = asmbase in {
650 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
651 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
652 pattern>, RecFormRel;
654 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
655 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
656 []>, isDOT, RecFormRel;
660 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
661 string asmbase, string asmstr, InstrItinClass itin,
663 let BaseName = asmbase in {
664 let Defs = [CARRY] in
665 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
666 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
667 pattern>, RecFormRel;
668 let Defs = [CARRY, CR0] in
669 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
670 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
671 []>, isDOT, RecFormRel;
675 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
676 string asmbase, string asmstr, InstrItinClass itin,
678 let BaseName = asmbase in {
679 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
680 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
681 pattern>, RecFormRel;
683 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
684 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
685 []>, isDOT, RecFormRel;
689 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
690 string asmbase, string asmstr, InstrItinClass itin,
692 let BaseName = asmbase in {
693 let Defs = [CARRY] in
694 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
695 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
696 pattern>, RecFormRel;
697 let Defs = [CARRY, CR0] in
698 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
699 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
700 []>, isDOT, RecFormRel;
704 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
705 string asmbase, string asmstr, InstrItinClass itin,
707 let BaseName = asmbase in {
708 def NAME : MForm_2<opcode, OOL, IOL,
709 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
710 pattern>, RecFormRel;
712 def o : MForm_2<opcode, OOL, IOL,
713 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
714 []>, isDOT, RecFormRel;
718 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
719 string asmbase, string asmstr, InstrItinClass itin,
721 let BaseName = asmbase in {
722 def NAME : MDForm_1<opcode, xo, OOL, IOL,
723 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
724 pattern>, RecFormRel;
726 def o : MDForm_1<opcode, xo, OOL, IOL,
727 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
728 []>, isDOT, RecFormRel;
732 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
733 string asmbase, string asmstr, InstrItinClass itin,
735 let BaseName = asmbase in {
736 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
737 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
738 pattern>, RecFormRel;
740 def o : MDSForm_1<opcode, xo, OOL, IOL,
741 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
742 []>, isDOT, RecFormRel;
746 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
747 string asmbase, string asmstr, InstrItinClass itin,
749 let BaseName = asmbase in {
750 let Defs = [CARRY] in
751 def NAME : XSForm_1<opcode, xo, OOL, IOL,
752 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
753 pattern>, RecFormRel;
754 let Defs = [CARRY, CR0] in
755 def o : XSForm_1<opcode, xo, OOL, IOL,
756 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
757 []>, isDOT, RecFormRel;
761 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
762 string asmbase, string asmstr, InstrItinClass itin,
764 let BaseName = asmbase in {
765 def NAME : XForm_26<opcode, xo, OOL, IOL,
766 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
767 pattern>, RecFormRel;
769 def o : XForm_26<opcode, xo, OOL, IOL,
770 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
771 []>, isDOT, RecFormRel;
775 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
776 string asmbase, string asmstr, InstrItinClass itin,
778 let BaseName = asmbase in {
779 def NAME : AForm_1<opcode, xo, OOL, IOL,
780 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
781 pattern>, RecFormRel;
783 def o : AForm_1<opcode, xo, OOL, IOL,
784 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
785 []>, isDOT, RecFormRel;
789 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
790 string asmbase, string asmstr, InstrItinClass itin,
792 let BaseName = asmbase in {
793 def NAME : AForm_2<opcode, xo, OOL, IOL,
794 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
795 pattern>, RecFormRel;
797 def o : AForm_2<opcode, xo, OOL, IOL,
798 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
799 []>, isDOT, RecFormRel;
803 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
804 string asmbase, string asmstr, InstrItinClass itin,
806 let BaseName = asmbase in {
807 def NAME : AForm_3<opcode, xo, OOL, IOL,
808 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
809 pattern>, RecFormRel;
811 def o : AForm_3<opcode, xo, OOL, IOL,
812 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
813 []>, isDOT, RecFormRel;
817 //===----------------------------------------------------------------------===//
818 // PowerPC Instruction Definitions.
820 // Pseudo-instructions:
822 let hasCtrlDep = 1 in {
823 let Defs = [R1], Uses = [R1] in {
824 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
825 [(callseq_start timm:$amt)]>;
826 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
827 [(callseq_end timm:$amt1, timm:$amt2)]>;
830 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
831 "UPDATE_VRSAVE $rD, $rS", []>;
834 let Defs = [R1], Uses = [R1] in
835 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
837 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
839 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
840 // instruction selection into a branch sequence.
841 let usesCustomInserter = 1, // Expanded after instruction selection.
842 PPC970_Single = 1 in {
843 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
844 // because either operand might become the first operand in an isel, and
845 // that operand cannot be r0.
846 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
847 gprc_nor0:$T, gprc_nor0:$F,
848 i32imm:$BROPC), "#SELECT_CC_I4",
850 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
851 g8rc_nox0:$T, g8rc_nox0:$F,
852 i32imm:$BROPC), "#SELECT_CC_I8",
854 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
855 i32imm:$BROPC), "#SELECT_CC_F4",
857 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
858 i32imm:$BROPC), "#SELECT_CC_F8",
860 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
861 i32imm:$BROPC), "#SELECT_CC_VRRC",
865 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
866 // scavenge a register for it.
868 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
871 // RESTORE_CR - Indicate that we're restoring the CR register (previously
872 // spilled), so we'll need to scavenge a register for it.
874 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
877 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
878 let isReturn = 1, Uses = [LR, RM] in
879 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", BrB,
881 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
882 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
884 let isCodeGenOnly = 1 in
885 def BCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
886 "b${cond:cc}ctr${cond:pm} ${cond:reg}", BrB, []>;
891 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
894 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
895 let isBarrier = 1 in {
896 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
899 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
903 // BCC represents an arbitrary conditional branch on a predicate.
904 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
905 // a two-value operand where a dag node expects two operands. :(
906 let isCodeGenOnly = 1 in {
907 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
908 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
909 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
910 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
911 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
913 let isReturn = 1, Uses = [LR, RM] in
914 def BCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
915 "b${cond:cc}lr${cond:pm} ${cond:reg}", BrB, []>;
918 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
919 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
921 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
923 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
925 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
927 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
929 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
933 let Defs = [CTR], Uses = [CTR] in {
934 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
936 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
938 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
940 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
942 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
944 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
946 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
948 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
950 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
952 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
954 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
956 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
961 // The unconditional BCL used by the SjLj setjmp code.
962 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
963 let Defs = [LR], Uses = [RM] in {
964 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
969 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
970 // Convenient aliases for call instructions
972 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
973 "bl $func", BrB, []>; // See Pat patterns below.
974 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
975 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>;
977 let isCodeGenOnly = 1 in {
978 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
979 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
980 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
981 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
984 let Uses = [CTR, RM] in {
985 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
986 "bctrl", BrB, [(PPCbctrl)]>,
987 Requires<[In32BitMode]>;
989 let isCodeGenOnly = 1 in
990 def BCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
991 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", BrB, []>;
993 let Uses = [LR, RM] in {
994 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
997 let isCodeGenOnly = 1 in
998 def BCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
999 "b${cond:cc}lrl${cond:pm} ${cond:reg}", BrB, []>;
1001 let Defs = [CTR], Uses = [CTR, RM] in {
1002 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1004 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1006 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1008 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1010 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1012 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1014 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1016 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1018 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1020 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1022 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1024 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1027 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1028 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1030 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1031 "bdnzlrl", BrB, []>;
1032 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1033 "bdzlrl+", BrB, []>;
1034 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1035 "bdnzlrl+", BrB, []>;
1036 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1037 "bdzlrl-", BrB, []>;
1038 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1039 "bdnzlrl-", BrB, []>;
1043 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1044 def TCRETURNdi :Pseudo< (outs),
1045 (ins calltarget:$dst, i32imm:$offset),
1046 "#TC_RETURNd $dst $offset",
1050 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1051 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1052 "#TC_RETURNa $func $offset",
1053 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1055 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1056 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1057 "#TC_RETURNr $dst $offset",
1061 let isCodeGenOnly = 1 in {
1063 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1064 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1065 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
1066 Requires<[In32BitMode]>;
1068 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1069 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1070 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1074 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1075 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1076 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1082 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1083 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1084 "#EH_SJLJ_SETJMP32",
1085 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1086 Requires<[In32BitMode]>;
1087 let isTerminator = 1 in
1088 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1089 "#EH_SJLJ_LONGJMP32",
1090 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1091 Requires<[In32BitMode]>;
1094 let isBranch = 1, isTerminator = 1 in {
1095 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1096 "#EH_SjLj_Setup\t$dst", []>;
1100 let PPC970_Unit = 7 in {
1101 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1102 "sc $lev", BrB, [(PPCsc (i32 imm:$lev))]>;
1105 // DCB* instructions.
1106 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
1107 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1108 PPC970_DGroup_Single;
1109 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
1110 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1111 PPC970_DGroup_Single;
1112 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
1113 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1114 PPC970_DGroup_Single;
1115 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
1116 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1117 PPC970_DGroup_Single;
1118 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
1119 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1120 PPC970_DGroup_Single;
1121 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
1122 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1123 PPC970_DGroup_Single;
1124 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
1125 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1126 PPC970_DGroup_Single;
1127 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
1128 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1129 PPC970_DGroup_Single;
1131 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1132 (DCBT xoaddr:$dst)>;
1134 // Atomic operations
1135 let usesCustomInserter = 1 in {
1136 let Defs = [CR0] in {
1137 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1138 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1139 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1140 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1141 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1142 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1143 def ATOMIC_LOAD_AND_I8 : Pseudo<
1144 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1145 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1146 def ATOMIC_LOAD_OR_I8 : Pseudo<
1147 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1148 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1149 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1150 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1151 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1152 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1153 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1154 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1155 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1156 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1157 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1158 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1159 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1160 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1161 def ATOMIC_LOAD_AND_I16 : Pseudo<
1162 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1163 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1164 def ATOMIC_LOAD_OR_I16 : Pseudo<
1165 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1166 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1167 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1168 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1169 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1170 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1171 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1172 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1173 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1174 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1175 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1176 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1177 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1178 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1179 def ATOMIC_LOAD_AND_I32 : Pseudo<
1180 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1181 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1182 def ATOMIC_LOAD_OR_I32 : Pseudo<
1183 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1184 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1185 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1186 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1187 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1188 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1189 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1190 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1192 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1193 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1194 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1195 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1196 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1197 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1198 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1199 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1200 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1202 def ATOMIC_SWAP_I8 : Pseudo<
1203 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1204 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1205 def ATOMIC_SWAP_I16 : Pseudo<
1206 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1207 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1208 def ATOMIC_SWAP_I32 : Pseudo<
1209 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1210 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1214 // Instructions to support atomic operations
1215 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1216 "lwarx $rD, $src", LdStLWARX,
1217 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1220 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1221 "stwcx. $rS, $dst", LdStSTWCX,
1222 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1225 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1226 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>;
1228 //===----------------------------------------------------------------------===//
1229 // PPC32 Load Instructions.
1232 // Unindexed (r+i) Loads.
1233 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1234 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1235 "lbz $rD, $src", LdStLoad,
1236 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1237 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1238 "lha $rD, $src", LdStLHA,
1239 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1240 PPC970_DGroup_Cracked;
1241 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1242 "lhz $rD, $src", LdStLoad,
1243 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1244 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1245 "lwz $rD, $src", LdStLoad,
1246 [(set i32:$rD, (load iaddr:$src))]>;
1248 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1249 "lfs $rD, $src", LdStLFD,
1250 [(set f32:$rD, (load iaddr:$src))]>;
1251 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1252 "lfd $rD, $src", LdStLFD,
1253 [(set f64:$rD, (load iaddr:$src))]>;
1256 // Unindexed (r+i) Loads with Update (preinc).
1257 let mayLoad = 1, neverHasSideEffects = 1 in {
1258 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1259 "lbzu $rD, $addr", LdStLoadUpd,
1260 []>, RegConstraint<"$addr.reg = $ea_result">,
1261 NoEncode<"$ea_result">;
1263 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1264 "lhau $rD, $addr", LdStLHAU,
1265 []>, RegConstraint<"$addr.reg = $ea_result">,
1266 NoEncode<"$ea_result">;
1268 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1269 "lhzu $rD, $addr", LdStLoadUpd,
1270 []>, RegConstraint<"$addr.reg = $ea_result">,
1271 NoEncode<"$ea_result">;
1273 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1274 "lwzu $rD, $addr", LdStLoadUpd,
1275 []>, RegConstraint<"$addr.reg = $ea_result">,
1276 NoEncode<"$ea_result">;
1278 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1279 "lfsu $rD, $addr", LdStLFDU,
1280 []>, RegConstraint<"$addr.reg = $ea_result">,
1281 NoEncode<"$ea_result">;
1283 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1284 "lfdu $rD, $addr", LdStLFDU,
1285 []>, RegConstraint<"$addr.reg = $ea_result">,
1286 NoEncode<"$ea_result">;
1289 // Indexed (r+r) Loads with Update (preinc).
1290 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1292 "lbzux $rD, $addr", LdStLoadUpd,
1293 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1294 NoEncode<"$ea_result">;
1296 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1298 "lhaux $rD, $addr", LdStLHAU,
1299 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1300 NoEncode<"$ea_result">;
1302 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1304 "lhzux $rD, $addr", LdStLoadUpd,
1305 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1306 NoEncode<"$ea_result">;
1308 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1310 "lwzux $rD, $addr", LdStLoadUpd,
1311 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1312 NoEncode<"$ea_result">;
1314 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1316 "lfsux $rD, $addr", LdStLFDU,
1317 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1318 NoEncode<"$ea_result">;
1320 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1322 "lfdux $rD, $addr", LdStLFDU,
1323 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1324 NoEncode<"$ea_result">;
1328 // Indexed (r+r) Loads.
1330 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1331 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1332 "lbzx $rD, $src", LdStLoad,
1333 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1334 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1335 "lhax $rD, $src", LdStLHA,
1336 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1337 PPC970_DGroup_Cracked;
1338 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1339 "lhzx $rD, $src", LdStLoad,
1340 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1341 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1342 "lwzx $rD, $src", LdStLoad,
1343 [(set i32:$rD, (load xaddr:$src))]>;
1346 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1347 "lhbrx $rD, $src", LdStLoad,
1348 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1349 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1350 "lwbrx $rD, $src", LdStLoad,
1351 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1353 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1354 "lfsx $frD, $src", LdStLFD,
1355 [(set f32:$frD, (load xaddr:$src))]>;
1356 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1357 "lfdx $frD, $src", LdStLFD,
1358 [(set f64:$frD, (load xaddr:$src))]>;
1360 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1361 "lfiwax $frD, $src", LdStLFD,
1362 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1363 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1364 "lfiwzx $frD, $src", LdStLFD,
1365 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1368 //===----------------------------------------------------------------------===//
1369 // PPC32 Store Instructions.
1372 // Unindexed (r+i) Stores.
1373 let PPC970_Unit = 2 in {
1374 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1375 "stb $rS, $src", LdStStore,
1376 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1377 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1378 "sth $rS, $src", LdStStore,
1379 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1380 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1381 "stw $rS, $src", LdStStore,
1382 [(store i32:$rS, iaddr:$src)]>;
1383 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1384 "stfs $rS, $dst", LdStSTFD,
1385 [(store f32:$rS, iaddr:$dst)]>;
1386 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1387 "stfd $rS, $dst", LdStSTFD,
1388 [(store f64:$rS, iaddr:$dst)]>;
1391 // Unindexed (r+i) Stores with Update (preinc).
1392 let PPC970_Unit = 2, mayStore = 1 in {
1393 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1394 "stbu $rS, $dst", LdStStoreUpd, []>,
1395 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1396 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1397 "sthu $rS, $dst", LdStStoreUpd, []>,
1398 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1399 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1400 "stwu $rS, $dst", LdStStoreUpd, []>,
1401 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1402 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1403 "stfsu $rS, $dst", LdStSTFDU, []>,
1404 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1405 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1406 "stfdu $rS, $dst", LdStSTFDU, []>,
1407 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1410 // Patterns to match the pre-inc stores. We can't put the patterns on
1411 // the instruction definitions directly as ISel wants the address base
1412 // and offset to be separate operands, not a single complex operand.
1413 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1414 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1415 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1416 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1417 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1418 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1419 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1420 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1421 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1422 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1424 // Indexed (r+r) Stores.
1425 let PPC970_Unit = 2 in {
1426 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1427 "stbx $rS, $dst", LdStStore,
1428 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1429 PPC970_DGroup_Cracked;
1430 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1431 "sthx $rS, $dst", LdStStore,
1432 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1433 PPC970_DGroup_Cracked;
1434 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1435 "stwx $rS, $dst", LdStStore,
1436 [(store i32:$rS, xaddr:$dst)]>,
1437 PPC970_DGroup_Cracked;
1439 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1440 "sthbrx $rS, $dst", LdStStore,
1441 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1442 PPC970_DGroup_Cracked;
1443 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1444 "stwbrx $rS, $dst", LdStStore,
1445 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1446 PPC970_DGroup_Cracked;
1448 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1449 "stfiwx $frS, $dst", LdStSTFD,
1450 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1452 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1453 "stfsx $frS, $dst", LdStSTFD,
1454 [(store f32:$frS, xaddr:$dst)]>;
1455 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1456 "stfdx $frS, $dst", LdStSTFD,
1457 [(store f64:$frS, xaddr:$dst)]>;
1460 // Indexed (r+r) Stores with Update (preinc).
1461 let PPC970_Unit = 2, mayStore = 1 in {
1462 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1463 "stbux $rS, $dst", LdStStoreUpd, []>,
1464 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1465 PPC970_DGroup_Cracked;
1466 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1467 "sthux $rS, $dst", LdStStoreUpd, []>,
1468 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1469 PPC970_DGroup_Cracked;
1470 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1471 "stwux $rS, $dst", LdStStoreUpd, []>,
1472 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1473 PPC970_DGroup_Cracked;
1474 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1475 "stfsux $rS, $dst", LdStSTFDU, []>,
1476 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1477 PPC970_DGroup_Cracked;
1478 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1479 "stfdux $rS, $dst", LdStSTFDU, []>,
1480 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1481 PPC970_DGroup_Cracked;
1484 // Patterns to match the pre-inc stores. We can't put the patterns on
1485 // the instruction definitions directly as ISel wants the address base
1486 // and offset to be separate operands, not a single complex operand.
1487 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1488 (STBUX $rS, $ptrreg, $ptroff)>;
1489 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1490 (STHUX $rS, $ptrreg, $ptroff)>;
1491 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1492 (STWUX $rS, $ptrreg, $ptroff)>;
1493 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1494 (STFSUX $rS, $ptrreg, $ptroff)>;
1495 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1496 (STFDUX $rS, $ptrreg, $ptroff)>;
1498 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
1502 //===----------------------------------------------------------------------===//
1503 // PPC32 Arithmetic Instructions.
1506 let PPC970_Unit = 1 in { // FXU Operations.
1507 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1508 "addi $rD, $rA, $imm", IntSimple,
1509 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1510 let BaseName = "addic" in {
1511 let Defs = [CARRY] in
1512 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1513 "addic $rD, $rA, $imm", IntGeneral,
1514 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1515 RecFormRel, PPC970_DGroup_Cracked;
1516 let Defs = [CARRY, CR0] in
1517 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1518 "addic. $rD, $rA, $imm", IntGeneral,
1519 []>, isDOT, RecFormRel;
1521 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1522 "addis $rD, $rA, $imm", IntSimple,
1523 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1524 let isCodeGenOnly = 1 in
1525 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1526 "la $rD, $sym($rA)", IntGeneral,
1527 [(set i32:$rD, (add i32:$rA,
1528 (PPClo tglobaladdr:$sym, 0)))]>;
1529 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1530 "mulli $rD, $rA, $imm", IntMulLI,
1531 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1532 let Defs = [CARRY] in
1533 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1534 "subfic $rD, $rA, $imm", IntGeneral,
1535 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1537 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1538 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1539 "li $rD, $imm", IntSimple,
1540 [(set i32:$rD, imm32SExt16:$imm)]>;
1541 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s16imm:$imm),
1542 "lis $rD, $imm", IntSimple,
1543 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1547 let PPC970_Unit = 1 in { // FXU Operations.
1548 let Defs = [CR0] in {
1549 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1550 "andi. $dst, $src1, $src2", IntGeneral,
1551 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1553 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1554 "andis. $dst, $src1, $src2", IntGeneral,
1555 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1558 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1559 "ori $dst, $src1, $src2", IntSimple,
1560 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1561 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1562 "oris $dst, $src1, $src2", IntSimple,
1563 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1564 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1565 "xori $dst, $src1, $src2", IntSimple,
1566 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1567 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1568 "xoris $dst, $src1, $src2", IntSimple,
1569 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1570 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple,
1572 let isCompare = 1, neverHasSideEffects = 1 in {
1573 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1574 "cmpwi $crD, $rA, $imm", IntCompare>;
1575 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1576 "cmplwi $dst, $src1, $src2", IntCompare>;
1580 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1581 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1582 "nand", "$rA, $rS, $rB", IntSimple,
1583 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1584 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1585 "and", "$rA, $rS, $rB", IntSimple,
1586 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1587 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1588 "andc", "$rA, $rS, $rB", IntSimple,
1589 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1590 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1591 "or", "$rA, $rS, $rB", IntSimple,
1592 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1593 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1594 "nor", "$rA, $rS, $rB", IntSimple,
1595 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1596 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1597 "orc", "$rA, $rS, $rB", IntSimple,
1598 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1599 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1600 "eqv", "$rA, $rS, $rB", IntSimple,
1601 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1602 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1603 "xor", "$rA, $rS, $rB", IntSimple,
1604 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1605 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1606 "slw", "$rA, $rS, $rB", IntGeneral,
1607 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1608 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1609 "srw", "$rA, $rS, $rB", IntGeneral,
1610 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1611 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1612 "sraw", "$rA, $rS, $rB", IntShift,
1613 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1616 let PPC970_Unit = 1 in { // FXU Operations.
1617 let neverHasSideEffects = 1 in {
1618 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1619 "srawi", "$rA, $rS, $SH", IntShift,
1620 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1621 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1622 "cntlzw", "$rA, $rS", IntGeneral,
1623 [(set i32:$rA, (ctlz i32:$rS))]>;
1624 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1625 "extsb", "$rA, $rS", IntSimple,
1626 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1627 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1628 "extsh", "$rA, $rS", IntSimple,
1629 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1631 let isCompare = 1, neverHasSideEffects = 1 in {
1632 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1633 "cmpw $crD, $rA, $rB", IntCompare>;
1634 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1635 "cmplw $crD, $rA, $rB", IntCompare>;
1638 let PPC970_Unit = 3 in { // FPU Operations.
1639 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1640 // "fcmpo $crD, $fA, $fB", FPCompare>;
1641 let isCompare = 1, neverHasSideEffects = 1 in {
1642 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1643 "fcmpu $crD, $fA, $fB", FPCompare>;
1644 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1645 "fcmpu $crD, $fA, $fB", FPCompare>;
1648 let Uses = [RM] in {
1649 let neverHasSideEffects = 1 in {
1650 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1651 "fctiwz", "$frD, $frB", FPGeneral,
1652 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1654 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1655 "frsp", "$frD, $frB", FPGeneral,
1656 [(set f32:$frD, (fround f64:$frB))]>;
1658 // The frin -> nearbyint mapping is valid only in fast-math mode.
1659 let Interpretation64Bit = 1 in
1660 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1661 "frin", "$frD, $frB", FPGeneral,
1662 [(set f64:$frD, (fnearbyint f64:$frB))]>;
1663 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1664 "frin", "$frD, $frB", FPGeneral,
1665 [(set f32:$frD, (fnearbyint f32:$frB))]>;
1668 // These pseudos expand to rint but also set FE_INEXACT when the result does
1669 // not equal the argument.
1670 let usesCustomInserter = 1, Defs = [RM] in { // FIXME: Model FPSCR!
1671 def FRINDrint : Pseudo<(outs f8rc:$frD), (ins f8rc:$frB),
1672 "#FRINDrint", [(set f64:$frD, (frint f64:$frB))]>;
1673 def FRINSrint : Pseudo<(outs f4rc:$frD), (ins f4rc:$frB),
1674 "#FRINSrint", [(set f32:$frD, (frint f32:$frB))]>;
1677 let neverHasSideEffects = 1 in {
1678 let Interpretation64Bit = 1 in
1679 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1680 "frip", "$frD, $frB", FPGeneral,
1681 [(set f64:$frD, (fceil f64:$frB))]>;
1682 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1683 "frip", "$frD, $frB", FPGeneral,
1684 [(set f32:$frD, (fceil f32:$frB))]>;
1685 let Interpretation64Bit = 1 in
1686 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1687 "friz", "$frD, $frB", FPGeneral,
1688 [(set f64:$frD, (ftrunc f64:$frB))]>;
1689 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1690 "friz", "$frD, $frB", FPGeneral,
1691 [(set f32:$frD, (ftrunc f32:$frB))]>;
1692 let Interpretation64Bit = 1 in
1693 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1694 "frim", "$frD, $frB", FPGeneral,
1695 [(set f64:$frD, (ffloor f64:$frB))]>;
1696 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1697 "frim", "$frD, $frB", FPGeneral,
1698 [(set f32:$frD, (ffloor f32:$frB))]>;
1700 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1701 "fsqrt", "$frD, $frB", FPSqrt,
1702 [(set f64:$frD, (fsqrt f64:$frB))]>;
1703 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1704 "fsqrts", "$frD, $frB", FPSqrt,
1705 [(set f32:$frD, (fsqrt f32:$frB))]>;
1710 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1711 /// often coalesced away and we don't want the dispatch group builder to think
1712 /// that they will fill slots (which could cause the load of a LSU reject to
1713 /// sneak into a d-group with a store).
1714 let neverHasSideEffects = 1 in
1715 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1716 "fmr", "$frD, $frB", FPGeneral,
1717 []>, // (set f32:$frD, f32:$frB)
1720 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1721 // These are artificially split into two different forms, for 4/8 byte FP.
1722 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
1723 "fabs", "$frD, $frB", FPGeneral,
1724 [(set f32:$frD, (fabs f32:$frB))]>;
1725 let Interpretation64Bit = 1 in
1726 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
1727 "fabs", "$frD, $frB", FPGeneral,
1728 [(set f64:$frD, (fabs f64:$frB))]>;
1729 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
1730 "fnabs", "$frD, $frB", FPGeneral,
1731 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1732 let Interpretation64Bit = 1 in
1733 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
1734 "fnabs", "$frD, $frB", FPGeneral,
1735 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1736 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
1737 "fneg", "$frD, $frB", FPGeneral,
1738 [(set f32:$frD, (fneg f32:$frB))]>;
1739 let Interpretation64Bit = 1 in
1740 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
1741 "fneg", "$frD, $frB", FPGeneral,
1742 [(set f64:$frD, (fneg f64:$frB))]>;
1744 // Reciprocal estimates.
1745 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
1746 "fre", "$frD, $frB", FPGeneral,
1747 [(set f64:$frD, (PPCfre f64:$frB))]>;
1748 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
1749 "fres", "$frD, $frB", FPGeneral,
1750 [(set f32:$frD, (PPCfre f32:$frB))]>;
1751 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
1752 "frsqrte", "$frD, $frB", FPGeneral,
1753 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1754 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
1755 "frsqrtes", "$frD, $frB", FPGeneral,
1756 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
1759 // XL-Form instructions. condition register logical ops.
1761 let neverHasSideEffects = 1 in
1762 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
1763 "mcrf $BF, $BFA", BrMCR>,
1764 PPC970_DGroup_First, PPC970_Unit_CRU;
1766 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
1767 (ins crbitrc:$CRA, crbitrc:$CRB),
1768 "creqv $CRD, $CRA, $CRB", BrCR,
1771 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
1772 (ins crbitrc:$CRA, crbitrc:$CRB),
1773 "cror $CRD, $CRA, $CRB", BrCR,
1776 let isCodeGenOnly = 1 in {
1777 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
1778 "creqv $dst, $dst, $dst", BrCR,
1781 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
1782 "crxor $dst, $dst, $dst", BrCR,
1785 let Defs = [CR1EQ], CRD = 6 in {
1786 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1787 "creqv 6, 6, 6", BrCR,
1790 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
1791 "crxor 6, 6, 6", BrCR,
1796 // XFX-Form instructions. Instructions that deal with SPRs.
1798 let Uses = [CTR] in {
1799 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
1800 "mfctr $rT", SprMFSPR>,
1801 PPC970_DGroup_First, PPC970_Unit_FXU;
1803 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
1804 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
1805 "mtctr $rS", SprMTSPR>,
1806 PPC970_DGroup_First, PPC970_Unit_FXU;
1808 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
1809 let Pattern = [(int_ppc_mtctr i32:$rS)] in
1810 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
1811 "mtctr $rS", SprMTSPR>,
1812 PPC970_DGroup_First, PPC970_Unit_FXU;
1815 let Defs = [LR] in {
1816 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
1817 "mtlr $rS", SprMTSPR>,
1818 PPC970_DGroup_First, PPC970_Unit_FXU;
1820 let Uses = [LR] in {
1821 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
1822 "mflr $rT", SprMFSPR>,
1823 PPC970_DGroup_First, PPC970_Unit_FXU;
1826 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1827 // a GPR on the PPC970. As such, copies in and out have the same performance
1828 // characteristics as an OR instruction.
1829 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
1830 "mtspr 256, $rS", IntGeneral>,
1831 PPC970_DGroup_Single, PPC970_Unit_FXU;
1832 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
1833 "mfspr $rT, 256", IntGeneral>,
1834 PPC970_DGroup_First, PPC970_Unit_FXU;
1836 let isCodeGenOnly = 1 in {
1837 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
1838 (outs VRSAVERC:$reg), (ins gprc:$rS),
1839 "mtspr 256, $rS", IntGeneral>,
1840 PPC970_DGroup_Single, PPC970_Unit_FXU;
1841 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
1842 (ins VRSAVERC:$reg),
1843 "mfspr $rT, 256", IntGeneral>,
1844 PPC970_DGroup_First, PPC970_Unit_FXU;
1847 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
1848 // so we'll need to scavenge a register for it.
1850 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
1851 "#SPILL_VRSAVE", []>;
1853 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
1854 // spilled), so we'll need to scavenge a register for it.
1856 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
1857 "#RESTORE_VRSAVE", []>;
1859 let neverHasSideEffects = 1 in {
1860 def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins gprc:$rS),
1861 "mtcrf $FXM, $rS", BrMCRX>,
1862 PPC970_MicroCode, PPC970_Unit_CRU;
1864 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
1865 // declaring that here gives the local register allocator problems with this:
1867 // MFCR <kill of whatever preg got assigned to vreg>
1868 // while not declaring it breaks DeadMachineInstructionElimination.
1869 // As it turns out, in all cases where we currently use this,
1870 // we're only interested in one subregister of it. Represent this in the
1871 // instruction to keep the register allocator from becoming confused.
1873 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
1874 let isCodeGenOnly = 1 in
1875 def MFCRpseud: XFXForm_3<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
1876 "#MFCRpseud", SprMFCR>,
1877 PPC970_MicroCode, PPC970_Unit_CRU;
1879 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
1880 "mfocrf $rT, $FXM", SprMFCR>,
1881 PPC970_DGroup_First, PPC970_Unit_CRU;
1882 } // neverHasSideEffects = 1
1884 let neverHasSideEffects = 1 in
1885 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
1886 "mfcr $rT", SprMFCR>,
1887 PPC970_MicroCode, PPC970_Unit_CRU;
1889 // Pseudo instruction to perform FADD in round-to-zero mode.
1890 let usesCustomInserter = 1, Uses = [RM] in {
1891 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
1892 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
1895 // The above pseudo gets expanded to make use of the following instructions
1896 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
1897 let Uses = [RM], Defs = [RM] in {
1898 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1899 "mtfsb0 $FM", IntMTFSB0, []>,
1900 PPC970_DGroup_Single, PPC970_Unit_FPU;
1901 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1902 "mtfsb1 $FM", IntMTFSB0, []>,
1903 PPC970_DGroup_Single, PPC970_Unit_FPU;
1904 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
1905 "mtfsf $FM, $rT", IntMTFSB0, []>,
1906 PPC970_DGroup_Single, PPC970_Unit_FPU;
1908 let Uses = [RM] in {
1909 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
1910 "mffs $rT", IntMFFS,
1911 [(set f64:$rT, (PPCmffs))]>,
1912 PPC970_DGroup_Single, PPC970_Unit_FPU;
1916 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1917 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1919 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1920 "add", "$rT, $rA, $rB", IntSimple,
1921 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
1922 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1923 "addc", "$rT, $rA, $rB", IntGeneral,
1924 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
1925 PPC970_DGroup_Cracked;
1926 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1927 "divw", "$rT, $rA, $rB", IntDivW,
1928 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
1929 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1930 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1931 "divwu", "$rT, $rA, $rB", IntDivW,
1932 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
1933 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1934 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1935 "mulhw", "$rT, $rA, $rB", IntMulHW,
1936 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
1937 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1938 "mulhwu", "$rT, $rA, $rB", IntMulHWU,
1939 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
1940 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1941 "mullw", "$rT, $rA, $rB", IntMulHW,
1942 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
1943 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1944 "subf", "$rT, $rA, $rB", IntGeneral,
1945 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
1946 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1947 "subfc", "$rT, $rA, $rB", IntGeneral,
1948 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
1949 PPC970_DGroup_Cracked;
1950 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
1951 "neg", "$rT, $rA", IntSimple,
1952 [(set i32:$rT, (ineg i32:$rA))]>;
1953 let Uses = [CARRY] in {
1954 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1955 "adde", "$rT, $rA, $rB", IntGeneral,
1956 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
1957 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
1958 "addme", "$rT, $rA", IntGeneral,
1959 [(set i32:$rT, (adde i32:$rA, -1))]>;
1960 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
1961 "addze", "$rT, $rA", IntGeneral,
1962 [(set i32:$rT, (adde i32:$rA, 0))]>;
1963 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1964 "subfe", "$rT, $rA, $rB", IntGeneral,
1965 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
1966 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
1967 "subfme", "$rT, $rA", IntGeneral,
1968 [(set i32:$rT, (sube -1, i32:$rA))]>;
1969 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
1970 "subfze", "$rT, $rA", IntGeneral,
1971 [(set i32:$rT, (sube 0, i32:$rA))]>;
1975 // A-Form instructions. Most of the instructions executed in the FPU are of
1978 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1979 let Uses = [RM] in {
1980 defm FMADD : AForm_1r<63, 29,
1981 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
1982 "fmadd", "$FRT, $FRA, $FRC, $FRB", FPFused,
1983 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
1984 defm FMADDS : AForm_1r<59, 29,
1985 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
1986 "fmadds", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1987 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
1988 defm FMSUB : AForm_1r<63, 28,
1989 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
1990 "fmsub", "$FRT, $FRA, $FRC, $FRB", FPFused,
1992 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
1993 defm FMSUBS : AForm_1r<59, 28,
1994 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
1995 "fmsubs", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1997 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
1998 defm FNMADD : AForm_1r<63, 31,
1999 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2000 "fnmadd", "$FRT, $FRA, $FRC, $FRB", FPFused,
2002 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2003 defm FNMADDS : AForm_1r<59, 31,
2004 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2005 "fnmadds", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
2007 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2008 defm FNMSUB : AForm_1r<63, 30,
2009 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2010 "fnmsub", "$FRT, $FRA, $FRC, $FRB", FPFused,
2011 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2012 (fneg f64:$FRB))))]>;
2013 defm FNMSUBS : AForm_1r<59, 30,
2014 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2015 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
2016 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2017 (fneg f32:$FRB))))]>;
2019 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2020 // having 4 of these, force the comparison to always be an 8-byte double (code
2021 // should use an FMRSD if the input comparison value really wants to be a float)
2022 // and 4/8 byte forms for the result and operand type..
2023 let Interpretation64Bit = 1 in
2024 defm FSELD : AForm_1r<63, 23,
2025 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2026 "fsel", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
2027 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2028 defm FSELS : AForm_1r<63, 23,
2029 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2030 "fsel", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
2031 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2032 let Uses = [RM] in {
2033 defm FADD : AForm_2r<63, 21,
2034 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2035 "fadd", "$FRT, $FRA, $FRB", FPAddSub,
2036 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2037 defm FADDS : AForm_2r<59, 21,
2038 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2039 "fadds", "$FRT, $FRA, $FRB", FPGeneral,
2040 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2041 defm FDIV : AForm_2r<63, 18,
2042 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2043 "fdiv", "$FRT, $FRA, $FRB", FPDivD,
2044 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2045 defm FDIVS : AForm_2r<59, 18,
2046 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2047 "fdivs", "$FRT, $FRA, $FRB", FPDivS,
2048 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2049 defm FMUL : AForm_3r<63, 25,
2050 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2051 "fmul", "$FRT, $FRA, $FRC", FPFused,
2052 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2053 defm FMULS : AForm_3r<59, 25,
2054 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2055 "fmuls", "$FRT, $FRA, $FRC", FPGeneral,
2056 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2057 defm FSUB : AForm_2r<63, 20,
2058 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2059 "fsub", "$FRT, $FRA, $FRB", FPAddSub,
2060 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2061 defm FSUBS : AForm_2r<59, 20,
2062 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2063 "fsubs", "$FRT, $FRA, $FRB", FPGeneral,
2064 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2068 let neverHasSideEffects = 1 in {
2069 let PPC970_Unit = 1 in { // FXU Operations.
2071 def ISEL : AForm_4<31, 15,
2072 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2073 "isel $rT, $rA, $rB, $cond", IntGeneral,
2077 let PPC970_Unit = 1 in { // FXU Operations.
2078 // M-Form instructions. rotate and mask instructions.
2080 let isCommutable = 1 in {
2081 // RLWIMI can be commuted if the rotate amount is zero.
2082 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2083 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2084 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", IntRotate,
2085 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
2088 let BaseName = "rlwinm" in {
2089 def RLWINM : MForm_2<21,
2090 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2091 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
2094 def RLWINMo : MForm_2<21,
2095 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2096 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
2097 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2099 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2100 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2101 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IntGeneral,
2104 } // neverHasSideEffects = 1
2106 //===----------------------------------------------------------------------===//
2107 // PowerPC Instruction Patterns
2110 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2111 def : Pat<(i32 imm:$imm),
2112 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2114 // Implement the 'not' operation with the NOR instruction.
2115 def NOT : Pat<(not i32:$in),
2118 // ADD an arbitrary immediate.
2119 def : Pat<(add i32:$in, imm:$imm),
2120 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2121 // OR an arbitrary immediate.
2122 def : Pat<(or i32:$in, imm:$imm),
2123 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2124 // XOR an arbitrary immediate.
2125 def : Pat<(xor i32:$in, imm:$imm),
2126 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2128 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2129 (SUBFIC $in, imm:$imm)>;
2132 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2133 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2134 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2135 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2138 def : Pat<(rotl i32:$in, i32:$sh),
2139 (RLWNM $in, $sh, 0, 31)>;
2140 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2141 (RLWINM $in, imm:$imm, 0, 31)>;
2144 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2145 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2148 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2149 (BL tglobaladdr:$dst)>;
2150 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2151 (BL texternalsym:$dst)>;
2154 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2155 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2157 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2158 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2160 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2161 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2165 // Hi and Lo for Darwin Global Addresses.
2166 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2167 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2168 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2169 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2170 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2171 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2172 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2173 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2174 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2175 (ADDIS $in, tglobaltlsaddr:$g)>;
2176 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2177 (ADDI $in, tglobaltlsaddr:$g)>;
2178 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2179 (ADDIS $in, tglobaladdr:$g)>;
2180 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2181 (ADDIS $in, tconstpool:$g)>;
2182 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2183 (ADDIS $in, tjumptable:$g)>;
2184 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2185 (ADDIS $in, tblockaddress:$g)>;
2187 // Standard shifts. These are represented separately from the real shifts above
2188 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2190 def : Pat<(sra i32:$rS, i32:$rB),
2192 def : Pat<(srl i32:$rS, i32:$rB),
2194 def : Pat<(shl i32:$rS, i32:$rB),
2197 def : Pat<(zextloadi1 iaddr:$src),
2199 def : Pat<(zextloadi1 xaddr:$src),
2201 def : Pat<(extloadi1 iaddr:$src),
2203 def : Pat<(extloadi1 xaddr:$src),
2205 def : Pat<(extloadi8 iaddr:$src),
2207 def : Pat<(extloadi8 xaddr:$src),
2209 def : Pat<(extloadi16 iaddr:$src),
2211 def : Pat<(extloadi16 xaddr:$src),
2213 def : Pat<(f64 (extloadf32 iaddr:$src)),
2214 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2215 def : Pat<(f64 (extloadf32 xaddr:$src)),
2216 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2218 def : Pat<(f64 (fextend f32:$src)),
2219 (COPY_TO_REGCLASS $src, F8RC)>;
2221 def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
2223 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2224 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2225 (FNMSUB $A, $C, $B)>;
2226 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2227 (FNMSUB $A, $C, $B)>;
2228 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2229 (FNMSUBS $A, $C, $B)>;
2230 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2231 (FNMSUBS $A, $C, $B)>;
2233 include "PPCInstrAltivec.td"
2234 include "PPCInstr64Bit.td"
2237 //===----------------------------------------------------------------------===//
2238 // PowerPC Instructions used for assembler/disassembler only
2241 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
2242 "isync", SprISYNC, []>;
2244 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
2245 "icbi $src", LdStICBI, []>;
2247 //===----------------------------------------------------------------------===//
2248 // PowerPC Assembler Instruction Aliases
2251 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
2252 // These are aliases that require C++ handling to convert to the target
2253 // instruction, while InstAliases can be handled directly by tblgen.
2254 class PPCAsmPseudo<string asm, dag iops>
2256 let Namespace = "PPC";
2257 bit PPC64 = 0; // Default value, override with isPPC64
2259 let OutOperandList = (outs);
2260 let InOperandList = iops;
2262 let AsmString = asm;
2263 let isAsmParserOnly = 1;
2267 def : InstAlias<"sc", (SC 0)>;
2269 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2271 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
2272 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2273 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
2274 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2275 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
2276 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2277 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
2278 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2280 // These generic branch instruction forms are used for the assembler parser only.
2281 // Defs and Uses are conservative, since we don't know the BO value.
2282 let PPC970_Unit = 7 in {
2283 let Defs = [CTR], Uses = [CTR, RM] in {
2284 def gBC : BForm_3<16, 0, 0, (outs),
2285 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
2286 "bc $bo, $bi, $dst">;
2287 def gBCA : BForm_3<16, 1, 0, (outs),
2288 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
2289 "bca $bo, $bi, $dst">;
2291 let Defs = [LR, CTR], Uses = [CTR, RM] in {
2292 def gBCL : BForm_3<16, 0, 1, (outs),
2293 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
2294 "bcl $bo, $bi, $dst">;
2295 def gBCLA : BForm_3<16, 1, 1, (outs),
2296 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
2297 "bcla $bo, $bi, $dst">;
2299 let Defs = [CTR], Uses = [CTR, LR, RM] in
2300 def gBCLR : XLForm_2<19, 16, 0, (outs),
2301 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2302 "bclr $bo, $bi, $bh", BrB, []>;
2303 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
2304 def gBCLRL : XLForm_2<19, 16, 1, (outs),
2305 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2306 "bclrl $bo, $bi, $bh", BrB, []>;
2307 let Defs = [CTR], Uses = [CTR, LR, RM] in
2308 def gBCCTR : XLForm_2<19, 528, 0, (outs),
2309 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2310 "bcctr $bo, $bi, $bh", BrB, []>;
2311 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
2312 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
2313 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
2314 "bcctrl $bo, $bi, $bh", BrB, []>;
2316 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
2317 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
2318 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
2319 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
2321 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
2322 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
2323 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
2324 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
2325 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
2326 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
2327 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
2329 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
2330 : BranchSimpleMnemonic1<name, pm, bo> {
2331 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
2332 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
2334 defm : BranchSimpleMnemonic2<"t", "", 12>;
2335 defm : BranchSimpleMnemonic2<"f", "", 4>;
2336 defm : BranchSimpleMnemonic2<"t", "-", 14>;
2337 defm : BranchSimpleMnemonic2<"f", "-", 6>;
2338 defm : BranchSimpleMnemonic2<"t", "+", 15>;
2339 defm : BranchSimpleMnemonic2<"f", "+", 7>;
2340 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
2341 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
2342 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
2343 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
2345 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
2346 def : InstAlias<"b"#name#pm#" $cc, $dst",
2347 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
2348 def : InstAlias<"b"#name#pm#" $dst",
2349 (BCC bibo, CR0, condbrtarget:$dst)>;
2351 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
2352 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
2353 def : InstAlias<"b"#name#"a"#pm#" $dst",
2354 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
2356 def : InstAlias<"b"#name#"lr"#pm#" $cc",
2357 (BCLR bibo, crrc:$cc)>;
2358 def : InstAlias<"b"#name#"lr"#pm,
2361 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
2362 (BCCTR bibo, crrc:$cc)>;
2363 def : InstAlias<"b"#name#"ctr"#pm,
2366 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
2367 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
2368 def : InstAlias<"b"#name#"l"#pm#" $dst",
2369 (BCCL bibo, CR0, condbrtarget:$dst)>;
2371 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
2372 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
2373 def : InstAlias<"b"#name#"la"#pm#" $dst",
2374 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
2376 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
2377 (BCLRL bibo, crrc:$cc)>;
2378 def : InstAlias<"b"#name#"lrl"#pm,
2381 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
2382 (BCCTRL bibo, crrc:$cc)>;
2383 def : InstAlias<"b"#name#"ctrl"#pm,
2384 (BCCTRL bibo, CR0)>;
2386 multiclass BranchExtendedMnemonic<string name, int bibo> {
2387 defm : BranchExtendedMnemonicPM<name, "", bibo>;
2388 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
2389 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
2391 defm : BranchExtendedMnemonic<"lt", 12>;
2392 defm : BranchExtendedMnemonic<"gt", 44>;
2393 defm : BranchExtendedMnemonic<"eq", 76>;
2394 defm : BranchExtendedMnemonic<"un", 108>;
2395 defm : BranchExtendedMnemonic<"so", 108>;
2396 defm : BranchExtendedMnemonic<"ge", 4>;
2397 defm : BranchExtendedMnemonic<"nl", 4>;
2398 defm : BranchExtendedMnemonic<"le", 36>;
2399 defm : BranchExtendedMnemonic<"ng", 36>;
2400 defm : BranchExtendedMnemonic<"ne", 68>;
2401 defm : BranchExtendedMnemonic<"nu", 100>;
2402 defm : BranchExtendedMnemonic<"ns", 100>;
2404 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
2405 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
2406 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
2407 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
2408 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
2409 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
2410 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
2411 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;