1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
26 def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
38 def SDT_PPClbrx : SDTypeProfile<1, 3, [
39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
41 def SDT_PPCstbrx : SDTypeProfile<0, 4, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
45 def SDT_PPClarx : SDTypeProfile<1, 1, [
46 SDTCisInt<0>, SDTCisPtrTy<1>
48 def SDT_PPCstcx : SDTypeProfile<0, 2, [
49 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
53 SDTCisPtrTy<0>, SDTCisVT<1, i32>
56 //===----------------------------------------------------------------------===//
57 // PowerPC specific DAG Nodes.
60 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
61 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
62 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
63 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
64 [SDNPHasChain, SDNPMayStore]>;
66 // This sequence is used for long double->int conversions. It changes the
67 // bits in the FPSCR which is not modelled.
68 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
70 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
71 [SDNPInFlag, SDNPOutFlag]>;
72 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
73 [SDNPInFlag, SDNPOutFlag]>;
74 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
75 [SDNPInFlag, SDNPOutFlag]>;
76 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
77 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
81 def PPCfsel : SDNode<"PPCISD::FSEL",
82 // Type constraint for fsel.
83 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
84 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
86 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
87 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
88 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
89 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
91 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
93 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
94 // amounts. These nodes are generated by the multi-precision shift code.
95 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
96 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
97 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
99 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
100 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
101 [SDNPHasChain, SDNPMayStore]>;
103 // These are target-independent nodes, but have target-specific formats.
104 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
105 [SDNPHasChain, SDNPOutFlag]>;
106 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
107 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
109 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
110 def PPCcall_Macho : SDNode<"PPCISD::CALL_Macho", SDT_PPCCall,
111 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
112 def PPCcall_ELF : SDNode<"PPCISD::CALL_ELF", SDT_PPCCall,
113 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
114 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
115 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
116 def PPCbctrl_Macho : SDNode<"PPCISD::BCTRL_Macho", SDTNone,
117 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
119 def PPCbctrl_ELF : SDNode<"PPCISD::BCTRL_ELF", SDTNone,
120 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
122 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
123 [SDNPHasChain, SDNPOptInFlag]>;
125 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
126 [SDNPHasChain, SDNPOptInFlag]>;
128 def PPCtailcall : SDNode<"PPCISD::TAILCALL", SDT_PPCCall,
129 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
131 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
132 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
134 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
135 [SDNPHasChain, SDNPOptInFlag]>;
137 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
138 [SDNPHasChain, SDNPMayLoad]>;
139 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
140 [SDNPHasChain, SDNPMayStore]>;
142 // Instructions to support atomic operations
143 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
144 [SDNPHasChain, SDNPMayLoad]>;
145 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
146 [SDNPHasChain, SDNPMayStore]>;
148 // Instructions to support dynamic alloca.
149 def SDTDynOp : SDTypeProfile<1, 2, []>;
150 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
152 //===----------------------------------------------------------------------===//
153 // PowerPC specific transformation functions and pattern fragments.
156 def SHL32 : SDNodeXForm<imm, [{
157 // Transformation function: 31 - imm
158 return getI32Imm(31 - N->getZExtValue());
161 def SRL32 : SDNodeXForm<imm, [{
162 // Transformation function: 32 - imm
163 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
166 def LO16 : SDNodeXForm<imm, [{
167 // Transformation function: get the low 16 bits.
168 return getI32Imm((unsigned short)N->getZExtValue());
171 def HI16 : SDNodeXForm<imm, [{
172 // Transformation function: shift the immediate value down into the low bits.
173 return getI32Imm((unsigned)N->getZExtValue() >> 16);
176 def HA16 : SDNodeXForm<imm, [{
177 // Transformation function: shift the immediate value down into the low bits.
178 signed int Val = N->getZExtValue();
179 return getI32Imm((Val - (signed short)Val) >> 16);
181 def MB : SDNodeXForm<imm, [{
182 // Transformation function: get the start bit of a mask
184 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
185 return getI32Imm(mb);
188 def ME : SDNodeXForm<imm, [{
189 // Transformation function: get the end bit of a mask
191 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
192 return getI32Imm(me);
194 def maskimm32 : PatLeaf<(imm), [{
195 // maskImm predicate - True if immediate is a run of ones.
197 if (N->getValueType(0) == MVT::i32)
198 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
203 def immSExt16 : PatLeaf<(imm), [{
204 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
205 // field. Used by instructions like 'addi'.
206 if (N->getValueType(0) == MVT::i32)
207 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
209 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
211 def immZExt16 : PatLeaf<(imm), [{
212 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
213 // field. Used by instructions like 'ori'.
214 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
217 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
218 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
219 // identical in 32-bit mode, but in 64-bit mode, they return true if the
220 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
222 def imm16ShiftedZExt : PatLeaf<(imm), [{
223 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
224 // immediate are set. Used by instructions like 'xoris'.
225 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
228 def imm16ShiftedSExt : PatLeaf<(imm), [{
229 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
230 // immediate are set. Used by instructions like 'addis'. Identical to
231 // imm16ShiftedZExt in 32-bit mode.
232 if (N->getZExtValue() & 0xFFFF) return false;
233 if (N->getValueType(0) == MVT::i32)
235 // For 64-bit, make sure it is sext right.
236 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
240 //===----------------------------------------------------------------------===//
241 // PowerPC Flag Definitions.
243 class isPPC64 { bit PPC64 = 1; }
245 list<Register> Defs = [CR0];
249 class RegConstraint<string C> {
250 string Constraints = C;
252 class NoEncode<string E> {
253 string DisableEncoding = E;
257 //===----------------------------------------------------------------------===//
258 // PowerPC Operand Definitions.
260 def s5imm : Operand<i32> {
261 let PrintMethod = "printS5ImmOperand";
263 def u5imm : Operand<i32> {
264 let PrintMethod = "printU5ImmOperand";
266 def u6imm : Operand<i32> {
267 let PrintMethod = "printU6ImmOperand";
269 def s16imm : Operand<i32> {
270 let PrintMethod = "printS16ImmOperand";
272 def u16imm : Operand<i32> {
273 let PrintMethod = "printU16ImmOperand";
275 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
276 let PrintMethod = "printS16X4ImmOperand";
278 def target : Operand<OtherVT> {
279 let PrintMethod = "printBranchOperand";
281 def calltarget : Operand<iPTR> {
282 let PrintMethod = "printCallOperand";
284 def aaddr : Operand<iPTR> {
285 let PrintMethod = "printAbsAddrOperand";
287 def piclabel: Operand<iPTR> {
288 let PrintMethod = "printPICLabel";
290 def symbolHi: Operand<i32> {
291 let PrintMethod = "printSymbolHi";
293 def symbolLo: Operand<i32> {
294 let PrintMethod = "printSymbolLo";
296 def crbitm: Operand<i8> {
297 let PrintMethod = "printcrbitm";
300 def memri : Operand<iPTR> {
301 let PrintMethod = "printMemRegImm";
302 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
304 def memrr : Operand<iPTR> {
305 let PrintMethod = "printMemRegReg";
306 let MIOperandInfo = (ops ptr_rc, ptr_rc);
308 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
309 let PrintMethod = "printMemRegImmShifted";
310 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
313 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
314 // that doesn't matter.
315 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
316 (ops (i32 20), (i32 zero_reg))> {
317 let PrintMethod = "printPredicateOperand";
320 // Define PowerPC specific addressing mode.
321 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
322 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
323 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
324 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
326 /// This is just the offset part of iaddr, used for preinc.
327 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
329 //===----------------------------------------------------------------------===//
330 // PowerPC Instruction Predicate Definitions.
331 def FPContractions : Predicate<"!NoExcessFPPrecision">;
332 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
333 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
336 //===----------------------------------------------------------------------===//
337 // PowerPC Instruction Definitions.
339 // Pseudo-instructions:
341 let hasCtrlDep = 1 in {
342 let Defs = [R1], Uses = [R1] in {
343 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt),
344 "${:comment} ADJCALLSTACKDOWN",
345 [(callseq_start timm:$amt)]>;
346 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
347 "${:comment} ADJCALLSTACKUP",
348 [(callseq_end timm:$amt1, timm:$amt2)]>;
351 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
352 "UPDATE_VRSAVE $rD, $rS", []>;
355 let Defs = [R1], Uses = [R1] in
356 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi),
357 "${:comment} DYNALLOC $result, $negsize, $fpsi",
359 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
361 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
362 // scheduler into a branch sequence.
363 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
364 PPC970_Single = 1 in {
365 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
366 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
368 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
369 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
371 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
372 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
374 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
375 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
377 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
378 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
382 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
383 // scavenge a register for it.
384 def SPILL_CR : Pseudo<(outs), (ins GPRC:$cond, memri:$F),
385 "${:comment} SPILL_CR $cond $F", []>;
387 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
388 let isReturn = 1, Uses = [LR, RM] in
389 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
390 "b${p:cc}lr ${p:reg}", BrB,
392 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in
393 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
397 def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>,
400 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
401 let isBarrier = 1 in {
402 def B : IForm<18, 0, 0, (outs), (ins target:$dst),
407 // BCC represents an arbitrary conditional branch on a predicate.
408 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
409 // a two-value operand where a dag node expects two operands. :(
410 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, target:$dst),
411 "b${cond:cc} ${cond:reg}, $dst"
412 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
416 let isCall = 1, PPC970_Unit = 7,
417 // All calls clobber the non-callee saved registers...
418 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
419 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
420 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
423 CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ,
424 CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN] in {
425 // Convenient aliases for call instructions
427 def BL_Macho : IForm<18, 0, 1,
428 (outs), (ins calltarget:$func, variable_ops),
429 "bl $func", BrB, []>; // See Pat patterns below.
430 def BLA_Macho : IForm<18, 1, 1,
431 (outs), (ins aaddr:$func, variable_ops),
432 "bla $func", BrB, [(PPCcall_Macho (i32 imm:$func))]>;
434 let Uses = [CTR, RM] in {
435 def BCTRL_Macho : XLForm_2_ext<19, 528, 20, 0, 1,
436 (outs), (ins variable_ops),
438 [(PPCbctrl_Macho)]>, Requires<[In32BitMode]>;
443 let isCall = 1, PPC970_Unit = 7,
444 // All calls clobber the non-callee saved registers...
445 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
446 F0,F1,F2,F3,F4,F5,F6,F7,F8,
447 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
450 CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ,
451 CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN] in {
452 // Convenient aliases for call instructions
454 def BL_ELF : IForm<18, 0, 1,
455 (outs), (ins calltarget:$func, variable_ops),
456 "bl $func", BrB, []>; // See Pat patterns below.
457 def BLA_ELF : IForm<18, 1, 1,
458 (outs), (ins aaddr:$func, variable_ops),
460 [(PPCcall_ELF (i32 imm:$func))]>;
462 let Uses = [CTR, RM] in {
463 def BCTRL_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
464 (outs), (ins variable_ops),
466 [(PPCbctrl_ELF)]>, Requires<[In32BitMode]>;
471 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
472 def TCRETURNdi :Pseudo< (outs),
473 (ins calltarget:$dst, i32imm:$offset, variable_ops),
474 "#TC_RETURNd $dst $offset",
478 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
479 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops),
480 "#TC_RETURNa $func $offset",
481 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
483 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
484 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset, variable_ops),
485 "#TC_RETURNr $dst $offset",
489 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
490 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
491 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
492 Requires<[In32BitMode]>;
496 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
497 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
498 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
503 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
504 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
505 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
510 // DCB* instructions.
511 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
512 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
513 PPC970_DGroup_Single;
514 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
515 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
516 PPC970_DGroup_Single;
517 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
518 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
519 PPC970_DGroup_Single;
520 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
521 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
522 PPC970_DGroup_Single;
523 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
524 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
525 PPC970_DGroup_Single;
526 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
527 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
528 PPC970_DGroup_Single;
529 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
530 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
531 PPC970_DGroup_Single;
532 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
533 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
534 PPC970_DGroup_Single;
537 let usesCustomDAGSchedInserter = 1 in {
538 let Uses = [CR0] in {
539 def ATOMIC_LOAD_ADD_I8 : Pseudo<
540 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
541 "${:comment} ATOMIC_LOAD_ADD_I8 PSEUDO!",
542 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>;
543 def ATOMIC_LOAD_SUB_I8 : Pseudo<
544 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
545 "${:comment} ATOMIC_LOAD_SUB_I8 PSEUDO!",
546 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>;
547 def ATOMIC_LOAD_AND_I8 : Pseudo<
548 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
549 "${:comment} ATOMIC_LOAD_AND_I8 PSEUDO!",
550 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>;
551 def ATOMIC_LOAD_OR_I8 : Pseudo<
552 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
553 "${:comment} ATOMIC_LOAD_OR_I8 PSEUDO!",
554 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>;
555 def ATOMIC_LOAD_XOR_I8 : Pseudo<
556 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
557 "${:comment} ATOMIC_LOAD_XOR_I8 PSEUDO!",
558 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>;
559 def ATOMIC_LOAD_NAND_I8 : Pseudo<
560 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
561 "${:comment} ATOMIC_LOAD_NAND_I8 PSEUDO!",
562 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>;
563 def ATOMIC_LOAD_ADD_I16 : Pseudo<
564 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
565 "${:comment} ATOMIC_LOAD_ADD_I16 PSEUDO!",
566 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>;
567 def ATOMIC_LOAD_SUB_I16 : Pseudo<
568 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
569 "${:comment} ATOMIC_LOAD_SUB_I16 PSEUDO!",
570 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>;
571 def ATOMIC_LOAD_AND_I16 : Pseudo<
572 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
573 "${:comment} ATOMIC_LOAD_AND_I16 PSEUDO!",
574 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>;
575 def ATOMIC_LOAD_OR_I16 : Pseudo<
576 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
577 "${:comment} ATOMIC_LOAD_OR_I16 PSEUDO!",
578 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>;
579 def ATOMIC_LOAD_XOR_I16 : Pseudo<
580 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
581 "${:comment} ATOMIC_LOAD_XOR_I16 PSEUDO!",
582 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>;
583 def ATOMIC_LOAD_NAND_I16 : Pseudo<
584 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
585 "${:comment} ATOMIC_LOAD_NAND_I16 PSEUDO!",
586 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>;
587 def ATOMIC_LOAD_ADD_I32 : Pseudo<
588 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
589 "${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!",
590 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>;
591 def ATOMIC_LOAD_SUB_I32 : Pseudo<
592 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
593 "${:comment} ATOMIC_LOAD_SUB_I32 PSEUDO!",
594 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>;
595 def ATOMIC_LOAD_AND_I32 : Pseudo<
596 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
597 "${:comment} ATOMIC_LOAD_AND_I32 PSEUDO!",
598 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>;
599 def ATOMIC_LOAD_OR_I32 : Pseudo<
600 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
601 "${:comment} ATOMIC_LOAD_OR_I32 PSEUDO!",
602 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>;
603 def ATOMIC_LOAD_XOR_I32 : Pseudo<
604 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
605 "${:comment} ATOMIC_LOAD_XOR_I32 PSEUDO!",
606 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>;
607 def ATOMIC_LOAD_NAND_I32 : Pseudo<
608 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
609 "${:comment} ATOMIC_LOAD_NAND_I32 PSEUDO!",
610 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>;
612 def ATOMIC_CMP_SWAP_I8 : Pseudo<
613 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new),
614 "${:comment} ATOMIC_CMP_SWAP_I8 PSEUDO!",
616 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
617 def ATOMIC_CMP_SWAP_I16 : Pseudo<
618 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new),
619 "${:comment} ATOMIC_CMP_SWAP_I16 PSEUDO!",
621 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
622 def ATOMIC_CMP_SWAP_I32 : Pseudo<
623 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new),
624 "${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!",
626 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
628 def ATOMIC_SWAP_I8 : Pseudo<
629 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new),
630 "${:comment} ATOMIC_SWAP_I8 PSEUDO!",
631 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>;
632 def ATOMIC_SWAP_I16 : Pseudo<
633 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new),
634 "${:comment} ATOMIC_SWAP_I16 PSEUDO!",
635 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>;
636 def ATOMIC_SWAP_I32 : Pseudo<
637 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new),
638 "${:comment} ATOMIC_SWAP_I32 PSEUDO!",
639 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>;
643 // Instructions to support atomic operations
644 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
645 "lwarx $rD, $src", LdStLWARX,
646 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>;
649 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
650 "stwcx. $rS, $dst", LdStSTWCX,
651 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>,
654 let isBarrier = 1, hasCtrlDep = 1 in
655 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStGeneral, [(trap)]>;
657 //===----------------------------------------------------------------------===//
658 // PPC32 Load Instructions.
661 // Unindexed (r+i) Loads.
662 let isSimpleLoad = 1, PPC970_Unit = 2 in {
663 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
664 "lbz $rD, $src", LdStGeneral,
665 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
666 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
667 "lha $rD, $src", LdStLHA,
668 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
669 PPC970_DGroup_Cracked;
670 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
671 "lhz $rD, $src", LdStGeneral,
672 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
673 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
674 "lwz $rD, $src", LdStGeneral,
675 [(set GPRC:$rD, (load iaddr:$src))]>;
677 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
678 "lfs $rD, $src", LdStLFDU,
679 [(set F4RC:$rD, (load iaddr:$src))]>;
680 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
681 "lfd $rD, $src", LdStLFD,
682 [(set F8RC:$rD, (load iaddr:$src))]>;
685 // Unindexed (r+i) Loads with Update (preinc).
686 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
687 "lbzu $rD, $addr", LdStGeneral,
688 []>, RegConstraint<"$addr.reg = $ea_result">,
689 NoEncode<"$ea_result">;
691 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
692 "lhau $rD, $addr", LdStGeneral,
693 []>, RegConstraint<"$addr.reg = $ea_result">,
694 NoEncode<"$ea_result">;
696 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
697 "lhzu $rD, $addr", LdStGeneral,
698 []>, RegConstraint<"$addr.reg = $ea_result">,
699 NoEncode<"$ea_result">;
701 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
702 "lwzu $rD, $addr", LdStGeneral,
703 []>, RegConstraint<"$addr.reg = $ea_result">,
704 NoEncode<"$ea_result">;
706 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
707 "lfs $rD, $addr", LdStLFDU,
708 []>, RegConstraint<"$addr.reg = $ea_result">,
709 NoEncode<"$ea_result">;
711 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
712 "lfd $rD, $addr", LdStLFD,
713 []>, RegConstraint<"$addr.reg = $ea_result">,
714 NoEncode<"$ea_result">;
717 // Indexed (r+r) Loads.
719 let isSimpleLoad = 1, PPC970_Unit = 2 in {
720 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
721 "lbzx $rD, $src", LdStGeneral,
722 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
723 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
724 "lhax $rD, $src", LdStLHA,
725 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
726 PPC970_DGroup_Cracked;
727 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
728 "lhzx $rD, $src", LdStGeneral,
729 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
730 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
731 "lwzx $rD, $src", LdStGeneral,
732 [(set GPRC:$rD, (load xaddr:$src))]>;
735 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
736 "lhbrx $rD, $src", LdStGeneral,
737 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>;
738 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
739 "lwbrx $rD, $src", LdStGeneral,
740 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>;
742 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
743 "lfsx $frD, $src", LdStLFDU,
744 [(set F4RC:$frD, (load xaddr:$src))]>;
745 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
746 "lfdx $frD, $src", LdStLFDU,
747 [(set F8RC:$frD, (load xaddr:$src))]>;
750 //===----------------------------------------------------------------------===//
751 // PPC32 Store Instructions.
754 // Unindexed (r+i) Stores.
755 let PPC970_Unit = 2 in {
756 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
757 "stb $rS, $src", LdStGeneral,
758 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
759 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
760 "sth $rS, $src", LdStGeneral,
761 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
762 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
763 "stw $rS, $src", LdStGeneral,
764 [(store GPRC:$rS, iaddr:$src)]>;
765 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
766 "stfs $rS, $dst", LdStUX,
767 [(store F4RC:$rS, iaddr:$dst)]>;
768 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
769 "stfd $rS, $dst", LdStUX,
770 [(store F8RC:$rS, iaddr:$dst)]>;
773 // Unindexed (r+i) Stores with Update (preinc).
774 let PPC970_Unit = 2 in {
775 def STBU : DForm_1<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
776 symbolLo:$ptroff, ptr_rc:$ptrreg),
777 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
778 [(set ptr_rc:$ea_res,
779 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
780 iaddroff:$ptroff))]>,
781 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
782 def STHU : DForm_1<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
783 symbolLo:$ptroff, ptr_rc:$ptrreg),
784 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
785 [(set ptr_rc:$ea_res,
786 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
787 iaddroff:$ptroff))]>,
788 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
789 def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
790 symbolLo:$ptroff, ptr_rc:$ptrreg),
791 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
792 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
793 iaddroff:$ptroff))]>,
794 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
795 def STFSU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
796 symbolLo:$ptroff, ptr_rc:$ptrreg),
797 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral,
798 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
799 iaddroff:$ptroff))]>,
800 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
801 def STFDU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
802 symbolLo:$ptroff, ptr_rc:$ptrreg),
803 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral,
804 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
805 iaddroff:$ptroff))]>,
806 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
810 // Indexed (r+r) Stores.
812 let PPC970_Unit = 2 in {
813 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
814 "stbx $rS, $dst", LdStGeneral,
815 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
816 PPC970_DGroup_Cracked;
817 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
818 "sthx $rS, $dst", LdStGeneral,
819 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
820 PPC970_DGroup_Cracked;
821 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
822 "stwx $rS, $dst", LdStGeneral,
823 [(store GPRC:$rS, xaddr:$dst)]>,
824 PPC970_DGroup_Cracked;
826 let mayStore = 1 in {
827 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
828 "stwux $rS, $rA, $rB", LdStGeneral,
831 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
832 "sthbrx $rS, $dst", LdStGeneral,
833 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
834 PPC970_DGroup_Cracked;
835 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
836 "stwbrx $rS, $dst", LdStGeneral,
837 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>,
838 PPC970_DGroup_Cracked;
840 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
841 "stfiwx $frS, $dst", LdStUX,
842 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
844 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
845 "stfsx $frS, $dst", LdStUX,
846 [(store F4RC:$frS, xaddr:$dst)]>;
847 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
848 "stfdx $frS, $dst", LdStUX,
849 [(store F8RC:$frS, xaddr:$dst)]>;
853 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
857 //===----------------------------------------------------------------------===//
858 // PPC32 Arithmetic Instructions.
861 let PPC970_Unit = 1 in { // FXU Operations.
862 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
863 "addi $rD, $rA, $imm", IntGeneral,
864 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
865 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
866 "addic $rD, $rA, $imm", IntGeneral,
867 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
868 PPC970_DGroup_Cracked;
869 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
870 "addic. $rD, $rA, $imm", IntGeneral,
872 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
873 "addis $rD, $rA, $imm", IntGeneral,
874 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
875 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
876 "la $rD, $sym($rA)", IntGeneral,
877 [(set GPRC:$rD, (add GPRC:$rA,
878 (PPClo tglobaladdr:$sym, 0)))]>;
879 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
880 "mulli $rD, $rA, $imm", IntMulLI,
881 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
882 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
883 "subfic $rD, $rA, $imm", IntGeneral,
884 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
886 let isReMaterializable = 1 in {
887 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
888 "li $rD, $imm", IntGeneral,
889 [(set GPRC:$rD, immSExt16:$imm)]>;
890 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
891 "lis $rD, $imm", IntGeneral,
892 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
896 let PPC970_Unit = 1 in { // FXU Operations.
897 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
898 "andi. $dst, $src1, $src2", IntGeneral,
899 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
901 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
902 "andis. $dst, $src1, $src2", IntGeneral,
903 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
905 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
906 "ori $dst, $src1, $src2", IntGeneral,
907 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
908 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
909 "oris $dst, $src1, $src2", IntGeneral,
910 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
911 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
912 "xori $dst, $src1, $src2", IntGeneral,
913 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
914 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
915 "xoris $dst, $src1, $src2", IntGeneral,
916 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
917 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral,
919 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
920 "cmpwi $crD, $rA, $imm", IntCompare>;
921 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
922 "cmplwi $dst, $src1, $src2", IntCompare>;
926 let PPC970_Unit = 1 in { // FXU Operations.
927 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
928 "nand $rA, $rS, $rB", IntGeneral,
929 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
930 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
931 "and $rA, $rS, $rB", IntGeneral,
932 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
933 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
934 "andc $rA, $rS, $rB", IntGeneral,
935 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
936 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
937 "or $rA, $rS, $rB", IntGeneral,
938 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
939 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
940 "nor $rA, $rS, $rB", IntGeneral,
941 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
942 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
943 "orc $rA, $rS, $rB", IntGeneral,
944 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
945 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
946 "eqv $rA, $rS, $rB", IntGeneral,
947 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
948 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
949 "xor $rA, $rS, $rB", IntGeneral,
950 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
951 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
952 "slw $rA, $rS, $rB", IntGeneral,
953 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
954 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
955 "srw $rA, $rS, $rB", IntGeneral,
956 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
957 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
958 "sraw $rA, $rS, $rB", IntShift,
959 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
962 let PPC970_Unit = 1 in { // FXU Operations.
963 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
964 "srawi $rA, $rS, $SH", IntShift,
965 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
966 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
967 "cntlzw $rA, $rS", IntGeneral,
968 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
969 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
970 "extsb $rA, $rS", IntGeneral,
971 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
972 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
973 "extsh $rA, $rS", IntGeneral,
974 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
976 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
977 "cmpw $crD, $rA, $rB", IntCompare>;
978 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
979 "cmplw $crD, $rA, $rB", IntCompare>;
981 let PPC970_Unit = 3 in { // FPU Operations.
982 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
983 // "fcmpo $crD, $fA, $fB", FPCompare>;
984 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
985 "fcmpu $crD, $fA, $fB", FPCompare>;
986 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
987 "fcmpu $crD, $fA, $fB", FPCompare>;
990 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
991 "fctiwz $frD, $frB", FPGeneral,
992 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
993 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
994 "frsp $frD, $frB", FPGeneral,
995 [(set F4RC:$frD, (fround F8RC:$frB))]>;
996 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
997 "fsqrt $frD, $frB", FPSqrt,
998 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
999 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
1000 "fsqrts $frD, $frB", FPSqrt,
1001 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
1005 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
1007 /// Note that these are defined as pseudo-ops on the PPC970 because they are
1008 /// often coalesced away and we don't want the dispatch group builder to think
1009 /// that they will fill slots (which could cause the load of a LSU reject to
1010 /// sneak into a d-group with a store).
1011 def FMRS : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
1012 "fmr $frD, $frB", FPGeneral,
1013 []>, // (set F4RC:$frD, F4RC:$frB)
1015 def FMRD : XForm_26<63, 72, (outs F8RC:$frD), (ins F8RC:$frB),
1016 "fmr $frD, $frB", FPGeneral,
1017 []>, // (set F8RC:$frD, F8RC:$frB)
1019 def FMRSD : XForm_26<63, 72, (outs F8RC:$frD), (ins F4RC:$frB),
1020 "fmr $frD, $frB", FPGeneral,
1021 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
1024 let PPC970_Unit = 3 in { // FPU Operations.
1025 // These are artificially split into two different forms, for 4/8 byte FP.
1026 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
1027 "fabs $frD, $frB", FPGeneral,
1028 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
1029 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
1030 "fabs $frD, $frB", FPGeneral,
1031 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
1032 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
1033 "fnabs $frD, $frB", FPGeneral,
1034 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
1035 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
1036 "fnabs $frD, $frB", FPGeneral,
1037 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
1038 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
1039 "fneg $frD, $frB", FPGeneral,
1040 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
1041 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
1042 "fneg $frD, $frB", FPGeneral,
1043 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
1047 // XL-Form instructions. condition register logical ops.
1049 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
1050 "mcrf $BF, $BFA", BrMCR>,
1051 PPC970_DGroup_First, PPC970_Unit_CRU;
1053 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
1054 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1055 "creqv $CRD, $CRA, $CRB", BrCR,
1058 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
1059 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1060 "cror $CRD, $CRA, $CRB", BrCR,
1063 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
1064 "creqv $dst, $dst, $dst", BrCR,
1067 // XFX-Form instructions. Instructions that deal with SPRs.
1069 let Uses = [CTR] in {
1070 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
1071 "mfctr $rT", SprMFSPR>,
1072 PPC970_DGroup_First, PPC970_Unit_FXU;
1074 let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in {
1075 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
1076 "mtctr $rS", SprMTSPR>,
1077 PPC970_DGroup_First, PPC970_Unit_FXU;
1080 let Defs = [LR] in {
1081 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1082 "mtlr $rS", SprMTSPR>,
1083 PPC970_DGroup_First, PPC970_Unit_FXU;
1085 let Uses = [LR] in {
1086 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1087 "mflr $rT", SprMFSPR>,
1088 PPC970_DGroup_First, PPC970_Unit_FXU;
1091 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1092 // a GPR on the PPC970. As such, copies in and out have the same performance
1093 // characteristics as an OR instruction.
1094 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1095 "mtspr 256, $rS", IntGeneral>,
1096 PPC970_DGroup_Single, PPC970_Unit_FXU;
1097 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1098 "mfspr $rT, 256", IntGeneral>,
1099 PPC970_DGroup_First, PPC970_Unit_FXU;
1101 def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS),
1102 "mtcrf $FXM, $rS", BrMCRX>,
1103 PPC970_MicroCode, PPC970_Unit_CRU;
1104 // FIXME: this Uses all the CR registers. Marking it as such is
1105 // necessary for DeadMachineInstructionElim to do the right thing.
1106 // However, marking it also exposes PR 2964, and causes crashes in
1107 // the Local RA because it doesn't like this sequence:
1109 // MFCR <kill of whatever preg got assigned to vreg>
1110 // For now DeadMachineInstructionElim is turned off, so don't do the marking.
1111 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), "mfcr $rT", SprMFCR>,
1112 PPC970_MicroCode, PPC970_Unit_CRU;
1113 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1114 "mfcr $rT, $FXM", SprMFCR>,
1115 PPC970_DGroup_First, PPC970_Unit_CRU;
1117 // Instructions to manipulate FPSCR. Only long double handling uses these.
1118 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
1120 let Uses = [RM], Defs = [RM] in {
1121 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1122 "mtfsb0 $FM", IntMTFSB0,
1123 [(PPCmtfsb0 (i32 imm:$FM))]>,
1124 PPC970_DGroup_Single, PPC970_Unit_FPU;
1125 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1126 "mtfsb1 $FM", IntMTFSB0,
1127 [(PPCmtfsb1 (i32 imm:$FM))]>,
1128 PPC970_DGroup_Single, PPC970_Unit_FPU;
1129 // MTFSF does not actually produce an FP result. We pretend it copies
1130 // input reg B to the output. If we didn't do this it would look like the
1131 // instruction had no outputs (because we aren't modelling the FPSCR) and
1132 // it would be deleted.
1133 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
1134 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
1135 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
1136 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM),
1137 F8RC:$rT, F8RC:$FRB))]>,
1138 PPC970_DGroup_Single, PPC970_Unit_FPU;
1140 let Uses = [RM] in {
1141 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1142 "mffs $rT", IntMFFS,
1143 [(set F8RC:$rT, (PPCmffs))]>,
1144 PPC970_DGroup_Single, PPC970_Unit_FPU;
1145 def FADDrtz: AForm_2<63, 21,
1146 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1147 "fadd $FRT, $FRA, $FRB", FPGeneral,
1148 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>,
1149 PPC970_DGroup_Single, PPC970_Unit_FPU;
1153 let PPC970_Unit = 1 in { // FXU Operations.
1155 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1157 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1158 "add $rT, $rA, $rB", IntGeneral,
1159 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
1160 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1161 "addc $rT, $rA, $rB", IntGeneral,
1162 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
1163 PPC970_DGroup_Cracked;
1164 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1165 "adde $rT, $rA, $rB", IntGeneral,
1166 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
1167 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1168 "divw $rT, $rA, $rB", IntDivW,
1169 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
1170 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1171 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1172 "divwu $rT, $rA, $rB", IntDivW,
1173 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
1174 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1175 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1176 "mulhw $rT, $rA, $rB", IntMulHW,
1177 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
1178 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1179 "mulhwu $rT, $rA, $rB", IntMulHWU,
1180 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
1181 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1182 "mullw $rT, $rA, $rB", IntMulHW,
1183 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
1184 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1185 "subf $rT, $rA, $rB", IntGeneral,
1186 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
1187 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1188 "subfc $rT, $rA, $rB", IntGeneral,
1189 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
1190 PPC970_DGroup_Cracked;
1191 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1192 "subfe $rT, $rA, $rB", IntGeneral,
1193 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
1194 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1195 "addme $rT, $rA", IntGeneral,
1196 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
1197 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1198 "addze $rT, $rA", IntGeneral,
1199 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
1200 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1201 "neg $rT, $rA", IntGeneral,
1202 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
1203 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1204 "subfme $rT, $rA", IntGeneral,
1205 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
1206 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1207 "subfze $rT, $rA", IntGeneral,
1208 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
1211 // A-Form instructions. Most of the instructions executed in the FPU are of
1214 let PPC970_Unit = 3 in { // FPU Operations.
1215 let Uses = [RM] in {
1216 def FMADD : AForm_1<63, 29,
1217 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1218 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1219 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1221 Requires<[FPContractions]>;
1222 def FMADDS : AForm_1<59, 29,
1223 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1224 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1225 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1227 Requires<[FPContractions]>;
1228 def FMSUB : AForm_1<63, 28,
1229 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1230 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1231 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1233 Requires<[FPContractions]>;
1234 def FMSUBS : AForm_1<59, 28,
1235 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1236 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1237 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1239 Requires<[FPContractions]>;
1240 def FNMADD : AForm_1<63, 31,
1241 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1242 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1243 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1245 Requires<[FPContractions]>;
1246 def FNMADDS : AForm_1<59, 31,
1247 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1248 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1249 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1251 Requires<[FPContractions]>;
1252 def FNMSUB : AForm_1<63, 30,
1253 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1254 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1255 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1257 Requires<[FPContractions]>;
1258 def FNMSUBS : AForm_1<59, 30,
1259 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1260 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1261 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1263 Requires<[FPContractions]>;
1265 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1266 // having 4 of these, force the comparison to always be an 8-byte double (code
1267 // should use an FMRSD if the input comparison value really wants to be a float)
1268 // and 4/8 byte forms for the result and operand type..
1269 def FSELD : AForm_1<63, 23,
1270 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1271 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1272 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
1273 def FSELS : AForm_1<63, 23,
1274 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1275 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1276 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
1277 let Uses = [RM] in {
1278 def FADD : AForm_2<63, 21,
1279 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1280 "fadd $FRT, $FRA, $FRB", FPGeneral,
1281 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
1282 def FADDS : AForm_2<59, 21,
1283 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1284 "fadds $FRT, $FRA, $FRB", FPGeneral,
1285 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
1286 def FDIV : AForm_2<63, 18,
1287 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1288 "fdiv $FRT, $FRA, $FRB", FPDivD,
1289 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1290 def FDIVS : AForm_2<59, 18,
1291 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1292 "fdivs $FRT, $FRA, $FRB", FPDivS,
1293 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1294 def FMUL : AForm_3<63, 25,
1295 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1296 "fmul $FRT, $FRA, $FRB", FPFused,
1297 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
1298 def FMULS : AForm_3<59, 25,
1299 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1300 "fmuls $FRT, $FRA, $FRB", FPGeneral,
1301 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
1302 def FSUB : AForm_2<63, 20,
1303 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1304 "fsub $FRT, $FRA, $FRB", FPGeneral,
1305 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1306 def FSUBS : AForm_2<59, 20,
1307 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1308 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1309 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1313 let PPC970_Unit = 1 in { // FXU Operations.
1314 // M-Form instructions. rotate and mask instructions.
1316 let isCommutable = 1 in {
1317 // RLWIMI can be commuted if the rotate amount is zero.
1318 def RLWIMI : MForm_2<20,
1319 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1320 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1321 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1324 def RLWINM : MForm_2<21,
1325 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1326 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1328 def RLWINMo : MForm_2<21,
1329 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1330 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1331 []>, isDOT, PPC970_DGroup_Cracked;
1332 def RLWNM : MForm_2<23,
1333 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1334 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1339 //===----------------------------------------------------------------------===//
1340 // DWARF Pseudo Instructions
1343 def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
1344 "${:comment} .loc $file, $line, $col",
1345 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
1348 //===----------------------------------------------------------------------===//
1349 // PowerPC Instruction Patterns
1352 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1353 def : Pat<(i32 imm:$imm),
1354 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1356 // Implement the 'not' operation with the NOR instruction.
1357 def NOT : Pat<(not GPRC:$in),
1358 (NOR GPRC:$in, GPRC:$in)>;
1360 // ADD an arbitrary immediate.
1361 def : Pat<(add GPRC:$in, imm:$imm),
1362 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1363 // OR an arbitrary immediate.
1364 def : Pat<(or GPRC:$in, imm:$imm),
1365 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1366 // XOR an arbitrary immediate.
1367 def : Pat<(xor GPRC:$in, imm:$imm),
1368 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1370 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1371 (SUBFIC GPRC:$in, imm:$imm)>;
1374 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1375 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1376 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1377 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1380 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1381 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1382 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1383 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1386 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1387 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1390 def : Pat<(PPCcall_Macho (i32 tglobaladdr:$dst)),
1391 (BL_Macho tglobaladdr:$dst)>;
1392 def : Pat<(PPCcall_Macho (i32 texternalsym:$dst)),
1393 (BL_Macho texternalsym:$dst)>;
1394 def : Pat<(PPCcall_ELF (i32 tglobaladdr:$dst)),
1395 (BL_ELF tglobaladdr:$dst)>;
1396 def : Pat<(PPCcall_ELF (i32 texternalsym:$dst)),
1397 (BL_ELF texternalsym:$dst)>;
1400 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1401 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1403 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1404 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1406 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1407 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1411 // Hi and Lo for Darwin Global Addresses.
1412 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1413 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1414 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1415 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1416 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1417 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1418 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1419 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1420 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1421 (ADDIS GPRC:$in, tconstpool:$g)>;
1422 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1423 (ADDIS GPRC:$in, tjumptable:$g)>;
1425 // Fused negative multiply subtract, alternate pattern
1426 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1427 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1428 Requires<[FPContractions]>;
1429 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1430 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1431 Requires<[FPContractions]>;
1433 // Standard shifts. These are represented separately from the real shifts above
1434 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1436 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1437 (SRAW GPRC:$rS, GPRC:$rB)>;
1438 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1439 (SRW GPRC:$rS, GPRC:$rB)>;
1440 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1441 (SLW GPRC:$rS, GPRC:$rB)>;
1443 def : Pat<(zextloadi1 iaddr:$src),
1445 def : Pat<(zextloadi1 xaddr:$src),
1447 def : Pat<(extloadi1 iaddr:$src),
1449 def : Pat<(extloadi1 xaddr:$src),
1451 def : Pat<(extloadi8 iaddr:$src),
1453 def : Pat<(extloadi8 xaddr:$src),
1455 def : Pat<(extloadi16 iaddr:$src),
1457 def : Pat<(extloadi16 xaddr:$src),
1459 def : Pat<(extloadf32 iaddr:$src),
1460 (FMRSD (LFS iaddr:$src))>;
1461 def : Pat<(extloadf32 xaddr:$src),
1462 (FMRSD (LFSX xaddr:$src))>;
1465 def : Pat<(membarrier (i32 imm:$ll),
1472 include "PPCInstrAltivec.td"
1473 include "PPCInstr64Bit.td"