1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPredicates.h"
18 #include "PPCGenInstrInfo.inc"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/Support/CommandLine.h"
25 extern cl::opt<bool> EnablePPCRS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
27 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
28 : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
29 RI(*TM.getSubtargetImpl(), *this) {}
31 /// getPointerRegClass - Return the register class to use to hold pointers.
32 /// This is used for addressing modes.
33 const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
34 if (TM.getSubtargetImpl()->isPPC64())
35 return &PPC::G8RCRegClass;
37 return &PPC::GPRCRegClass;
41 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
43 unsigned& destReg) const {
44 unsigned oc = MI.getOpcode();
45 if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
46 oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
47 assert(MI.getNumOperands() >= 3 &&
48 MI.getOperand(0).isRegister() &&
49 MI.getOperand(1).isRegister() &&
50 MI.getOperand(2).isRegister() &&
51 "invalid PPC OR instruction!");
52 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
53 sourceReg = MI.getOperand(1).getReg();
54 destReg = MI.getOperand(0).getReg();
57 } else if (oc == PPC::ADDI) { // addi r1, r2, 0
58 assert(MI.getNumOperands() >= 3 &&
59 MI.getOperand(0).isRegister() &&
60 MI.getOperand(2).isImmediate() &&
61 "invalid PPC ADDI instruction!");
62 if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImm() == 0) {
63 sourceReg = MI.getOperand(1).getReg();
64 destReg = MI.getOperand(0).getReg();
67 } else if (oc == PPC::ORI) { // ori r1, r2, 0
68 assert(MI.getNumOperands() >= 3 &&
69 MI.getOperand(0).isRegister() &&
70 MI.getOperand(1).isRegister() &&
71 MI.getOperand(2).isImmediate() &&
72 "invalid PPC ORI instruction!");
73 if (MI.getOperand(2).getImm() == 0) {
74 sourceReg = MI.getOperand(1).getReg();
75 destReg = MI.getOperand(0).getReg();
78 } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
79 oc == PPC::FMRSD) { // fmr r1, r2
80 assert(MI.getNumOperands() >= 2 &&
81 MI.getOperand(0).isRegister() &&
82 MI.getOperand(1).isRegister() &&
83 "invalid PPC FMR instruction");
84 sourceReg = MI.getOperand(1).getReg();
85 destReg = MI.getOperand(0).getReg();
87 } else if (oc == PPC::MCRF) { // mcrf cr1, cr2
88 assert(MI.getNumOperands() >= 2 &&
89 MI.getOperand(0).isRegister() &&
90 MI.getOperand(1).isRegister() &&
91 "invalid PPC MCRF instruction");
92 sourceReg = MI.getOperand(1).getReg();
93 destReg = MI.getOperand(0).getReg();
99 unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
100 int &FrameIndex) const {
101 switch (MI->getOpcode()) {
107 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
108 MI->getOperand(2).isFI()) {
109 FrameIndex = MI->getOperand(2).getIndex();
110 return MI->getOperand(0).getReg();
117 unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI,
118 int &FrameIndex) const {
119 switch (MI->getOpcode()) {
125 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
126 MI->getOperand(2).isFI()) {
127 FrameIndex = MI->getOperand(2).getIndex();
128 return MI->getOperand(0).getReg();
135 // commuteInstruction - We can commute rlwimi instructions, but only if the
136 // rotate amt is zero. We also have to munge the immediates a bit.
137 MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
138 // Normal instructions can be commuted the obvious way.
139 if (MI->getOpcode() != PPC::RLWIMI)
140 return TargetInstrInfoImpl::commuteInstruction(MI);
142 // Cannot commute if it has a non-zero rotate count.
143 if (MI->getOperand(3).getImm() != 0)
146 // If we have a zero rotate count, we have:
148 // Op0 = (Op1 & ~M) | (Op2 & M)
150 // M = mask((ME+1)&31, (MB-1)&31)
151 // Op0 = (Op2 & ~M) | (Op1 & M)
154 unsigned Reg0 = MI->getOperand(0).getReg();
155 unsigned Reg1 = MI->getOperand(1).getReg();
156 unsigned Reg2 = MI->getOperand(2).getReg();
157 bool Reg1IsKill = MI->getOperand(1).isKill();
158 bool Reg2IsKill = MI->getOperand(2).isKill();
159 // If machine instrs are no longer in two-address forms, update
160 // destination register as well.
162 // Must be two address instruction!
163 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
164 "Expecting a two-address instruction!");
165 MI->getOperand(0).setReg(Reg2);
168 MI->getOperand(2).setReg(Reg1);
169 MI->getOperand(1).setReg(Reg2);
170 MI->getOperand(2).setIsKill(Reg1IsKill);
171 MI->getOperand(1).setIsKill(Reg2IsKill);
173 // Swap the mask around.
174 unsigned MB = MI->getOperand(4).getImm();
175 unsigned ME = MI->getOperand(5).getImm();
176 MI->getOperand(4).setImm((ME+1) & 31);
177 MI->getOperand(5).setImm((MB-1) & 31);
181 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
182 MachineBasicBlock::iterator MI) const {
183 BuildMI(MBB, MI, get(PPC::NOP));
188 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
189 MachineBasicBlock *&FBB,
190 std::vector<MachineOperand> &Cond) const {
191 // If the block has no terminators, it just falls into the block after it.
192 MachineBasicBlock::iterator I = MBB.end();
193 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
196 // Get the last instruction in the block.
197 MachineInstr *LastInst = I;
199 // If there is only one terminator instruction, process it.
200 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
201 if (LastInst->getOpcode() == PPC::B) {
202 TBB = LastInst->getOperand(0).getMBB();
204 } else if (LastInst->getOpcode() == PPC::BCC) {
205 // Block ends with fall-through condbranch.
206 TBB = LastInst->getOperand(2).getMBB();
207 Cond.push_back(LastInst->getOperand(0));
208 Cond.push_back(LastInst->getOperand(1));
211 // Otherwise, don't know what this is.
215 // Get the instruction before it if it's a terminator.
216 MachineInstr *SecondLastInst = I;
218 // If there are three terminators, we don't know what sort of block this is.
219 if (SecondLastInst && I != MBB.begin() &&
220 isUnpredicatedTerminator(--I))
223 // If the block ends with PPC::B and PPC:BCC, handle it.
224 if (SecondLastInst->getOpcode() == PPC::BCC &&
225 LastInst->getOpcode() == PPC::B) {
226 TBB = SecondLastInst->getOperand(2).getMBB();
227 Cond.push_back(SecondLastInst->getOperand(0));
228 Cond.push_back(SecondLastInst->getOperand(1));
229 FBB = LastInst->getOperand(0).getMBB();
233 // If the block ends with two PPC:Bs, handle it. The second one is not
234 // executed, so remove it.
235 if (SecondLastInst->getOpcode() == PPC::B &&
236 LastInst->getOpcode() == PPC::B) {
237 TBB = SecondLastInst->getOperand(0).getMBB();
239 I->eraseFromParent();
243 // Otherwise, can't handle this.
247 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
248 MachineBasicBlock::iterator I = MBB.end();
249 if (I == MBB.begin()) return 0;
251 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
254 // Remove the branch.
255 I->eraseFromParent();
259 if (I == MBB.begin()) return 1;
261 if (I->getOpcode() != PPC::BCC)
264 // Remove the branch.
265 I->eraseFromParent();
270 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
271 MachineBasicBlock *FBB,
272 const std::vector<MachineOperand> &Cond) const {
273 // Shouldn't be a fall through.
274 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
275 assert((Cond.size() == 2 || Cond.size() == 0) &&
276 "PPC branch conditions have two components!");
280 if (Cond.empty()) // Unconditional branch
281 BuildMI(&MBB, get(PPC::B)).addMBB(TBB);
282 else // Conditional branch
283 BuildMI(&MBB, get(PPC::BCC))
284 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
288 // Two-way Conditional Branch.
289 BuildMI(&MBB, get(PPC::BCC))
290 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
291 BuildMI(&MBB, get(PPC::B)).addMBB(FBB);
295 void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
296 MachineBasicBlock::iterator MI,
297 unsigned DestReg, unsigned SrcReg,
298 const TargetRegisterClass *DestRC,
299 const TargetRegisterClass *SrcRC) const {
300 if (DestRC != SrcRC) {
301 cerr << "Not yet supported!";
305 if (DestRC == PPC::GPRCRegisterClass) {
306 BuildMI(MBB, MI, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
307 } else if (DestRC == PPC::G8RCRegisterClass) {
308 BuildMI(MBB, MI, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
309 } else if (DestRC == PPC::F4RCRegisterClass) {
310 BuildMI(MBB, MI, get(PPC::FMRS), DestReg).addReg(SrcReg);
311 } else if (DestRC == PPC::F8RCRegisterClass) {
312 BuildMI(MBB, MI, get(PPC::FMRD), DestReg).addReg(SrcReg);
313 } else if (DestRC == PPC::CRRCRegisterClass) {
314 BuildMI(MBB, MI, get(PPC::MCRF), DestReg).addReg(SrcReg);
315 } else if (DestRC == PPC::VRRCRegisterClass) {
316 BuildMI(MBB, MI, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
318 cerr << "Attempt to copy register that is not GPR or FPR";
323 static bool StoreRegToStackSlot(const TargetInstrInfo &TII,
324 unsigned SrcReg, bool isKill, int FrameIdx,
325 const TargetRegisterClass *RC,
326 SmallVectorImpl<MachineInstr*> &NewMIs) {
327 if (RC == PPC::GPRCRegisterClass) {
328 if (SrcReg != PPC::LR) {
329 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
330 .addReg(SrcReg, false, false, isKill), FrameIdx));
332 // FIXME: this spills LR immediately to memory in one step. To do this,
333 // we use R11, which we know cannot be used in the prolog/epilog. This is
335 NewMIs.push_back(BuildMI(TII.get(PPC::MFLR), PPC::R11));
336 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
337 .addReg(PPC::R11, false, false, isKill), FrameIdx));
339 } else if (RC == PPC::G8RCRegisterClass) {
340 if (SrcReg != PPC::LR8) {
341 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD))
342 .addReg(SrcReg, false, false, isKill), FrameIdx));
344 // FIXME: this spills LR immediately to memory in one step. To do this,
345 // we use R11, which we know cannot be used in the prolog/epilog. This is
347 NewMIs.push_back(BuildMI(TII.get(PPC::MFLR8), PPC::X11));
348 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD))
349 .addReg(PPC::X11, false, false, isKill), FrameIdx));
351 } else if (RC == PPC::F8RCRegisterClass) {
352 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFD))
353 .addReg(SrcReg, false, false, isKill), FrameIdx));
354 } else if (RC == PPC::F4RCRegisterClass) {
355 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS))
356 .addReg(SrcReg, false, false, isKill), FrameIdx));
357 } else if (RC == PPC::CRRCRegisterClass) {
358 if (EnablePPCRS) { // FIXME (64-bit): Enable
359 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::SPILL_CR))
360 .addReg(SrcReg, false, false, isKill),
364 // FIXME: We use R0 here, because it isn't available for RA. We need to
365 // store the CR in the low 4-bits of the saved value. First, issue a MFCR
366 // to save all of the CRBits.
367 NewMIs.push_back(BuildMI(TII.get(PPC::MFCR), PPC::R0));
369 // If the saved register wasn't CR0, shift the bits left so that they are
371 if (SrcReg != PPC::CR0) {
372 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
373 // rlwinm r0, r0, ShiftBits, 0, 31.
374 NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0)
375 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
378 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
379 .addReg(PPC::R0, false, false, isKill),
382 } else if (RC == PPC::VRRCRegisterClass) {
383 // We don't have indexed addressing for vector loads. Emit:
387 // FIXME: We use R0 here, because it isn't available for RA.
388 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0),
390 NewMIs.push_back(BuildMI(TII.get(PPC::STVX))
391 .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
393 assert(0 && "Unknown regclass!");
401 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
402 MachineBasicBlock::iterator MI,
403 unsigned SrcReg, bool isKill, int FrameIdx,
404 const TargetRegisterClass *RC) const {
405 SmallVector<MachineInstr*, 4> NewMIs;
407 if (StoreRegToStackSlot(*this, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
408 PPCFunctionInfo *FuncInfo = MBB.getParent()->getInfo<PPCFunctionInfo>();
409 FuncInfo->setSpillsCR();
412 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
413 MBB.insert(MI, NewMIs[i]);
416 void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
418 SmallVectorImpl<MachineOperand> &Addr,
419 const TargetRegisterClass *RC,
420 SmallVectorImpl<MachineInstr*> &NewMIs) const{
421 if (Addr[0].isFrameIndex()) {
422 if (StoreRegToStackSlot(*this, SrcReg, isKill, Addr[0].getIndex(),
424 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
425 FuncInfo->setSpillsCR();
432 if (RC == PPC::GPRCRegisterClass) {
434 } else if (RC == PPC::G8RCRegisterClass) {
436 } else if (RC == PPC::F8RCRegisterClass) {
438 } else if (RC == PPC::F4RCRegisterClass) {
440 } else if (RC == PPC::VRRCRegisterClass) {
443 assert(0 && "Unknown regclass!");
446 MachineInstrBuilder MIB = BuildMI(get(Opc))
447 .addReg(SrcReg, false, false, isKill);
448 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
449 MachineOperand &MO = Addr[i];
451 MIB.addReg(MO.getReg());
452 else if (MO.isImmediate())
453 MIB.addImm(MO.getImm());
455 MIB.addFrameIndex(MO.getIndex());
457 NewMIs.push_back(MIB);
461 static void LoadRegFromStackSlot(const TargetInstrInfo &TII,
462 unsigned DestReg, int FrameIdx,
463 const TargetRegisterClass *RC,
464 SmallVectorImpl<MachineInstr*> &NewMIs) {
465 if (RC == PPC::GPRCRegisterClass) {
466 if (DestReg != PPC::LR) {
467 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), DestReg),
470 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R11),
472 NewMIs.push_back(BuildMI(TII.get(PPC::MTLR)).addReg(PPC::R11));
474 } else if (RC == PPC::G8RCRegisterClass) {
475 if (DestReg != PPC::LR8) {
476 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), DestReg),
479 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), PPC::R11),
481 NewMIs.push_back(BuildMI(TII.get(PPC::MTLR8)).addReg(PPC::R11));
483 } else if (RC == PPC::F8RCRegisterClass) {
484 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFD), DestReg),
486 } else if (RC == PPC::F4RCRegisterClass) {
487 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFS), DestReg),
489 } else if (RC == PPC::CRRCRegisterClass) {
490 // FIXME: We use R0 here, because it isn't available for RA.
491 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R0),
494 // If the reloaded register isn't CR0, shift the bits right so that they are
495 // in the right CR's slot.
496 if (DestReg != PPC::CR0) {
497 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
498 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
499 NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0)
500 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
503 NewMIs.push_back(BuildMI(TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0));
504 } else if (RC == PPC::VRRCRegisterClass) {
505 // We don't have indexed addressing for vector loads. Emit:
509 // FIXME: We use R0 here, because it isn't available for RA.
510 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0),
512 NewMIs.push_back(BuildMI(TII.get(PPC::LVX),DestReg).addReg(PPC::R0)
515 assert(0 && "Unknown regclass!");
521 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
522 MachineBasicBlock::iterator MI,
523 unsigned DestReg, int FrameIdx,
524 const TargetRegisterClass *RC) const {
525 SmallVector<MachineInstr*, 4> NewMIs;
526 LoadRegFromStackSlot(*this, DestReg, FrameIdx, RC, NewMIs);
527 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
528 MBB.insert(MI, NewMIs[i]);
531 void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
532 SmallVectorImpl<MachineOperand> &Addr,
533 const TargetRegisterClass *RC,
534 SmallVectorImpl<MachineInstr*> &NewMIs)const{
535 if (Addr[0].isFrameIndex()) {
536 LoadRegFromStackSlot(*this, DestReg, Addr[0].getIndex(), RC, NewMIs);
541 if (RC == PPC::GPRCRegisterClass) {
542 assert(DestReg != PPC::LR && "Can't handle this yet!");
544 } else if (RC == PPC::G8RCRegisterClass) {
545 assert(DestReg != PPC::LR8 && "Can't handle this yet!");
547 } else if (RC == PPC::F8RCRegisterClass) {
549 } else if (RC == PPC::F4RCRegisterClass) {
551 } else if (RC == PPC::VRRCRegisterClass) {
554 assert(0 && "Unknown regclass!");
557 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
558 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
559 MachineOperand &MO = Addr[i];
561 MIB.addReg(MO.getReg());
562 else if (MO.isImmediate())
563 MIB.addImm(MO.getImm());
565 MIB.addFrameIndex(MO.getIndex());
567 NewMIs.push_back(MIB);
571 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
572 /// copy instructions, turning them into load/store instructions.
573 MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineFunction &MF,
575 SmallVectorImpl<unsigned> &Ops,
576 int FrameIndex) const {
577 if (Ops.size() != 1) return NULL;
579 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
580 // it takes more than one instruction to store it.
581 unsigned Opc = MI->getOpcode();
582 unsigned OpNum = Ops[0];
584 MachineInstr *NewMI = NULL;
585 if ((Opc == PPC::OR &&
586 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
587 if (OpNum == 0) { // move -> store
588 unsigned InReg = MI->getOperand(1).getReg();
589 NewMI = addFrameReference(BuildMI(get(PPC::STW)).addReg(InReg),
591 } else { // move -> load
592 unsigned OutReg = MI->getOperand(0).getReg();
593 NewMI = addFrameReference(BuildMI(get(PPC::LWZ), OutReg),
596 } else if ((Opc == PPC::OR8 &&
597 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
598 if (OpNum == 0) { // move -> store
599 unsigned InReg = MI->getOperand(1).getReg();
600 NewMI = addFrameReference(BuildMI(get(PPC::STD)).addReg(InReg),
602 } else { // move -> load
603 unsigned OutReg = MI->getOperand(0).getReg();
604 NewMI = addFrameReference(BuildMI(get(PPC::LD), OutReg), FrameIndex);
606 } else if (Opc == PPC::FMRD) {
607 if (OpNum == 0) { // move -> store
608 unsigned InReg = MI->getOperand(1).getReg();
609 NewMI = addFrameReference(BuildMI(get(PPC::STFD)).addReg(InReg),
611 } else { // move -> load
612 unsigned OutReg = MI->getOperand(0).getReg();
613 NewMI = addFrameReference(BuildMI(get(PPC::LFD), OutReg), FrameIndex);
615 } else if (Opc == PPC::FMRS) {
616 if (OpNum == 0) { // move -> store
617 unsigned InReg = MI->getOperand(1).getReg();
618 NewMI = addFrameReference(BuildMI(get(PPC::STFS)).addReg(InReg),
620 } else { // move -> load
621 unsigned OutReg = MI->getOperand(0).getReg();
622 NewMI = addFrameReference(BuildMI(get(PPC::LFS), OutReg), FrameIndex);
627 NewMI->copyKillDeadInfo(MI);
631 bool PPCInstrInfo::canFoldMemoryOperand(MachineInstr *MI,
632 SmallVectorImpl<unsigned> &Ops) const {
633 if (Ops.size() != 1) return false;
635 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
636 // it takes more than one instruction to store it.
637 unsigned Opc = MI->getOpcode();
639 if ((Opc == PPC::OR &&
640 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
642 else if ((Opc == PPC::OR8 &&
643 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
645 else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
652 bool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
653 if (MBB.empty()) return false;
655 switch (MBB.back().getOpcode()) {
656 case PPC::BLR: // Return.
657 case PPC::B: // Uncond branch.
658 case PPC::BCTR: // Indirect branch.
660 default: return false;
665 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
666 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
667 // Leave the CR# the same, but invert the condition.
668 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));