1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
16 #include "PPCInstrBuilder.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCHazardRecognizers.h"
20 #include "MCTargetDesc/PPCPredicates.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/TargetRegistry.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/ADT/STLExtras.h"
33 #define GET_INSTRINFO_CTOR
34 #include "PPCGenInstrInfo.inc"
37 extern cl::opt<bool> DisablePPC32RS;
38 extern cl::opt<bool> DisablePPC64RS;
43 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
44 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
45 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
47 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
48 /// this target when scheduling the DAG.
49 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
50 const TargetMachine *TM,
51 const ScheduleDAG *DAG) const {
52 unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
53 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2) {
54 const InstrItineraryData *II = TM->getInstrItineraryData();
55 return new PPCScoreboardHazardRecognizer(II, DAG);
58 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
61 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
62 /// to use for this target when scheduling the DAG.
63 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer(
64 const InstrItineraryData *II,
65 const ScheduleDAG *DAG) const {
66 unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
68 // Most subtargets use a PPC970 recognizer.
69 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2) {
70 const TargetInstrInfo *TII = TM.getInstrInfo();
71 assert(TII && "No InstrInfo?");
73 return new PPCHazardRecognizer970(*TII);
76 return new PPCScoreboardHazardRecognizer(II, DAG);
78 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
79 int &FrameIndex) const {
80 switch (MI->getOpcode()) {
86 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
87 MI->getOperand(2).isFI()) {
88 FrameIndex = MI->getOperand(2).getIndex();
89 return MI->getOperand(0).getReg();
96 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
97 int &FrameIndex) const {
98 switch (MI->getOpcode()) {
104 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
105 MI->getOperand(2).isFI()) {
106 FrameIndex = MI->getOperand(2).getIndex();
107 return MI->getOperand(0).getReg();
114 // commuteInstruction - We can commute rlwimi instructions, but only if the
115 // rotate amt is zero. We also have to munge the immediates a bit.
117 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
118 MachineFunction &MF = *MI->getParent()->getParent();
120 // Normal instructions can be commuted the obvious way.
121 if (MI->getOpcode() != PPC::RLWIMI)
122 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
124 // Cannot commute if it has a non-zero rotate count.
125 if (MI->getOperand(3).getImm() != 0)
128 // If we have a zero rotate count, we have:
130 // Op0 = (Op1 & ~M) | (Op2 & M)
132 // M = mask((ME+1)&31, (MB-1)&31)
133 // Op0 = (Op2 & ~M) | (Op1 & M)
136 unsigned Reg0 = MI->getOperand(0).getReg();
137 unsigned Reg1 = MI->getOperand(1).getReg();
138 unsigned Reg2 = MI->getOperand(2).getReg();
139 bool Reg1IsKill = MI->getOperand(1).isKill();
140 bool Reg2IsKill = MI->getOperand(2).isKill();
141 bool ChangeReg0 = false;
142 // If machine instrs are no longer in two-address forms, update
143 // destination register as well.
145 // Must be two address instruction!
146 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
147 "Expecting a two-address instruction!");
153 unsigned MB = MI->getOperand(4).getImm();
154 unsigned ME = MI->getOperand(5).getImm();
157 // Create a new instruction.
158 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
159 bool Reg0IsDead = MI->getOperand(0).isDead();
160 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
161 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
162 .addReg(Reg2, getKillRegState(Reg2IsKill))
163 .addReg(Reg1, getKillRegState(Reg1IsKill))
165 .addImm((MB-1) & 31);
169 MI->getOperand(0).setReg(Reg2);
170 MI->getOperand(2).setReg(Reg1);
171 MI->getOperand(1).setReg(Reg2);
172 MI->getOperand(2).setIsKill(Reg1IsKill);
173 MI->getOperand(1).setIsKill(Reg2IsKill);
175 // Swap the mask around.
176 MI->getOperand(4).setImm((ME+1) & 31);
177 MI->getOperand(5).setImm((MB-1) & 31);
181 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
182 MachineBasicBlock::iterator MI) const {
184 BuildMI(MBB, MI, DL, get(PPC::NOP));
189 // Note: If the condition register is set to CTR or CTR8 then this is a
190 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
191 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
192 MachineBasicBlock *&FBB,
193 SmallVectorImpl<MachineOperand> &Cond,
194 bool AllowModify) const {
195 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
197 // If the block has no terminators, it just falls into the block after it.
198 MachineBasicBlock::iterator I = MBB.end();
199 if (I == MBB.begin())
202 while (I->isDebugValue()) {
203 if (I == MBB.begin())
207 if (!isUnpredicatedTerminator(I))
210 // Get the last instruction in the block.
211 MachineInstr *LastInst = I;
213 // If there is only one terminator instruction, process it.
214 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
215 if (LastInst->getOpcode() == PPC::B) {
216 if (!LastInst->getOperand(0).isMBB())
218 TBB = LastInst->getOperand(0).getMBB();
220 } else if (LastInst->getOpcode() == PPC::BCC) {
221 if (!LastInst->getOperand(2).isMBB())
223 // Block ends with fall-through condbranch.
224 TBB = LastInst->getOperand(2).getMBB();
225 Cond.push_back(LastInst->getOperand(0));
226 Cond.push_back(LastInst->getOperand(1));
228 } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
229 LastInst->getOpcode() == PPC::BDNZ) {
230 if (!LastInst->getOperand(0).isMBB())
232 TBB = LastInst->getOperand(0).getMBB();
233 Cond.push_back(MachineOperand::CreateImm(1));
234 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
237 } else if (LastInst->getOpcode() == PPC::BDZ8 ||
238 LastInst->getOpcode() == PPC::BDZ) {
239 if (!LastInst->getOperand(0).isMBB())
241 TBB = LastInst->getOperand(0).getMBB();
242 Cond.push_back(MachineOperand::CreateImm(0));
243 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
248 // Otherwise, don't know what this is.
252 // Get the instruction before it if it's a terminator.
253 MachineInstr *SecondLastInst = I;
255 // If there are three terminators, we don't know what sort of block this is.
256 if (SecondLastInst && I != MBB.begin() &&
257 isUnpredicatedTerminator(--I))
260 // If the block ends with PPC::B and PPC:BCC, handle it.
261 if (SecondLastInst->getOpcode() == PPC::BCC &&
262 LastInst->getOpcode() == PPC::B) {
263 if (!SecondLastInst->getOperand(2).isMBB() ||
264 !LastInst->getOperand(0).isMBB())
266 TBB = SecondLastInst->getOperand(2).getMBB();
267 Cond.push_back(SecondLastInst->getOperand(0));
268 Cond.push_back(SecondLastInst->getOperand(1));
269 FBB = LastInst->getOperand(0).getMBB();
271 } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
272 SecondLastInst->getOpcode() == PPC::BDNZ) &&
273 LastInst->getOpcode() == PPC::B) {
274 if (!SecondLastInst->getOperand(0).isMBB() ||
275 !LastInst->getOperand(0).isMBB())
277 TBB = SecondLastInst->getOperand(0).getMBB();
278 Cond.push_back(MachineOperand::CreateImm(1));
279 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
281 FBB = LastInst->getOperand(0).getMBB();
283 } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
284 SecondLastInst->getOpcode() == PPC::BDZ) &&
285 LastInst->getOpcode() == PPC::B) {
286 if (!SecondLastInst->getOperand(0).isMBB() ||
287 !LastInst->getOperand(0).isMBB())
289 TBB = SecondLastInst->getOperand(0).getMBB();
290 Cond.push_back(MachineOperand::CreateImm(0));
291 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
293 FBB = LastInst->getOperand(0).getMBB();
297 // If the block ends with two PPC:Bs, handle it. The second one is not
298 // executed, so remove it.
299 if (SecondLastInst->getOpcode() == PPC::B &&
300 LastInst->getOpcode() == PPC::B) {
301 if (!SecondLastInst->getOperand(0).isMBB())
303 TBB = SecondLastInst->getOperand(0).getMBB();
306 I->eraseFromParent();
310 // Otherwise, can't handle this.
314 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
315 MachineBasicBlock::iterator I = MBB.end();
316 if (I == MBB.begin()) return 0;
318 while (I->isDebugValue()) {
319 if (I == MBB.begin())
323 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
324 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
325 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
328 // Remove the branch.
329 I->eraseFromParent();
333 if (I == MBB.begin()) return 1;
335 if (I->getOpcode() != PPC::BCC &&
336 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
337 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
340 // Remove the branch.
341 I->eraseFromParent();
346 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
347 MachineBasicBlock *FBB,
348 const SmallVectorImpl<MachineOperand> &Cond,
350 // Shouldn't be a fall through.
351 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
352 assert((Cond.size() == 2 || Cond.size() == 0) &&
353 "PPC branch conditions have two components!");
355 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
359 if (Cond.empty()) // Unconditional branch
360 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
361 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
362 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
363 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
364 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
365 else // Conditional branch
366 BuildMI(&MBB, DL, get(PPC::BCC))
367 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
371 // Two-way Conditional Branch.
372 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
373 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
374 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
375 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
377 BuildMI(&MBB, DL, get(PPC::BCC))
378 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
379 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
383 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
384 MachineBasicBlock::iterator I, DebugLoc DL,
385 unsigned DestReg, unsigned SrcReg,
386 bool KillSrc) const {
388 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
390 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
392 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
394 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
396 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
398 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
401 llvm_unreachable("Impossible reg-to-reg copy");
403 const MCInstrDesc &MCID = get(Opc);
404 if (MCID.getNumOperands() == 3)
405 BuildMI(MBB, I, DL, MCID, DestReg)
406 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
408 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
411 // This function returns true if a CR spill is necessary and false otherwise.
413 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
414 unsigned SrcReg, bool isKill,
416 const TargetRegisterClass *RC,
417 SmallVectorImpl<MachineInstr*> &NewMIs) const{
419 if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
420 if (SrcReg != PPC::LR) {
421 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
423 getKillRegState(isKill)),
426 // FIXME: this spills LR immediately to memory in one step. To do this,
427 // we use R11, which we know cannot be used in the prolog/epilog. This is
429 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
430 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
432 getKillRegState(isKill)),
435 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
436 if (SrcReg != PPC::LR8) {
437 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
439 getKillRegState(isKill)),
442 // FIXME: this spills LR immediately to memory in one step. To do this,
443 // we use X11, which we know cannot be used in the prolog/epilog. This is
445 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
446 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
448 getKillRegState(isKill)),
451 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
452 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
454 getKillRegState(isKill)),
456 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
457 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
459 getKillRegState(isKill)),
461 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
462 if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
463 (!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
464 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
466 getKillRegState(isKill)),
470 // FIXME: We need a scatch reg here. The trouble with using R0 is that
471 // it's possible for the stack frame to be so big the save location is
472 // out of range of immediate offsets, necessitating another register.
473 // We hack this on Darwin by reserving R2. It's probably broken on Linux
476 bool is64Bit = TM.getSubtargetImpl()->isPPC64();
477 // We need to store the CR in the low 4-bits of the saved value. First,
478 // issue a MFCR to save all of the CRBits.
479 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
480 (is64Bit ? PPC::X2 : PPC::R2) :
481 (is64Bit ? PPC::X0 : PPC::R0);
482 NewMIs.push_back(BuildMI(MF, DL, get(is64Bit ? PPC::MFCR8pseud :
483 PPC::MFCRpseud), ScratchReg)
484 .addReg(SrcReg, getKillRegState(isKill)));
486 // If the saved register wasn't CR0, shift the bits left so that they are
488 if (SrcReg != PPC::CR0) {
489 unsigned ShiftBits = getPPCRegisterNumbering(SrcReg)*4;
490 // rlwinm scratch, scratch, ShiftBits, 0, 31.
491 NewMIs.push_back(BuildMI(MF, DL, get(is64Bit ? PPC::RLWINM8 :
492 PPC::RLWINM), ScratchReg)
493 .addReg(ScratchReg).addImm(ShiftBits)
494 .addImm(0).addImm(31));
497 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(is64Bit ?
498 PPC::STW8 : PPC::STW))
500 getKillRegState(isKill)),
503 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
504 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
505 // backend currently only uses CR1EQ as an individual bit, this should
506 // not cause any bug. If we need other uses of CR bits, the following
507 // code may be invalid.
509 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
510 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
512 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
513 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
515 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
516 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
518 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
519 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
521 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
522 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
524 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
525 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
527 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
528 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
530 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
531 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
534 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
535 &PPC::CRRCRegClass, NewMIs);
537 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
538 // We don't have indexed addressing for vector loads. Emit:
542 // FIXME: We use R0 here, because it isn't available for RA.
543 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
545 NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
546 .addReg(SrcReg, getKillRegState(isKill))
550 llvm_unreachable("Unknown regclass!");
557 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
558 MachineBasicBlock::iterator MI,
559 unsigned SrcReg, bool isKill, int FrameIdx,
560 const TargetRegisterClass *RC,
561 const TargetRegisterInfo *TRI) const {
562 MachineFunction &MF = *MBB.getParent();
563 SmallVector<MachineInstr*, 4> NewMIs;
565 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
566 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
567 FuncInfo->setSpillsCR();
570 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
571 MBB.insert(MI, NewMIs[i]);
573 const MachineFrameInfo &MFI = *MF.getFrameInfo();
574 MachineMemOperand *MMO =
575 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
576 MachineMemOperand::MOStore,
577 MFI.getObjectSize(FrameIdx),
578 MFI.getObjectAlignment(FrameIdx));
579 NewMIs.back()->addMemOperand(MF, MMO);
583 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
584 unsigned DestReg, int FrameIdx,
585 const TargetRegisterClass *RC,
586 SmallVectorImpl<MachineInstr*> &NewMIs)const{
587 if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
588 if (DestReg != PPC::LR) {
589 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
590 DestReg), FrameIdx));
592 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
593 PPC::R11), FrameIdx));
594 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
596 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
597 if (DestReg != PPC::LR8) {
598 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
601 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
602 PPC::X11), FrameIdx));
603 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::X11));
605 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
606 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
608 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
609 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
611 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
612 if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
613 (!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
614 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
615 get(PPC::RESTORE_CR), DestReg)
619 // FIXME: We need a scatch reg here. The trouble with using R0 is that
620 // it's possible for the stack frame to be so big the save location is
621 // out of range of immediate offsets, necessitating another register.
622 // We hack this on Darwin by reserving R2. It's probably broken on Linux
624 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
626 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
627 ScratchReg), FrameIdx));
629 // If the reloaded register isn't CR0, shift the bits right so that they are
630 // in the right CR's slot.
631 if (DestReg != PPC::CR0) {
632 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4;
633 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
634 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
635 .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
639 NewMIs.push_back(BuildMI(MF, DL, get(TM.getSubtargetImpl()->isPPC64() ?
640 PPC::MTCRF8 : PPC::MTCRF), DestReg)
641 .addReg(ScratchReg));
643 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
646 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
647 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
649 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
650 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
652 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
653 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
655 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
656 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
658 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
659 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
661 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
662 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
664 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
665 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
667 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
668 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
671 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
672 &PPC::CRRCRegClass, NewMIs);
674 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
675 // We don't have indexed addressing for vector loads. Emit:
679 // FIXME: We use R0 here, because it isn't available for RA.
680 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
682 NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
685 llvm_unreachable("Unknown regclass!");
692 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
693 MachineBasicBlock::iterator MI,
694 unsigned DestReg, int FrameIdx,
695 const TargetRegisterClass *RC,
696 const TargetRegisterInfo *TRI) const {
697 MachineFunction &MF = *MBB.getParent();
698 SmallVector<MachineInstr*, 4> NewMIs;
700 if (MI != MBB.end()) DL = MI->getDebugLoc();
701 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs)) {
702 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
703 FuncInfo->setSpillsCR();
705 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
706 MBB.insert(MI, NewMIs[i]);
708 const MachineFrameInfo &MFI = *MF.getFrameInfo();
709 MachineMemOperand *MMO =
710 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
711 MachineMemOperand::MOLoad,
712 MFI.getObjectSize(FrameIdx),
713 MFI.getObjectAlignment(FrameIdx));
714 NewMIs.back()->addMemOperand(MF, MMO);
718 PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
719 int FrameIx, uint64_t Offset,
722 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
723 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
728 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
729 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
730 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
731 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
733 // Leave the CR# the same, but invert the condition.
734 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
738 /// GetInstSize - Return the number of bytes of code the specified
739 /// instruction may be. This returns the maximum number of bytes.
741 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
742 switch (MI->getOpcode()) {
743 case PPC::INLINEASM: { // Inline Asm: Variable size.
744 const MachineFunction *MF = MI->getParent()->getParent();
745 const char *AsmStr = MI->getOperand(0).getSymbolName();
746 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
748 case PPC::PROLOG_LABEL:
753 case PPC::BL8_NOP_ELF:
754 case PPC::BLA8_NOP_ELF:
757 return 4; // PowerPC instructions are all 4 bytes