1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
16 #include "PPCInstrBuilder.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCHazardRecognizers.h"
20 #include "MCTargetDesc/PPCPredicates.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/MC/MCAsmInfo.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/TargetRegistry.h"
29 #include "llvm/Support/raw_ostream.h"
30 #include "llvm/ADT/STLExtras.h"
32 #define GET_INSTRINFO_CTOR
33 #include "PPCGenInstrInfo.inc"
36 extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
37 extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
42 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
43 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
44 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
46 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
47 /// this target when scheduling the DAG.
48 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
49 const TargetMachine *TM,
50 const ScheduleDAG *DAG) const {
51 // Should use subtarget info to pick the right hazard recognizer. For
52 // now, always return a PPC970 recognizer.
53 const TargetInstrInfo *TII = TM->getInstrInfo();
55 assert(TII && "No InstrInfo?");
57 unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
58 if (Directive == PPC::DIR_440) {
59 const InstrItineraryData *II = TM->getInstrItineraryData();
60 return new PPCHazardRecognizer440(II, DAG);
63 // Disable the hazard recognizer for now, as it doesn't support
64 // bottom-up scheduling.
65 //return new PPCHazardRecognizer970(*TII);
66 return new ScheduleHazardRecognizer();
70 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
71 int &FrameIndex) const {
72 switch (MI->getOpcode()) {
78 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
79 MI->getOperand(2).isFI()) {
80 FrameIndex = MI->getOperand(2).getIndex();
81 return MI->getOperand(0).getReg();
88 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
89 int &FrameIndex) const {
90 switch (MI->getOpcode()) {
96 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
97 MI->getOperand(2).isFI()) {
98 FrameIndex = MI->getOperand(2).getIndex();
99 return MI->getOperand(0).getReg();
106 // commuteInstruction - We can commute rlwimi instructions, but only if the
107 // rotate amt is zero. We also have to munge the immediates a bit.
109 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
110 MachineFunction &MF = *MI->getParent()->getParent();
112 // Normal instructions can be commuted the obvious way.
113 if (MI->getOpcode() != PPC::RLWIMI)
114 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
116 // Cannot commute if it has a non-zero rotate count.
117 if (MI->getOperand(3).getImm() != 0)
120 // If we have a zero rotate count, we have:
122 // Op0 = (Op1 & ~M) | (Op2 & M)
124 // M = mask((ME+1)&31, (MB-1)&31)
125 // Op0 = (Op2 & ~M) | (Op1 & M)
128 unsigned Reg0 = MI->getOperand(0).getReg();
129 unsigned Reg1 = MI->getOperand(1).getReg();
130 unsigned Reg2 = MI->getOperand(2).getReg();
131 bool Reg1IsKill = MI->getOperand(1).isKill();
132 bool Reg2IsKill = MI->getOperand(2).isKill();
133 bool ChangeReg0 = false;
134 // If machine instrs are no longer in two-address forms, update
135 // destination register as well.
137 // Must be two address instruction!
138 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
139 "Expecting a two-address instruction!");
145 unsigned MB = MI->getOperand(4).getImm();
146 unsigned ME = MI->getOperand(5).getImm();
149 // Create a new instruction.
150 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
151 bool Reg0IsDead = MI->getOperand(0).isDead();
152 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
153 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
154 .addReg(Reg2, getKillRegState(Reg2IsKill))
155 .addReg(Reg1, getKillRegState(Reg1IsKill))
157 .addImm((MB-1) & 31);
161 MI->getOperand(0).setReg(Reg2);
162 MI->getOperand(2).setReg(Reg1);
163 MI->getOperand(1).setReg(Reg2);
164 MI->getOperand(2).setIsKill(Reg1IsKill);
165 MI->getOperand(1).setIsKill(Reg2IsKill);
167 // Swap the mask around.
168 MI->getOperand(4).setImm((ME+1) & 31);
169 MI->getOperand(5).setImm((MB-1) & 31);
173 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
174 MachineBasicBlock::iterator MI) const {
176 BuildMI(MBB, MI, DL, get(PPC::NOP));
181 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
182 MachineBasicBlock *&FBB,
183 SmallVectorImpl<MachineOperand> &Cond,
184 bool AllowModify) const {
185 // If the block has no terminators, it just falls into the block after it.
186 MachineBasicBlock::iterator I = MBB.end();
187 if (I == MBB.begin())
190 while (I->isDebugValue()) {
191 if (I == MBB.begin())
195 if (!isUnpredicatedTerminator(I))
198 // Get the last instruction in the block.
199 MachineInstr *LastInst = I;
201 // If there is only one terminator instruction, process it.
202 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
203 if (LastInst->getOpcode() == PPC::B) {
204 if (!LastInst->getOperand(0).isMBB())
206 TBB = LastInst->getOperand(0).getMBB();
208 } else if (LastInst->getOpcode() == PPC::BCC) {
209 if (!LastInst->getOperand(2).isMBB())
211 // Block ends with fall-through condbranch.
212 TBB = LastInst->getOperand(2).getMBB();
213 Cond.push_back(LastInst->getOperand(0));
214 Cond.push_back(LastInst->getOperand(1));
217 // Otherwise, don't know what this is.
221 // Get the instruction before it if it's a terminator.
222 MachineInstr *SecondLastInst = I;
224 // If there are three terminators, we don't know what sort of block this is.
225 if (SecondLastInst && I != MBB.begin() &&
226 isUnpredicatedTerminator(--I))
229 // If the block ends with PPC::B and PPC:BCC, handle it.
230 if (SecondLastInst->getOpcode() == PPC::BCC &&
231 LastInst->getOpcode() == PPC::B) {
232 if (!SecondLastInst->getOperand(2).isMBB() ||
233 !LastInst->getOperand(0).isMBB())
235 TBB = SecondLastInst->getOperand(2).getMBB();
236 Cond.push_back(SecondLastInst->getOperand(0));
237 Cond.push_back(SecondLastInst->getOperand(1));
238 FBB = LastInst->getOperand(0).getMBB();
242 // If the block ends with two PPC:Bs, handle it. The second one is not
243 // executed, so remove it.
244 if (SecondLastInst->getOpcode() == PPC::B &&
245 LastInst->getOpcode() == PPC::B) {
246 if (!SecondLastInst->getOperand(0).isMBB())
248 TBB = SecondLastInst->getOperand(0).getMBB();
251 I->eraseFromParent();
255 // Otherwise, can't handle this.
259 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
260 MachineBasicBlock::iterator I = MBB.end();
261 if (I == MBB.begin()) return 0;
263 while (I->isDebugValue()) {
264 if (I == MBB.begin())
268 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
271 // Remove the branch.
272 I->eraseFromParent();
276 if (I == MBB.begin()) return 1;
278 if (I->getOpcode() != PPC::BCC)
281 // Remove the branch.
282 I->eraseFromParent();
287 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
288 MachineBasicBlock *FBB,
289 const SmallVectorImpl<MachineOperand> &Cond,
291 // Shouldn't be a fall through.
292 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
293 assert((Cond.size() == 2 || Cond.size() == 0) &&
294 "PPC branch conditions have two components!");
298 if (Cond.empty()) // Unconditional branch
299 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
300 else // Conditional branch
301 BuildMI(&MBB, DL, get(PPC::BCC))
302 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
306 // Two-way Conditional Branch.
307 BuildMI(&MBB, DL, get(PPC::BCC))
308 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
309 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
313 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
314 MachineBasicBlock::iterator I, DebugLoc DL,
315 unsigned DestReg, unsigned SrcReg,
316 bool KillSrc) const {
318 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
320 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
322 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
324 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
326 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
328 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
331 llvm_unreachable("Impossible reg-to-reg copy");
333 const MCInstrDesc &MCID = get(Opc);
334 if (MCID.getNumOperands() == 3)
335 BuildMI(MBB, I, DL, MCID, DestReg)
336 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
338 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
342 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
343 unsigned SrcReg, bool isKill,
345 const TargetRegisterClass *RC,
346 SmallVectorImpl<MachineInstr*> &NewMIs) const{
348 if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) {
349 if (SrcReg != PPC::LR) {
350 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
352 getKillRegState(isKill)),
355 // FIXME: this spills LR immediately to memory in one step. To do this,
356 // we use R11, which we know cannot be used in the prolog/epilog. This is
358 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
359 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
361 getKillRegState(isKill)),
364 } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) {
365 if (SrcReg != PPC::LR8) {
366 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
368 getKillRegState(isKill)),
371 // FIXME: this spills LR immediately to memory in one step. To do this,
372 // we use R11, which we know cannot be used in the prolog/epilog. This is
374 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
375 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
377 getKillRegState(isKill)),
380 } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) {
381 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
383 getKillRegState(isKill)),
385 } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) {
386 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
388 getKillRegState(isKill)),
390 } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) {
391 if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
392 (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
393 // FIXME (64-bit): Enable
394 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
396 getKillRegState(isKill)),
400 // FIXME: We need a scatch reg here. The trouble with using R0 is that
401 // it's possible for the stack frame to be so big the save location is
402 // out of range of immediate offsets, necessitating another register.
403 // We hack this on Darwin by reserving R2. It's probably broken on Linux
406 // We need to store the CR in the low 4-bits of the saved value. First,
407 // issue a MFCR to save all of the CRBits.
408 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
410 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCRpseud), ScratchReg)
411 .addReg(SrcReg, getKillRegState(isKill)));
413 // If the saved register wasn't CR0, shift the bits left so that they are
415 if (SrcReg != PPC::CR0) {
416 unsigned ShiftBits = getPPCRegisterNumbering(SrcReg)*4;
417 // rlwinm scratch, scratch, ShiftBits, 0, 31.
418 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
419 .addReg(ScratchReg).addImm(ShiftBits)
420 .addImm(0).addImm(31));
423 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
425 getKillRegState(isKill)),
428 } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) {
429 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
430 // backend currently only uses CR1EQ as an individual bit, this should
431 // not cause any bug. If we need other uses of CR bits, the following
432 // code may be invalid.
434 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
435 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
437 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
438 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
440 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
441 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
443 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
444 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
446 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
447 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
449 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
450 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
452 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
453 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
455 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
456 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
459 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
460 PPC::CRRCRegisterClass, NewMIs);
462 } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) {
463 // We don't have indexed addressing for vector loads. Emit:
467 // FIXME: We use R0 here, because it isn't available for RA.
468 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
470 NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
471 .addReg(SrcReg, getKillRegState(isKill))
475 llvm_unreachable("Unknown regclass!");
482 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
483 MachineBasicBlock::iterator MI,
484 unsigned SrcReg, bool isKill, int FrameIdx,
485 const TargetRegisterClass *RC,
486 const TargetRegisterInfo *TRI) const {
487 MachineFunction &MF = *MBB.getParent();
488 SmallVector<MachineInstr*, 4> NewMIs;
490 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
491 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
492 FuncInfo->setSpillsCR();
495 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
496 MBB.insert(MI, NewMIs[i]);
498 const MachineFrameInfo &MFI = *MF.getFrameInfo();
499 MachineMemOperand *MMO =
500 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
501 MachineMemOperand::MOStore,
502 MFI.getObjectSize(FrameIdx),
503 MFI.getObjectAlignment(FrameIdx));
504 NewMIs.back()->addMemOperand(MF, MMO);
508 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
509 unsigned DestReg, int FrameIdx,
510 const TargetRegisterClass *RC,
511 SmallVectorImpl<MachineInstr*> &NewMIs)const{
512 if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) {
513 if (DestReg != PPC::LR) {
514 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
515 DestReg), FrameIdx));
517 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
518 PPC::R11), FrameIdx));
519 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
521 } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) {
522 if (DestReg != PPC::LR8) {
523 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
526 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
527 PPC::R11), FrameIdx));
528 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
530 } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) {
531 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
533 } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) {
534 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
536 } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) {
537 // FIXME: We need a scatch reg here. The trouble with using R0 is that
538 // it's possible for the stack frame to be so big the save location is
539 // out of range of immediate offsets, necessitating another register.
540 // We hack this on Darwin by reserving R2. It's probably broken on Linux
542 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
544 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
545 ScratchReg), FrameIdx));
547 // If the reloaded register isn't CR0, shift the bits right so that they are
548 // in the right CR's slot.
549 if (DestReg != PPC::CR0) {
550 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4;
551 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
552 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
553 .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
557 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg)
558 .addReg(ScratchReg));
559 } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) {
562 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
563 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
565 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
566 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
568 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
569 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
571 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
572 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
574 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
575 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
577 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
578 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
580 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
581 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
583 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
584 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
587 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
588 PPC::CRRCRegisterClass, NewMIs);
590 } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) {
591 // We don't have indexed addressing for vector loads. Emit:
595 // FIXME: We use R0 here, because it isn't available for RA.
596 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
598 NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
601 llvm_unreachable("Unknown regclass!");
606 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
607 MachineBasicBlock::iterator MI,
608 unsigned DestReg, int FrameIdx,
609 const TargetRegisterClass *RC,
610 const TargetRegisterInfo *TRI) const {
611 MachineFunction &MF = *MBB.getParent();
612 SmallVector<MachineInstr*, 4> NewMIs;
614 if (MI != MBB.end()) DL = MI->getDebugLoc();
615 LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
616 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
617 MBB.insert(MI, NewMIs[i]);
619 const MachineFrameInfo &MFI = *MF.getFrameInfo();
620 MachineMemOperand *MMO =
621 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
622 MachineMemOperand::MOLoad,
623 MFI.getObjectSize(FrameIdx),
624 MFI.getObjectAlignment(FrameIdx));
625 NewMIs.back()->addMemOperand(MF, MMO);
629 PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
630 int FrameIx, uint64_t Offset,
633 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
634 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
639 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
640 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
641 // Leave the CR# the same, but invert the condition.
642 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
646 /// GetInstSize - Return the number of bytes of code the specified
647 /// instruction may be. This returns the maximum number of bytes.
649 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
650 switch (MI->getOpcode()) {
651 case PPC::INLINEASM: { // Inline Asm: Variable size.
652 const MachineFunction *MF = MI->getParent()->getParent();
653 const char *AsmStr = MI->getOperand(0).getSymbolName();
654 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
656 case PPC::PROLOG_LABEL:
662 return 4; // PowerPC instructions are all 4 bytes