1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineMemOperand.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/PseudoSourceValue.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/TargetRegistry.h"
33 #include "llvm/Support/raw_ostream.h"
35 #define GET_INSTRMAP_INFO
36 #define GET_INSTRINFO_CTOR_DTOR
37 #include "PPCGenInstrInfo.inc"
42 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
43 cl::desc("Disable analysis for CTR loops"));
45 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
46 cl::desc("Disable compare instruction optimization"), cl::Hidden);
48 // Pin the vtable to this file.
49 void PPCInstrInfo::anchor() {}
51 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
52 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
53 TM(tm), RI(*TM.getSubtargetImpl()) {}
55 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
56 /// this target when scheduling the DAG.
57 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
58 const TargetMachine *TM,
59 const ScheduleDAG *DAG) const {
60 unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
61 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
62 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
63 const InstrItineraryData *II = TM->getInstrItineraryData();
64 return new ScoreboardHazardRecognizer(II, DAG);
67 return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG);
70 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
71 /// to use for this target when scheduling the DAG.
72 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer(
73 const InstrItineraryData *II,
74 const ScheduleDAG *DAG) const {
75 unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
77 if (Directive == PPC::DIR_PWR7)
78 return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
80 // Most subtargets use a PPC970 recognizer.
81 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
82 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
83 assert(TM.getInstrInfo() && "No InstrInfo?");
85 return new PPCHazardRecognizer970(TM);
88 return new ScoreboardHazardRecognizer(II, DAG);
92 int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
93 const MachineInstr *DefMI, unsigned DefIdx,
94 const MachineInstr *UseMI,
95 unsigned UseIdx) const {
96 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
99 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
100 unsigned Reg = DefMO.getReg();
102 const TargetRegisterInfo *TRI = &getRegisterInfo();
104 if (TRI->isVirtualRegister(Reg)) {
105 const MachineRegisterInfo *MRI =
106 &DefMI->getParent()->getParent()->getRegInfo();
107 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
108 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
110 IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
111 PPC::CRBITRCRegClass.contains(Reg);
114 if (UseMI->isBranch() && IsRegCR) {
116 Latency = getInstrLatency(ItinData, DefMI);
118 // On some cores, there is an additional delay between writing to a condition
119 // register, and using it from a branch.
120 unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
141 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
142 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
143 unsigned &SrcReg, unsigned &DstReg,
144 unsigned &SubIdx) const {
145 switch (MI.getOpcode()) {
146 default: return false;
148 case PPC::EXTSW_32_64:
149 SrcReg = MI.getOperand(1).getReg();
150 DstReg = MI.getOperand(0).getReg();
151 SubIdx = PPC::sub_32;
156 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
157 int &FrameIndex) const {
158 // Note: This list must be kept consistent with LoadRegFromStackSlot.
159 switch (MI->getOpcode()) {
165 case PPC::RESTORE_CR:
166 case PPC::RESTORE_CRBIT:
169 case PPC::RESTORE_VRSAVE:
170 // Check for the operands added by addFrameReference (the immediate is the
171 // offset which defaults to 0).
172 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
173 MI->getOperand(2).isFI()) {
174 FrameIndex = MI->getOperand(2).getIndex();
175 return MI->getOperand(0).getReg();
182 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
183 int &FrameIndex) const {
184 // Note: This list must be kept consistent with StoreRegToStackSlot.
185 switch (MI->getOpcode()) {
192 case PPC::SPILL_CRBIT:
195 case PPC::SPILL_VRSAVE:
196 // Check for the operands added by addFrameReference (the immediate is the
197 // offset which defaults to 0).
198 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
199 MI->getOperand(2).isFI()) {
200 FrameIndex = MI->getOperand(2).getIndex();
201 return MI->getOperand(0).getReg();
208 // commuteInstruction - We can commute rlwimi instructions, but only if the
209 // rotate amt is zero. We also have to munge the immediates a bit.
211 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
212 MachineFunction &MF = *MI->getParent()->getParent();
214 // Normal instructions can be commuted the obvious way.
215 if (MI->getOpcode() != PPC::RLWIMI &&
216 MI->getOpcode() != PPC::RLWIMIo &&
217 MI->getOpcode() != PPC::RLWIMI8 &&
218 MI->getOpcode() != PPC::RLWIMI8o)
219 return TargetInstrInfo::commuteInstruction(MI, NewMI);
221 // Cannot commute if it has a non-zero rotate count.
222 if (MI->getOperand(3).getImm() != 0)
225 // If we have a zero rotate count, we have:
227 // Op0 = (Op1 & ~M) | (Op2 & M)
229 // M = mask((ME+1)&31, (MB-1)&31)
230 // Op0 = (Op2 & ~M) | (Op1 & M)
233 unsigned Reg0 = MI->getOperand(0).getReg();
234 unsigned Reg1 = MI->getOperand(1).getReg();
235 unsigned Reg2 = MI->getOperand(2).getReg();
236 unsigned SubReg1 = MI->getOperand(1).getSubReg();
237 unsigned SubReg2 = MI->getOperand(2).getSubReg();
238 bool Reg1IsKill = MI->getOperand(1).isKill();
239 bool Reg2IsKill = MI->getOperand(2).isKill();
240 bool ChangeReg0 = false;
241 // If machine instrs are no longer in two-address forms, update
242 // destination register as well.
244 // Must be two address instruction!
245 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
246 "Expecting a two-address instruction!");
247 assert(MI->getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
253 unsigned MB = MI->getOperand(4).getImm();
254 unsigned ME = MI->getOperand(5).getImm();
257 // Create a new instruction.
258 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
259 bool Reg0IsDead = MI->getOperand(0).isDead();
260 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
261 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
262 .addReg(Reg2, getKillRegState(Reg2IsKill))
263 .addReg(Reg1, getKillRegState(Reg1IsKill))
265 .addImm((MB-1) & 31);
269 MI->getOperand(0).setReg(Reg2);
270 MI->getOperand(0).setSubReg(SubReg2);
272 MI->getOperand(2).setReg(Reg1);
273 MI->getOperand(1).setReg(Reg2);
274 MI->getOperand(2).setSubReg(SubReg1);
275 MI->getOperand(1).setSubReg(SubReg2);
276 MI->getOperand(2).setIsKill(Reg1IsKill);
277 MI->getOperand(1).setIsKill(Reg2IsKill);
279 // Swap the mask around.
280 MI->getOperand(4).setImm((ME+1) & 31);
281 MI->getOperand(5).setImm((MB-1) & 31);
285 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
286 MachineBasicBlock::iterator MI) const {
287 // This function is used for scheduling, and the nop wanted here is the type
288 // that terminates dispatch groups on the POWER cores.
289 unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
292 default: Opcode = PPC::NOP; break;
293 case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
294 case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
298 BuildMI(MBB, MI, DL, get(Opcode));
302 // Note: If the condition register is set to CTR or CTR8 then this is a
303 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
304 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
305 MachineBasicBlock *&FBB,
306 SmallVectorImpl<MachineOperand> &Cond,
307 bool AllowModify) const {
308 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
310 // If the block has no terminators, it just falls into the block after it.
311 MachineBasicBlock::iterator I = MBB.end();
312 if (I == MBB.begin())
315 while (I->isDebugValue()) {
316 if (I == MBB.begin())
320 if (!isUnpredicatedTerminator(I))
323 // Get the last instruction in the block.
324 MachineInstr *LastInst = I;
326 // If there is only one terminator instruction, process it.
327 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
328 if (LastInst->getOpcode() == PPC::B) {
329 if (!LastInst->getOperand(0).isMBB())
331 TBB = LastInst->getOperand(0).getMBB();
333 } else if (LastInst->getOpcode() == PPC::BCC) {
334 if (!LastInst->getOperand(2).isMBB())
336 // Block ends with fall-through condbranch.
337 TBB = LastInst->getOperand(2).getMBB();
338 Cond.push_back(LastInst->getOperand(0));
339 Cond.push_back(LastInst->getOperand(1));
341 } else if (LastInst->getOpcode() == PPC::BC) {
342 if (!LastInst->getOperand(1).isMBB())
344 // Block ends with fall-through condbranch.
345 TBB = LastInst->getOperand(1).getMBB();
346 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
347 Cond.push_back(LastInst->getOperand(0));
349 } else if (LastInst->getOpcode() == PPC::BCn) {
350 if (!LastInst->getOperand(1).isMBB())
352 // Block ends with fall-through condbranch.
353 TBB = LastInst->getOperand(1).getMBB();
354 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
355 Cond.push_back(LastInst->getOperand(0));
357 } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
358 LastInst->getOpcode() == PPC::BDNZ) {
359 if (!LastInst->getOperand(0).isMBB())
361 if (DisableCTRLoopAnal)
363 TBB = LastInst->getOperand(0).getMBB();
364 Cond.push_back(MachineOperand::CreateImm(1));
365 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
368 } else if (LastInst->getOpcode() == PPC::BDZ8 ||
369 LastInst->getOpcode() == PPC::BDZ) {
370 if (!LastInst->getOperand(0).isMBB())
372 if (DisableCTRLoopAnal)
374 TBB = LastInst->getOperand(0).getMBB();
375 Cond.push_back(MachineOperand::CreateImm(0));
376 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
381 // Otherwise, don't know what this is.
385 // Get the instruction before it if it's a terminator.
386 MachineInstr *SecondLastInst = I;
388 // If there are three terminators, we don't know what sort of block this is.
389 if (SecondLastInst && I != MBB.begin() &&
390 isUnpredicatedTerminator(--I))
393 // If the block ends with PPC::B and PPC:BCC, handle it.
394 if (SecondLastInst->getOpcode() == PPC::BCC &&
395 LastInst->getOpcode() == PPC::B) {
396 if (!SecondLastInst->getOperand(2).isMBB() ||
397 !LastInst->getOperand(0).isMBB())
399 TBB = SecondLastInst->getOperand(2).getMBB();
400 Cond.push_back(SecondLastInst->getOperand(0));
401 Cond.push_back(SecondLastInst->getOperand(1));
402 FBB = LastInst->getOperand(0).getMBB();
404 } else if (SecondLastInst->getOpcode() == PPC::BC &&
405 LastInst->getOpcode() == PPC::B) {
406 if (!SecondLastInst->getOperand(1).isMBB() ||
407 !LastInst->getOperand(0).isMBB())
409 TBB = SecondLastInst->getOperand(1).getMBB();
410 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
411 Cond.push_back(SecondLastInst->getOperand(0));
412 FBB = LastInst->getOperand(0).getMBB();
414 } else if (SecondLastInst->getOpcode() == PPC::BCn &&
415 LastInst->getOpcode() == PPC::B) {
416 if (!SecondLastInst->getOperand(1).isMBB() ||
417 !LastInst->getOperand(0).isMBB())
419 TBB = SecondLastInst->getOperand(1).getMBB();
420 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
421 Cond.push_back(SecondLastInst->getOperand(0));
422 FBB = LastInst->getOperand(0).getMBB();
424 } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
425 SecondLastInst->getOpcode() == PPC::BDNZ) &&
426 LastInst->getOpcode() == PPC::B) {
427 if (!SecondLastInst->getOperand(0).isMBB() ||
428 !LastInst->getOperand(0).isMBB())
430 if (DisableCTRLoopAnal)
432 TBB = SecondLastInst->getOperand(0).getMBB();
433 Cond.push_back(MachineOperand::CreateImm(1));
434 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
436 FBB = LastInst->getOperand(0).getMBB();
438 } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
439 SecondLastInst->getOpcode() == PPC::BDZ) &&
440 LastInst->getOpcode() == PPC::B) {
441 if (!SecondLastInst->getOperand(0).isMBB() ||
442 !LastInst->getOperand(0).isMBB())
444 if (DisableCTRLoopAnal)
446 TBB = SecondLastInst->getOperand(0).getMBB();
447 Cond.push_back(MachineOperand::CreateImm(0));
448 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
450 FBB = LastInst->getOperand(0).getMBB();
454 // If the block ends with two PPC:Bs, handle it. The second one is not
455 // executed, so remove it.
456 if (SecondLastInst->getOpcode() == PPC::B &&
457 LastInst->getOpcode() == PPC::B) {
458 if (!SecondLastInst->getOperand(0).isMBB())
460 TBB = SecondLastInst->getOperand(0).getMBB();
463 I->eraseFromParent();
467 // Otherwise, can't handle this.
471 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
472 MachineBasicBlock::iterator I = MBB.end();
473 if (I == MBB.begin()) return 0;
475 while (I->isDebugValue()) {
476 if (I == MBB.begin())
480 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
481 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
482 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
483 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
486 // Remove the branch.
487 I->eraseFromParent();
491 if (I == MBB.begin()) return 1;
493 if (I->getOpcode() != PPC::BCC &&
494 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
495 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
496 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
499 // Remove the branch.
500 I->eraseFromParent();
505 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
506 MachineBasicBlock *FBB,
507 const SmallVectorImpl<MachineOperand> &Cond,
509 // Shouldn't be a fall through.
510 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
511 assert((Cond.size() == 2 || Cond.size() == 0) &&
512 "PPC branch conditions have two components!");
514 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
518 if (Cond.empty()) // Unconditional branch
519 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
520 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
521 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
522 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
523 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
524 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
525 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
526 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
527 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
528 else // Conditional branch
529 BuildMI(&MBB, DL, get(PPC::BCC))
530 .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
534 // Two-way Conditional Branch.
535 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
536 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
537 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
538 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
539 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
540 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
541 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
542 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
544 BuildMI(&MBB, DL, get(PPC::BCC))
545 .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
546 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
551 bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
552 const SmallVectorImpl<MachineOperand> &Cond,
553 unsigned TrueReg, unsigned FalseReg,
554 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
555 if (!TM.getSubtargetImpl()->hasISEL())
558 if (Cond.size() != 2)
561 // If this is really a bdnz-like condition, then it cannot be turned into a
563 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
566 // Check register classes.
567 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
568 const TargetRegisterClass *RC =
569 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
573 // isel is for regular integer GPRs only.
574 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
575 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
576 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
577 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
580 // FIXME: These numbers are for the A2, how well they work for other cores is
581 // an open question. On the A2, the isel instruction has a 2-cycle latency
582 // but single-cycle throughput. These numbers are used in combination with
583 // the MispredictPenalty setting from the active SchedMachineModel.
591 void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
592 MachineBasicBlock::iterator MI, DebugLoc dl,
594 const SmallVectorImpl<MachineOperand> &Cond,
595 unsigned TrueReg, unsigned FalseReg) const {
596 assert(Cond.size() == 2 &&
597 "PPC branch conditions have two components!");
599 assert(TM.getSubtargetImpl()->hasISEL() &&
600 "Cannot insert select on target without ISEL support");
602 // Get the register classes.
603 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
604 const TargetRegisterClass *RC =
605 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
606 assert(RC && "TrueReg and FalseReg must have overlapping register classes");
608 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
609 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
611 PPC::GPRCRegClass.hasSubClassEq(RC) ||
612 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
613 "isel is for regular integer GPRs only");
615 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
616 unsigned SelectPred = Cond[0].getImm();
620 switch (SelectPred) {
621 default: llvm_unreachable("invalid predicate for isel");
622 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break;
623 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break;
624 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break;
625 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break;
626 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break;
627 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break;
628 case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break;
629 case PPC::PRED_NU: SubIdx = PPC::sub_un; SwapOps = true; break;
630 case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
631 case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
634 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
635 SecondReg = SwapOps ? TrueReg : FalseReg;
637 // The first input register of isel cannot be r0. If it is a member
638 // of a register class that can be r0, then copy it first (the
639 // register allocator should eliminate the copy).
640 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
641 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
642 const TargetRegisterClass *FirstRC =
643 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
644 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
645 unsigned OldFirstReg = FirstReg;
646 FirstReg = MRI.createVirtualRegister(FirstRC);
647 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
648 .addReg(OldFirstReg);
651 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
652 .addReg(FirstReg).addReg(SecondReg)
653 .addReg(Cond[1].getReg(), 0, SubIdx);
656 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
657 MachineBasicBlock::iterator I, DebugLoc DL,
658 unsigned DestReg, unsigned SrcReg,
659 bool KillSrc) const {
660 // We can end up with self copies and similar things as a result of VSX copy
661 // legalization. Promote (or just ignore) them here.
662 const TargetRegisterInfo *TRI = &getRegisterInfo();
663 if (PPC::F8RCRegClass.contains(DestReg) &&
664 PPC::VSLRCRegClass.contains(SrcReg)) {
666 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
668 if (SrcReg == SuperReg)
672 } else if (PPC::VRRCRegClass.contains(DestReg) &&
673 PPC::VSHRCRegClass.contains(SrcReg)) {
675 TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass);
677 if (SrcReg == SuperReg)
681 } else if (PPC::F8RCRegClass.contains(SrcReg) &&
682 PPC::VSLRCRegClass.contains(DestReg)) {
684 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
686 if (DestReg == SuperReg)
690 } else if (PPC::VRRCRegClass.contains(SrcReg) &&
691 PPC::VSHRCRegClass.contains(DestReg)) {
693 TRI->getMatchingSuperReg(SrcReg, PPC::sub_128, &PPC::VSRCRegClass);
695 if (DestReg == SuperReg)
702 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
704 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
706 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
708 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
710 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
712 else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
713 // There are two different ways this can be done:
714 // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
715 // issue in VSU pipeline 0.
716 // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
717 // can go to either pipeline.
718 // We'll always use xxlor here, because in practically all cases where
719 // copies are generated, they are close enough to some use that the
720 // lower-latency form is preferable.
722 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
725 llvm_unreachable("Impossible reg-to-reg copy");
727 const MCInstrDesc &MCID = get(Opc);
728 if (MCID.getNumOperands() == 3)
729 BuildMI(MBB, I, DL, MCID, DestReg)
730 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
732 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
735 // This function returns true if a CR spill is necessary and false otherwise.
737 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
738 unsigned SrcReg, bool isKill,
740 const TargetRegisterClass *RC,
741 SmallVectorImpl<MachineInstr*> &NewMIs,
742 bool &NonRI, bool &SpillsVRS) const{
743 // Note: If additional store instructions are added here,
744 // update isStoreToStackSlot.
747 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
748 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
749 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
751 getKillRegState(isKill)),
753 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
754 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
755 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
757 getKillRegState(isKill)),
759 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
760 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
762 getKillRegState(isKill)),
764 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
765 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
767 getKillRegState(isKill)),
769 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
770 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
772 getKillRegState(isKill)),
775 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
776 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT))
778 getKillRegState(isKill)),
781 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
782 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
784 getKillRegState(isKill)),
787 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
788 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXVD2X))
790 getKillRegState(isKill)),
793 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
794 assert(TM.getSubtargetImpl()->isDarwin() &&
795 "VRSAVE only needs spill/restore on Darwin");
796 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
798 getKillRegState(isKill)),
802 llvm_unreachable("Unknown regclass!");
809 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
810 MachineBasicBlock::iterator MI,
811 unsigned SrcReg, bool isKill, int FrameIdx,
812 const TargetRegisterClass *RC,
813 const TargetRegisterInfo *TRI) const {
814 MachineFunction &MF = *MBB.getParent();
815 SmallVector<MachineInstr*, 4> NewMIs;
817 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
818 FuncInfo->setHasSpills();
820 bool NonRI = false, SpillsVRS = false;
821 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
823 FuncInfo->setSpillsCR();
826 FuncInfo->setSpillsVRSAVE();
829 FuncInfo->setHasNonRISpills();
831 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
832 MBB.insert(MI, NewMIs[i]);
834 const MachineFrameInfo &MFI = *MF.getFrameInfo();
835 MachineMemOperand *MMO =
836 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
837 MachineMemOperand::MOStore,
838 MFI.getObjectSize(FrameIdx),
839 MFI.getObjectAlignment(FrameIdx));
840 NewMIs.back()->addMemOperand(MF, MMO);
844 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
845 unsigned DestReg, int FrameIdx,
846 const TargetRegisterClass *RC,
847 SmallVectorImpl<MachineInstr*> &NewMIs,
848 bool &NonRI, bool &SpillsVRS) const{
849 // Note: If additional load instructions are added here,
850 // update isLoadFromStackSlot.
852 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
853 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
854 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
855 DestReg), FrameIdx));
856 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
857 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
858 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
860 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
861 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
863 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
864 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
866 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
867 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
868 get(PPC::RESTORE_CR), DestReg),
871 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
872 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
873 get(PPC::RESTORE_CRBIT), DestReg),
876 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
877 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
880 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
881 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXVD2X), DestReg),
884 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
885 assert(TM.getSubtargetImpl()->isDarwin() &&
886 "VRSAVE only needs spill/restore on Darwin");
887 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
888 get(PPC::RESTORE_VRSAVE),
893 llvm_unreachable("Unknown regclass!");
900 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
901 MachineBasicBlock::iterator MI,
902 unsigned DestReg, int FrameIdx,
903 const TargetRegisterClass *RC,
904 const TargetRegisterInfo *TRI) const {
905 MachineFunction &MF = *MBB.getParent();
906 SmallVector<MachineInstr*, 4> NewMIs;
908 if (MI != MBB.end()) DL = MI->getDebugLoc();
910 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
911 FuncInfo->setHasSpills();
913 bool NonRI = false, SpillsVRS = false;
914 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
916 FuncInfo->setSpillsCR();
919 FuncInfo->setSpillsVRSAVE();
922 FuncInfo->setHasNonRISpills();
924 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
925 MBB.insert(MI, NewMIs[i]);
927 const MachineFrameInfo &MFI = *MF.getFrameInfo();
928 MachineMemOperand *MMO =
929 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
930 MachineMemOperand::MOLoad,
931 MFI.getObjectSize(FrameIdx),
932 MFI.getObjectAlignment(FrameIdx));
933 NewMIs.back()->addMemOperand(MF, MMO);
937 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
938 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
939 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
940 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
942 // Leave the CR# the same, but invert the condition.
943 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
947 bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
948 unsigned Reg, MachineRegisterInfo *MRI) const {
949 // For some instructions, it is legal to fold ZERO into the RA register field.
950 // A zero immediate should always be loaded with a single li.
951 unsigned DefOpc = DefMI->getOpcode();
952 if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
954 if (!DefMI->getOperand(1).isImm())
956 if (DefMI->getOperand(1).getImm() != 0)
959 // Note that we cannot here invert the arguments of an isel in order to fold
960 // a ZERO into what is presented as the second argument. All we have here
961 // is the condition bit, and that might come from a CR-logical bit operation.
963 const MCInstrDesc &UseMCID = UseMI->getDesc();
965 // Only fold into real machine instructions.
966 if (UseMCID.isPseudo())
970 for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx)
971 if (UseMI->getOperand(UseIdx).isReg() &&
972 UseMI->getOperand(UseIdx).getReg() == Reg)
975 assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI");
976 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
978 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
980 // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
981 // register (which might also be specified as a pointer class kind).
982 if (UseInfo->isLookupPtrRegClass()) {
983 if (UseInfo->RegClass /* Kind */ != 1)
986 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
987 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
991 // Make sure this is not tied to an output register (or otherwise
992 // constrained). This is true for ST?UX registers, for example, which
993 // are tied to their output registers.
994 if (UseInfo->Constraints != 0)
998 if (UseInfo->isLookupPtrRegClass()) {
999 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
1000 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1002 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1003 PPC::ZERO8 : PPC::ZERO;
1006 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1007 UseMI->getOperand(UseIdx).setReg(ZeroReg);
1010 DefMI->eraseFromParent();
1015 static bool MBBDefinesCTR(MachineBasicBlock &MBB) {
1016 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1018 if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1023 // We should make sure that, if we're going to predicate both sides of a
1024 // condition (a diamond), that both sides don't define the counter register. We
1025 // can predicate counter-decrement-based branches, but while that predicates
1026 // the branching, it does not predicate the counter decrement. If we tried to
1027 // merge the triangle into one predicated block, we'd decrement the counter
1029 bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
1030 unsigned NumT, unsigned ExtraT,
1031 MachineBasicBlock &FMBB,
1032 unsigned NumF, unsigned ExtraF,
1033 const BranchProbability &Probability) const {
1034 return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1038 bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const {
1039 // The predicated branches are identified by their type, not really by the
1040 // explicit presence of a predicate. Furthermore, some of them can be
1041 // predicated more than once. Because if conversion won't try to predicate
1042 // any instruction which already claims to be predicated (by returning true
1043 // here), always return false. In doing so, we let isPredicable() be the
1044 // final word on whether not the instruction can be (further) predicated.
1049 bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1050 if (!MI->isTerminator())
1053 // Conditional branch is a special case.
1054 if (MI->isBranch() && !MI->isBarrier())
1057 return !isPredicated(MI);
1060 bool PPCInstrInfo::PredicateInstruction(
1062 const SmallVectorImpl<MachineOperand> &Pred) const {
1063 unsigned OpC = MI->getOpcode();
1064 if (OpC == PPC::BLR) {
1065 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1066 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
1067 MI->setDesc(get(Pred[0].getImm() ?
1068 (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) :
1069 (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1070 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1071 MI->setDesc(get(PPC::BCLR));
1072 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1073 .addReg(Pred[1].getReg());
1074 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1075 MI->setDesc(get(PPC::BCLRn));
1076 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1077 .addReg(Pred[1].getReg());
1079 MI->setDesc(get(PPC::BCCLR));
1080 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1081 .addImm(Pred[0].getImm())
1082 .addReg(Pred[1].getReg());
1086 } else if (OpC == PPC::B) {
1087 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1088 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
1089 MI->setDesc(get(Pred[0].getImm() ?
1090 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1091 (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1092 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1093 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1094 MI->RemoveOperand(0);
1096 MI->setDesc(get(PPC::BC));
1097 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1098 .addReg(Pred[1].getReg())
1100 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1101 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1102 MI->RemoveOperand(0);
1104 MI->setDesc(get(PPC::BCn));
1105 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1106 .addReg(Pred[1].getReg())
1109 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1110 MI->RemoveOperand(0);
1112 MI->setDesc(get(PPC::BCC));
1113 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1114 .addImm(Pred[0].getImm())
1115 .addReg(Pred[1].getReg())
1120 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
1121 OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
1122 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1123 llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1125 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1126 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
1128 if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1129 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) :
1130 (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1131 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1132 .addReg(Pred[1].getReg());
1134 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1135 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) :
1136 (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1137 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1138 .addReg(Pred[1].getReg());
1142 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) :
1143 (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1144 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1145 .addImm(Pred[0].getImm())
1146 .addReg(Pred[1].getReg());
1153 bool PPCInstrInfo::SubsumesPredicate(
1154 const SmallVectorImpl<MachineOperand> &Pred1,
1155 const SmallVectorImpl<MachineOperand> &Pred2) const {
1156 assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1157 assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1159 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1161 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1164 // P1 can only subsume P2 if they test the same condition register.
1165 if (Pred1[1].getReg() != Pred2[1].getReg())
1168 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1169 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1174 // Does P1 subsume P2, e.g. GE subsumes GT.
1175 if (P1 == PPC::PRED_LE &&
1176 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1178 if (P1 == PPC::PRED_GE &&
1179 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1185 bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI,
1186 std::vector<MachineOperand> &Pred) const {
1187 // Note: At the present time, the contents of Pred from this function is
1188 // unused by IfConversion. This implementation follows ARM by pushing the
1189 // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1190 // predicate, instructions defining CTR or CTR8 are also included as
1191 // predicate-defining instructions.
1193 const TargetRegisterClass *RCs[] =
1194 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1195 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1198 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1199 const MachineOperand &MO = MI->getOperand(i);
1200 for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1201 const TargetRegisterClass *RC = RCs[c];
1203 if (MO.isDef() && RC->contains(MO.getReg())) {
1207 } else if (MO.isRegMask()) {
1208 for (TargetRegisterClass::iterator I = RC->begin(),
1209 IE = RC->end(); I != IE; ++I)
1210 if (MO.clobbersPhysReg(*I)) {
1221 bool PPCInstrInfo::isPredicable(MachineInstr *MI) const {
1222 unsigned OpC = MI->getOpcode();
1236 bool PPCInstrInfo::analyzeCompare(const MachineInstr *MI,
1237 unsigned &SrcReg, unsigned &SrcReg2,
1238 int &Mask, int &Value) const {
1239 unsigned Opc = MI->getOpcode();
1242 default: return false;
1247 SrcReg = MI->getOperand(1).getReg();
1249 Value = MI->getOperand(2).getImm();
1258 SrcReg = MI->getOperand(1).getReg();
1259 SrcReg2 = MI->getOperand(2).getReg();
1264 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr,
1265 unsigned SrcReg, unsigned SrcReg2,
1266 int Mask, int Value,
1267 const MachineRegisterInfo *MRI) const {
1271 int OpC = CmpInstr->getOpcode();
1272 unsigned CRReg = CmpInstr->getOperand(0).getReg();
1274 // FP record forms set CR1 based on the execption status bits, not a
1275 // comparison with zero.
1276 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1279 // The record forms set the condition register based on a signed comparison
1280 // with zero (so says the ISA manual). This is not as straightforward as it
1281 // seems, however, because this is always a 64-bit comparison on PPC64, even
1282 // for instructions that are 32-bit in nature (like slw for example).
1283 // So, on PPC32, for unsigned comparisons, we can use the record forms only
1284 // for equality checks (as those don't depend on the sign). On PPC64,
1285 // we are restricted to equality for unsigned 64-bit comparisons and for
1286 // signed 32-bit comparisons the applicability is more restricted.
1287 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
1288 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1289 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1290 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1292 // Get the unique definition of SrcReg.
1293 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1294 if (!MI) return false;
1295 int MIOpC = MI->getOpcode();
1297 bool equalityOnly = false;
1300 if (is32BitSignedCompare) {
1301 // We can perform this optimization only if MI is sign-extending.
1302 if (MIOpC == PPC::SRAW || MIOpC == PPC::SRAWo ||
1303 MIOpC == PPC::SRAWI || MIOpC == PPC::SRAWIo ||
1304 MIOpC == PPC::EXTSB || MIOpC == PPC::EXTSBo ||
1305 MIOpC == PPC::EXTSH || MIOpC == PPC::EXTSHo ||
1306 MIOpC == PPC::EXTSW || MIOpC == PPC::EXTSWo) {
1310 } else if (is32BitUnsignedCompare) {
1311 // We can perform this optimization, equality only, if MI is
1313 if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo ||
1314 MIOpC == PPC::SLW || MIOpC == PPC::SLWo ||
1315 MIOpC == PPC::SRW || MIOpC == PPC::SRWo) {
1317 equalityOnly = true;
1321 equalityOnly = is64BitUnsignedCompare;
1323 equalityOnly = is32BitUnsignedCompare;
1326 // We need to check the uses of the condition register in order to reject
1327 // non-equality comparisons.
1328 for (MachineRegisterInfo::use_instr_iterator I =MRI->use_instr_begin(CRReg),
1329 IE = MRI->use_instr_end(); I != IE; ++I) {
1330 MachineInstr *UseMI = &*I;
1331 if (UseMI->getOpcode() == PPC::BCC) {
1332 unsigned Pred = UseMI->getOperand(0).getImm();
1333 if (Pred != PPC::PRED_EQ && Pred != PPC::PRED_NE)
1335 } else if (UseMI->getOpcode() == PPC::ISEL ||
1336 UseMI->getOpcode() == PPC::ISEL8) {
1337 unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1338 if (SubIdx != PPC::sub_eq)
1345 MachineBasicBlock::iterator I = CmpInstr;
1347 // Scan forward to find the first use of the compare.
1348 for (MachineBasicBlock::iterator EL = CmpInstr->getParent()->end();
1350 bool FoundUse = false;
1351 for (MachineRegisterInfo::use_instr_iterator J =MRI->use_instr_begin(CRReg),
1352 JE = MRI->use_instr_end(); J != JE; ++J)
1362 // There are two possible candidates which can be changed to set CR[01].
1363 // One is MI, the other is a SUB instruction.
1364 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1365 MachineInstr *Sub = NULL;
1367 // MI is not a candidate for CMPrr.
1369 // FIXME: Conservatively refuse to convert an instruction which isn't in the
1370 // same BB as the comparison. This is to allow the check below to avoid calls
1371 // (and other explicit clobbers); instead we should really check for these
1372 // more explicitly (in at least a few predecessors).
1373 else if (MI->getParent() != CmpInstr->getParent() || Value != 0) {
1374 // PPC does not have a record-form SUBri.
1379 const TargetRegisterInfo *TRI = &getRegisterInfo();
1382 // Get ready to iterate backward from CmpInstr.
1383 MachineBasicBlock::iterator E = MI,
1384 B = CmpInstr->getParent()->begin();
1386 for (; I != E && !noSub; --I) {
1387 const MachineInstr &Instr = *I;
1388 unsigned IOpC = Instr.getOpcode();
1390 if (&*I != CmpInstr && (
1391 Instr.modifiesRegister(PPC::CR0, TRI) ||
1392 Instr.readsRegister(PPC::CR0, TRI)))
1393 // This instruction modifies or uses the record condition register after
1394 // the one we want to change. While we could do this transformation, it
1395 // would likely not be profitable. This transformation removes one
1396 // instruction, and so even forcing RA to generate one move probably
1397 // makes it unprofitable.
1400 // Check whether CmpInstr can be made redundant by the current instruction.
1401 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1402 OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1403 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1404 ((Instr.getOperand(1).getReg() == SrcReg &&
1405 Instr.getOperand(2).getReg() == SrcReg2) ||
1406 (Instr.getOperand(1).getReg() == SrcReg2 &&
1407 Instr.getOperand(2).getReg() == SrcReg))) {
1413 // The 'and' is below the comparison instruction.
1417 // Return false if no candidates exist.
1421 // The single candidate is called MI.
1425 MIOpC = MI->getOpcode();
1426 if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
1429 NewOpC = PPC::getRecordFormOpcode(MIOpC);
1430 if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1434 // FIXME: On the non-embedded POWER architectures, only some of the record
1435 // forms are fast, and we should use only the fast ones.
1437 // The defining instruction has a record form (or is already a record
1438 // form). It is possible, however, that we'll need to reverse the condition
1439 // code of the users.
1443 SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate;
1444 SmallVector<std::pair<MachineOperand*, unsigned>, 4> SubRegsToUpdate;
1446 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1447 // needs to be updated to be based on SUB. Push the condition code
1448 // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1449 // condition code of these operands will be modified.
1450 bool ShouldSwap = false;
1452 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1453 Sub->getOperand(2).getReg() == SrcReg;
1455 // The operands to subf are the opposite of sub, so only in the fixed-point
1456 // case, invert the order.
1457 ShouldSwap = !ShouldSwap;
1461 for (MachineRegisterInfo::use_instr_iterator
1462 I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1464 MachineInstr *UseMI = &*I;
1465 if (UseMI->getOpcode() == PPC::BCC) {
1466 PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1467 assert((!equalityOnly ||
1468 Pred == PPC::PRED_EQ || Pred == PPC::PRED_NE) &&
1469 "Invalid predicate for equality-only optimization");
1470 PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1471 PPC::getSwappedPredicate(Pred)));
1472 } else if (UseMI->getOpcode() == PPC::ISEL ||
1473 UseMI->getOpcode() == PPC::ISEL8) {
1474 unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1475 assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1476 "Invalid CR bit for equality-only optimization");
1478 if (NewSubReg == PPC::sub_lt)
1479 NewSubReg = PPC::sub_gt;
1480 else if (NewSubReg == PPC::sub_gt)
1481 NewSubReg = PPC::sub_lt;
1483 SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1485 } else // We need to abort on a user we don't understand.
1489 // Create a new virtual register to hold the value of the CR set by the
1490 // record-form instruction. If the instruction was not previously in
1491 // record form, then set the kill flag on the CR.
1492 CmpInstr->eraseFromParent();
1494 MachineBasicBlock::iterator MII = MI;
1495 BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1496 get(TargetOpcode::COPY), CRReg)
1497 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1499 if (MIOpC != NewOpC) {
1500 // We need to be careful here: we're replacing one instruction with
1501 // another, and we need to make sure that we get all of the right
1502 // implicit uses and defs. On the other hand, the caller may be holding
1503 // an iterator to this instruction, and so we can't delete it (this is
1504 // specifically the case if this is the instruction directly after the
1507 const MCInstrDesc &NewDesc = get(NewOpC);
1508 MI->setDesc(NewDesc);
1510 if (NewDesc.ImplicitDefs)
1511 for (const uint16_t *ImpDefs = NewDesc.getImplicitDefs();
1512 *ImpDefs; ++ImpDefs)
1513 if (!MI->definesRegister(*ImpDefs))
1514 MI->addOperand(*MI->getParent()->getParent(),
1515 MachineOperand::CreateReg(*ImpDefs, true, true));
1516 if (NewDesc.ImplicitUses)
1517 for (const uint16_t *ImpUses = NewDesc.getImplicitUses();
1518 *ImpUses; ++ImpUses)
1519 if (!MI->readsRegister(*ImpUses))
1520 MI->addOperand(*MI->getParent()->getParent(),
1521 MachineOperand::CreateReg(*ImpUses, false, true));
1524 // Modify the condition code of operands in OperandsToUpdate.
1525 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1526 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1527 for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1528 PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1530 for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
1531 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1536 /// GetInstSize - Return the number of bytes of code the specified
1537 /// instruction may be. This returns the maximum number of bytes.
1539 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
1540 unsigned Opcode = MI->getOpcode();
1542 if (Opcode == PPC::INLINEASM) {
1543 const MachineFunction *MF = MI->getParent()->getParent();
1544 const char *AsmStr = MI->getOperand(0).getSymbolName();
1545 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1547 const MCInstrDesc &Desc = get(Opcode);
1548 return Desc.getSize();
1554 #define DEBUG_TYPE "ppc-vsx-copy"
1557 void initializePPCVSXCopyPass(PassRegistry&);
1561 // PPCVSXCopy pass - For copies between VSX registers and non-VSX registers
1562 // (Altivec and scalar floating-point registers), we need to transform the
1563 // copies into subregister copies with other restrictions.
1564 struct PPCVSXCopy : public MachineFunctionPass {
1566 PPCVSXCopy() : MachineFunctionPass(ID) {
1567 initializePPCVSXCopyPass(*PassRegistry::getPassRegistry());
1570 const PPCTargetMachine *TM;
1571 const PPCInstrInfo *TII;
1573 bool IsRegInClass(unsigned Reg, const TargetRegisterClass *RC,
1574 MachineRegisterInfo &MRI) {
1575 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1576 return RC->hasSubClassEq(MRI.getRegClass(Reg));
1577 } else if (RC->contains(Reg)) {
1584 bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) {
1585 return IsRegInClass(Reg, &PPC::VSRCRegClass, MRI);
1588 bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) {
1589 return IsRegInClass(Reg, &PPC::VRRCRegClass, MRI);
1592 bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) {
1593 return IsRegInClass(Reg, &PPC::F8RCRegClass, MRI);
1597 bool processBlock(MachineBasicBlock &MBB) {
1598 bool Changed = false;
1600 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1601 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1603 MachineInstr *MI = I;
1604 if (!MI->isFullCopy())
1607 MachineOperand &DstMO = MI->getOperand(0);
1608 MachineOperand &SrcMO = MI->getOperand(1);
1610 if ( IsVSReg(DstMO.getReg(), MRI) &&
1611 !IsVSReg(SrcMO.getReg(), MRI)) {
1612 // This is a copy *to* a VSX register from a non-VSX register.
1615 const TargetRegisterClass *SrcRC =
1616 IsVRReg(SrcMO.getReg(), MRI) ? &PPC::VSHRCRegClass :
1617 &PPC::VSLRCRegClass;
1618 assert((IsF8Reg(SrcMO.getReg(), MRI) ||
1619 IsVRReg(SrcMO.getReg(), MRI)) &&
1620 "Unknown source for a VSX copy");
1622 unsigned NewVReg = MRI.createVirtualRegister(SrcRC);
1623 BuildMI(MBB, MI, MI->getDebugLoc(),
1624 TII->get(TargetOpcode::SUBREG_TO_REG), NewVReg)
1625 .addImm(1) // add 1, not 0, because there is no implicit clearing
1626 // of the high bits.
1628 .addImm(IsVRReg(SrcMO.getReg(), MRI) ? PPC::sub_128 :
1631 // The source of the original copy is now the new virtual register.
1632 SrcMO.setReg(NewVReg);
1633 } else if (!IsVSReg(DstMO.getReg(), MRI) &&
1634 IsVSReg(SrcMO.getReg(), MRI)) {
1635 // This is a copy *from* a VSX register to a non-VSX register.
1638 const TargetRegisterClass *DstRC =
1639 IsVRReg(DstMO.getReg(), MRI) ? &PPC::VSHRCRegClass :
1640 &PPC::VSLRCRegClass;
1641 assert((IsF8Reg(DstMO.getReg(), MRI) ||
1642 IsVRReg(DstMO.getReg(), MRI)) &&
1643 "Unknown destination for a VSX copy");
1645 // Copy the VSX value into a new VSX register of the correct subclass.
1646 unsigned NewVReg = MRI.createVirtualRegister(DstRC);
1647 BuildMI(MBB, MI, MI->getDebugLoc(),
1648 TII->get(TargetOpcode::COPY), NewVReg)
1651 // Transform the original copy into a subregister extraction copy.
1652 SrcMO.setReg(NewVReg);
1653 SrcMO.setSubReg(IsVRReg(DstMO.getReg(), MRI) ? PPC::sub_128 :
1662 virtual bool runOnMachineFunction(MachineFunction &MF) {
1663 TM = static_cast<const PPCTargetMachine *>(&MF.getTarget());
1664 TII = TM->getInstrInfo();
1666 bool Changed = false;
1668 for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
1669 MachineBasicBlock &B = *I++;
1670 if (processBlock(B))
1677 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1678 MachineFunctionPass::getAnalysisUsage(AU);
1683 INITIALIZE_PASS(PPCVSXCopy, DEBUG_TYPE,
1684 "PowerPC VSX Copy Legalization", false, false)
1686 char PPCVSXCopy::ID = 0;
1688 llvm::createPPCVSXCopyPass() { return new PPCVSXCopy(); }
1691 #define DEBUG_TYPE "ppc-early-ret"
1692 STATISTIC(NumBCLR, "Number of early conditional returns");
1693 STATISTIC(NumBLR, "Number of early returns");
1696 void initializePPCEarlyReturnPass(PassRegistry&);
1700 // PPCEarlyReturn pass - For simple functions without epilogue code, move
1701 // returns up, and create conditional returns, to avoid unnecessary
1702 // branch-to-blr sequences.
1703 struct PPCEarlyReturn : public MachineFunctionPass {
1705 PPCEarlyReturn() : MachineFunctionPass(ID) {
1706 initializePPCEarlyReturnPass(*PassRegistry::getPassRegistry());
1709 const PPCTargetMachine *TM;
1710 const PPCInstrInfo *TII;
1713 bool processBlock(MachineBasicBlock &ReturnMBB) {
1714 bool Changed = false;
1716 MachineBasicBlock::iterator I = ReturnMBB.begin();
1717 I = ReturnMBB.SkipPHIsAndLabels(I);
1719 // The block must be essentially empty except for the blr.
1720 if (I == ReturnMBB.end() || I->getOpcode() != PPC::BLR ||
1721 I != ReturnMBB.getLastNonDebugInstr())
1724 SmallVector<MachineBasicBlock*, 8> PredToRemove;
1725 for (MachineBasicBlock::pred_iterator PI = ReturnMBB.pred_begin(),
1726 PIE = ReturnMBB.pred_end(); PI != PIE; ++PI) {
1727 bool OtherReference = false, BlockChanged = false;
1728 for (MachineBasicBlock::iterator J = (*PI)->getLastNonDebugInstr();;) {
1729 if (J->getOpcode() == PPC::B) {
1730 if (J->getOperand(0).getMBB() == &ReturnMBB) {
1731 // This is an unconditional branch to the return. Replace the
1732 // branch with a blr.
1733 BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BLR));
1734 MachineBasicBlock::iterator K = J--;
1735 K->eraseFromParent();
1736 BlockChanged = true;
1740 } else if (J->getOpcode() == PPC::BCC) {
1741 if (J->getOperand(2).getMBB() == &ReturnMBB) {
1742 // This is a conditional branch to the return. Replace the branch
1744 BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BCCLR))
1745 .addImm(J->getOperand(0).getImm())
1746 .addReg(J->getOperand(1).getReg());
1747 MachineBasicBlock::iterator K = J--;
1748 K->eraseFromParent();
1749 BlockChanged = true;
1753 } else if (J->getOpcode() == PPC::BC || J->getOpcode() == PPC::BCn) {
1754 if (J->getOperand(1).getMBB() == &ReturnMBB) {
1755 // This is a conditional branch to the return. Replace the branch
1757 BuildMI(**PI, J, J->getDebugLoc(),
1758 TII->get(J->getOpcode() == PPC::BC ?
1759 PPC::BCLR : PPC::BCLRn))
1760 .addReg(J->getOperand(0).getReg());
1761 MachineBasicBlock::iterator K = J--;
1762 K->eraseFromParent();
1763 BlockChanged = true;
1767 } else if (J->isBranch()) {
1768 if (J->isIndirectBranch()) {
1769 if (ReturnMBB.hasAddressTaken())
1770 OtherReference = true;
1772 for (unsigned i = 0; i < J->getNumOperands(); ++i)
1773 if (J->getOperand(i).isMBB() &&
1774 J->getOperand(i).getMBB() == &ReturnMBB)
1775 OtherReference = true;
1776 } else if (!J->isTerminator() && !J->isDebugValue())
1779 if (J == (*PI)->begin())
1785 if ((*PI)->canFallThrough() && (*PI)->isLayoutSuccessor(&ReturnMBB))
1786 OtherReference = true;
1788 // Predecessors are stored in a vector and can't be removed here.
1789 if (!OtherReference && BlockChanged) {
1790 PredToRemove.push_back(*PI);
1797 for (unsigned i = 0, ie = PredToRemove.size(); i != ie; ++i)
1798 PredToRemove[i]->removeSuccessor(&ReturnMBB);
1800 if (Changed && !ReturnMBB.hasAddressTaken()) {
1801 // We now might be able to merge this blr-only block into its
1802 // by-layout predecessor.
1803 if (ReturnMBB.pred_size() == 1 &&
1804 (*ReturnMBB.pred_begin())->isLayoutSuccessor(&ReturnMBB)) {
1805 // Move the blr into the preceding block.
1806 MachineBasicBlock &PrevMBB = **ReturnMBB.pred_begin();
1807 PrevMBB.splice(PrevMBB.end(), &ReturnMBB, I);
1808 PrevMBB.removeSuccessor(&ReturnMBB);
1811 if (ReturnMBB.pred_empty())
1812 ReturnMBB.eraseFromParent();
1819 virtual bool runOnMachineFunction(MachineFunction &MF) {
1820 TM = static_cast<const PPCTargetMachine *>(&MF.getTarget());
1821 TII = TM->getInstrInfo();
1823 bool Changed = false;
1825 // If the function does not have at least two blocks, then there is
1830 for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
1831 MachineBasicBlock &B = *I++;
1832 if (processBlock(B))
1839 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1840 MachineFunctionPass::getAnalysisUsage(AU);
1845 INITIALIZE_PASS(PPCEarlyReturn, DEBUG_TYPE,
1846 "PowerPC Early-Return Creation", false, false)
1848 char PPCEarlyReturn::ID = 0;
1850 llvm::createPPCEarlyReturnPass() { return new PPCEarlyReturn(); }