1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 class Format<bits<5> val> {
17 def Pseudo: Format<0>;
20 def Simm16 : Format<3>;
21 def PCRelimm24 : Format<5>;
22 def Imm24 : Format<6>;
24 def PCRelimm14 : Format<8>;
25 def Imm14 : Format<9>;
26 def Imm2 : Format<10>;
28 def Imm3 : Format<12>;
29 def Imm1 : Format<13>;
31 def Imm4 : Format<15>;
32 def Imm8 : Format<16>;
33 def Disimm16 : Format<17>;
34 def Disimm14 : Format<18>;
37 def Imm15 : Format<21>;
39 def Imm6 : Format<23>;
41 //===----------------------------------------------------------------------===//
43 // PowerPC instruction formats
45 class I<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
53 let Namespace = "PPC";
54 let Inst{0-5} = opcode;
56 let AsmString = asmstr;
60 class IForm<bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx,
61 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
70 class BForm<bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx,
71 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
83 class BForm_ext<bits<6> opcode, bit aa, bit lk, bits<5> bo, bits<5> bi,
84 bit ppc64, bit vmx, dag OL, string asmstr>
85 : BForm<opcode, aa, lk, ppc64, vmx, OL, asmstr> {
91 class DForm_base<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
92 : I<opcode, ppc64, vmx, OL, asmstr> {
102 class DForm_1<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
103 : I<opcode, ppc64, vmx, OL, asmstr> {
113 class DForm_2<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
114 : DForm_base<opcode, ppc64, vmx, OL, asmstr>;
116 class DForm_2_r0<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
117 : I<opcode, ppc64, vmx, OL, asmstr> {
126 // Currently we make the use/def reg distinction in ISel, not tablegen
127 class DForm_3<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
128 : DForm_1<opcode, ppc64, vmx, OL, asmstr>;
130 class DForm_4<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
131 : DForm_base<opcode, ppc64, vmx, OL, asmstr>;
133 class DForm_4_zero<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
134 : DForm_1<opcode, ppc64, vmx, OL, asmstr> {
140 class DForm_5<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
141 : I<opcode, ppc64, vmx, OL, asmstr> {
150 let Inst{11-15} = RA;
154 class DForm_5_ext<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
155 : DForm_5<opcode, ppc64, vmx, OL, asmstr> {
159 class DForm_6<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
160 : DForm_5<opcode, ppc64, vmx, OL, asmstr>;
162 class DForm_6_ext<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
163 : DForm_6<opcode, ppc64, vmx, OL, asmstr> {
167 class DForm_8<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
168 : DForm_1<opcode, ppc64, vmx, OL, asmstr> {
171 class DForm_9<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
172 : DForm_1<opcode, ppc64, vmx, OL, asmstr> {
176 class DSForm_1<bits<6> opcode, bits<2> xo, bit ppc64, bit vmx,
177 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
182 let Inst{6-10} = RST;
183 let Inst{11-15} = RA;
184 let Inst{16-29} = DS;
185 let Inst{30-31} = xo;
188 class DSForm_2<bits<6> opcode, bits<2> xo, bit ppc64, bit vmx,
189 dag OL, string asmstr>
190 : DSForm_1<opcode, xo, ppc64, vmx, OL, asmstr>;
193 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
194 dag OL, string asmstr>
195 : I<opcode, ppc64, vmx, OL, asmstr> {
200 let Inst{6-10} = RST;
203 let Inst{21-30} = xo;
208 class XForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
209 dag OL, string asmstr>
210 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr>;
212 class XForm_5<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
213 dag OL, string asmstr>
214 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
219 class XForm_6<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
220 dag OL, string asmstr>
221 : I<opcode, ppc64, vmx, OL, asmstr> {
226 let Inst{6-10} = RST;
229 let Inst{21-30} = xo;
233 class XForm_8<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
234 dag OL, string asmstr>
235 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr>;
237 class XForm_10<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
238 dag OL, string asmstr>
239 : XForm_base_r3xo<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
242 class XForm_11<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
243 dag OL, string asmstr>
244 : XForm_base_r3xo<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
248 class XForm_16<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
249 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
258 let Inst{11-15} = RA;
259 let Inst{16-20} = RB;
260 let Inst{21-30} = xo;
264 class XForm_16_ext<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
265 dag OL, string asmstr>
266 : XForm_16<opcode, xo, ppc64, vmx, OL, asmstr> {
270 class XForm_17<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
271 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
278 let Inst{11-15} = FRA;
279 let Inst{16-20} = FRB;
280 let Inst{21-30} = xo;
284 class XForm_25<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
285 dag OL, string asmstr>
286 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
289 class XForm_26<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
290 dag OL, string asmstr>
291 : XForm_base_r3xo<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
295 class XForm_28<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
296 dag OL, string asmstr>
297 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
301 class XLForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
302 dag OL, string asmstr>
303 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
306 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, bit ppc64, bit vmx,
307 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
313 let Inst{11-15} = BI;
315 let Inst{19-20} = BH;
316 let Inst{21-30} = xo;
320 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo,
321 bits<5> bi, bit lk, bit ppc64, bit vmx,
322 dag OL, string asmstr>
323 : XLForm_2<opcode, xo, lk, ppc64, vmx, OL, asmstr> {
330 class XFXForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
331 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
336 let Inst{11-20} = SPR;
337 let Inst{21-30} = xo;
341 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, bit ppc64,
342 bit vmx, dag OL, string asmstr>
343 : XFXForm_1<opcode, xo, ppc64, vmx, OL, asmstr> {
347 class XFXForm_7<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
348 dag OL, string asmstr>
349 : XFXForm_1<opcode, xo, ppc64, vmx, OL, asmstr>;
351 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
352 bit ppc64, bit vmx, dag OL, string asmstr>
353 : XFXForm_7<opcode, xo, ppc64, vmx, OL, asmstr> {
358 class XSForm_1<bits<6> opcode, bits<9> xo, bit rc, bit ppc64, bit vmx,
359 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
366 let Inst{16-20} = SH{1-5};
367 let Inst{21-29} = xo;
368 let Inst{30} = SH{0};
373 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, bit rc, bit ppc64, bit vmx,
374 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
380 let Inst{11-15} = RA;
381 let Inst{16-20} = RB;
383 let Inst{22-30} = xo;
387 class XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, bit rc, bit ppc64, bit vmx,
388 dag OL, string asmstr>
389 : XOForm_1<opcode, xo, oe, rc, ppc64, vmx, OL, asmstr> {
390 let Inst{11-15} = RB;
391 let Inst{16-20} = RA;
394 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, bit rc, bit ppc64, bit vmx,
395 dag OL, string asmstr>
396 : XOForm_1<opcode, xo, oe, rc, ppc64, vmx, OL, asmstr> {
401 class AForm_1<bits<6> opcode, bits<5> xo, bit rc, bit ppc64, bit vmx,
402 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
408 let Inst{6-10} = FRT;
409 let Inst{11-15} = FRA;
410 let Inst{16-20} = FRB;
411 let Inst{21-25} = FRC;
412 let Inst{26-30} = xo;
416 class AForm_2<bits<6> opcode, bits<5> xo, bit rc, bit ppc64, bit vmx, dag OL,
418 : AForm_1<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
422 class AForm_3<bits<6> opcode, bits<5> xo, bit rc, bit ppc64, bit vmx, dag OL,
424 : AForm_1<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
429 class MForm_1<bits<6> opcode, bit rc, bit ppc64, bit vmx,
430 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
438 let Inst{11-15} = RA;
439 let Inst{16-20} = RB;
440 let Inst{21-25} = MB;
441 let Inst{26-30} = ME;
445 class MForm_2<bits<6> opcode, bit rc, bit ppc64, bit vmx,
446 dag OL, string asmstr>
447 : MForm_1<opcode, rc, ppc64, vmx, OL, asmstr> {
451 class MDForm_1<bits<6> opcode, bits<3> xo, bit rc, bit ppc64, bit vmx,
452 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
459 let Inst{11-15} = RA;
460 let Inst{16-20} = SH{1-5};
461 let Inst{21-26} = MBE;
462 let Inst{27-29} = xo;
463 let Inst{30} = SH{0};
467 //===----------------------------------------------------------------------===//
469 class Pseudo<dag OL, string asmstr> : I<0, 0, 0, OL, asmstr> {