1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
18 bit PPC64 = 0; // Default value, override with isPPC64
20 let Namespace = "PPC";
21 let Inst{0-5} = opcode;
22 let OutOperandList = OOL;
23 let InOperandList = IOL;
24 let AsmString = asmstr;
27 bits<1> PPC970_First = 0;
28 bits<1> PPC970_Single = 0;
29 bits<1> PPC970_Cracked = 0;
30 bits<3> PPC970_Unit = 0;
32 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
33 /// these must be reflected there! See comments there for what these are.
34 let TSFlags{0} = PPC970_First;
35 let TSFlags{1} = PPC970_Single;
36 let TSFlags{2} = PPC970_Cracked;
37 let TSFlags{5-3} = PPC970_Unit;
39 // Fields used for relation models.
42 // For cases where multiple instruction definitions really represent the
43 // same underlying instruction but with one definition for 64-bit arguments
44 // and one for 32-bit arguments, this bit breaks the degeneracy between
45 // the two forms and allows TableGen to generate mapping tables.
46 bit Interpretation64Bit = 0;
49 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
50 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
51 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
52 class PPC970_MicroCode;
54 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
55 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
56 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
57 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
58 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
59 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
60 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
61 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
63 // Two joined instructions; used to emit two adjacent instructions as one.
64 // The itinerary from the first instruction is used for scheduling and
66 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
71 bit PPC64 = 0; // Default value, override with isPPC64
73 let Namespace = "PPC";
74 let Inst{0-5} = opcode1;
75 let Inst{32-37} = opcode2;
76 let OutOperandList = OOL;
77 let InOperandList = IOL;
78 let AsmString = asmstr;
81 bits<1> PPC970_First = 0;
82 bits<1> PPC970_Single = 0;
83 bits<1> PPC970_Cracked = 0;
84 bits<3> PPC970_Unit = 0;
86 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
87 /// these must be reflected there! See comments there for what these are.
88 let TSFlags{0} = PPC970_First;
89 let TSFlags{1} = PPC970_Single;
90 let TSFlags{2} = PPC970_Cracked;
91 let TSFlags{5-3} = PPC970_Unit;
93 // Fields used for relation models.
95 bit Interpretation64Bit = 0;
99 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
100 InstrItinClass itin, list<dag> pattern>
101 : I<opcode, OOL, IOL, asmstr, itin> {
102 let Pattern = pattern;
111 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
112 : I<opcode, OOL, IOL, asmstr, BrB> {
113 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
118 let BI{0-1} = BIBO{5-6};
119 let BI{2-4} = CR{0-2};
121 let Inst{6-10} = BIBO{4-0};
122 let Inst{11-15} = BI;
123 let Inst{16-29} = BD;
128 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
130 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
136 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
137 dag OOL, dag IOL, string asmstr>
138 : I<opcode, OOL, IOL, asmstr, BrB> {
142 let Inst{11-15} = bi;
143 let Inst{16-29} = BD;
148 class BForm_3<bits<6> opcode, bit aa, bit lk,
149 dag OOL, dag IOL, string asmstr>
150 : I<opcode, OOL, IOL, asmstr, BrB> {
156 let Inst{11-15} = BI;
157 let Inst{16-29} = BD;
163 class SCForm<bits<6> opcode, bits<1> xo,
164 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
166 : I<opcode, OOL, IOL, asmstr, itin> {
169 let Pattern = pattern;
171 let Inst{20-26} = LEV;
176 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
177 InstrItinClass itin, list<dag> pattern>
178 : I<opcode, OOL, IOL, asmstr, itin> {
183 let Pattern = pattern;
190 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
191 InstrItinClass itin, list<dag> pattern>
192 : I<opcode, OOL, IOL, asmstr, itin> {
196 let Pattern = pattern;
199 let Inst{11-15} = Addr{20-16}; // Base Reg
200 let Inst{16-31} = Addr{15-0}; // Displacement
203 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
204 InstrItinClass itin, list<dag> pattern>
205 : I<opcode, OOL, IOL, asmstr, itin> {
210 let Pattern = pattern;
218 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
219 InstrItinClass itin, list<dag> pattern>
220 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
222 // Even though ADDICo does not really have an RC bit, provide
223 // the declaration of one here so that isDOT has something to set.
227 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
228 InstrItinClass itin, list<dag> pattern>
229 : I<opcode, OOL, IOL, asmstr, itin> {
233 let Pattern = pattern;
240 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
241 InstrItinClass itin, list<dag> pattern>
242 : I<opcode, OOL, IOL, asmstr, itin> {
247 let Pattern = pattern;
254 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
255 InstrItinClass itin, list<dag> pattern>
256 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
261 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
262 dag OOL, dag IOL, string asmstr,
263 InstrItinClass itin, list<dag> pattern>
264 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
268 let Pattern = pattern;
276 let Inst{43-47} = Addr{20-16}; // Base Reg
277 let Inst{48-63} = Addr{15-0}; // Displacement
280 // This is used to emit BL8+NOP.
281 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
282 dag OOL, dag IOL, string asmstr,
283 InstrItinClass itin, list<dag> pattern>
284 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
285 OOL, IOL, asmstr, itin, pattern> {
290 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
292 : I<opcode, OOL, IOL, asmstr, itin> {
301 let Inst{11-15} = RA;
305 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
307 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
311 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
313 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
315 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
317 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
323 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
324 InstrItinClass itin, list<dag> pattern>
325 : I<opcode, OOL, IOL, asmstr, itin> {
329 let Pattern = pattern;
331 let Inst{6-10} = RST;
332 let Inst{11-15} = DS_RA{18-14}; // Register #
333 let Inst{16-29} = DS_RA{13-0}; // Displacement.
334 let Inst{30-31} = xo;
337 class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
338 InstrItinClass itin, list<dag> pattern>
339 : I<opcode, OOL, IOL, asmstr, itin> {
344 let Pattern = pattern;
346 let Inst{6-10} = RST;
347 let Inst{11-15} = RA;
348 let Inst{16-29} = DS;
349 let Inst{30-31} = xo;
353 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
354 InstrItinClass itin, list<dag> pattern>
355 : I<opcode, OOL, IOL, asmstr, itin> {
360 let Pattern = pattern;
362 bit RC = 0; // set by isDOT
364 let Inst{6-10} = RST;
367 let Inst{21-30} = xo;
371 // This is the same as XForm_base_r3xo, but the first two operands are swapped
372 // when code is emitted.
373 class XForm_base_r3xo_swapped
374 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
376 : I<opcode, OOL, IOL, asmstr, itin> {
381 bit RC = 0; // set by isDOT
383 let Inst{6-10} = RST;
386 let Inst{21-30} = xo;
391 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
392 InstrItinClass itin, list<dag> pattern>
393 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
395 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
396 InstrItinClass itin, list<dag> pattern>
397 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
401 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
402 InstrItinClass itin, list<dag> pattern>
403 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
404 let Pattern = pattern;
407 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
408 InstrItinClass itin, list<dag> pattern>
409 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
411 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
412 InstrItinClass itin, list<dag> pattern>
413 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
414 let Pattern = pattern;
417 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
418 InstrItinClass itin, list<dag> pattern>
419 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
421 let Pattern = pattern;
424 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
426 : I<opcode, OOL, IOL, asmstr, itin> {
435 let Inst{11-15} = RA;
436 let Inst{16-20} = RB;
437 let Inst{21-30} = xo;
441 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
443 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
447 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
449 : I<opcode, OOL, IOL, asmstr, itin> {
456 let Inst{11-15} = FRA;
457 let Inst{16-20} = FRB;
458 let Inst{21-30} = xo;
462 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
463 InstrItinClass itin, list<dag> pattern>
464 : I<opcode, OOL, IOL, asmstr, itin> {
465 let Pattern = pattern;
469 let Inst{21-30} = xo;
473 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
474 string asmstr, InstrItinClass itin, list<dag> pattern>
475 : I<opcode, OOL, IOL, asmstr, itin> {
476 let Pattern = pattern;
480 let Inst{21-30} = xo;
484 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
485 InstrItinClass itin, list<dag> pattern>
486 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
489 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
490 InstrItinClass itin, list<dag> pattern>
491 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
495 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
496 InstrItinClass itin, list<dag> pattern>
497 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
500 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
501 // numbers presumably relates to some document, but I haven't found it.
502 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
503 InstrItinClass itin, list<dag> pattern>
504 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
505 let Pattern = pattern;
507 bit RC = 0; // set by isDOT
509 let Inst{6-10} = RST;
511 let Inst{21-30} = xo;
514 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
515 InstrItinClass itin, list<dag> pattern>
516 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
517 let Pattern = pattern;
520 bit RC = 0; // set by isDOT
524 let Inst{21-30} = xo;
528 // DCB_Form - Form X instruction, used for dcb* instructions.
529 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
530 InstrItinClass itin, list<dag> pattern>
531 : I<31, OOL, IOL, asmstr, itin> {
535 let Pattern = pattern;
537 let Inst{6-10} = immfield;
540 let Inst{21-30} = xo;
545 // DSS_Form - Form X instruction, used for altivec dss* instructions.
546 class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr,
547 InstrItinClass itin, list<dag> pattern>
548 : I<31, OOL, IOL, asmstr, itin> {
554 let Pattern = pattern;
558 let Inst{9-10} = STRM;
561 let Inst{21-30} = xo;
566 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
567 InstrItinClass itin, list<dag> pattern>
568 : I<opcode, OOL, IOL, asmstr, itin> {
573 let Pattern = pattern;
575 let Inst{6-10} = CRD;
576 let Inst{11-15} = CRA;
577 let Inst{16-20} = CRB;
578 let Inst{21-30} = xo;
582 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
583 InstrItinClass itin, list<dag> pattern>
584 : I<opcode, OOL, IOL, asmstr, itin> {
587 let Pattern = pattern;
589 let Inst{6-10} = CRD;
590 let Inst{11-15} = CRD;
591 let Inst{16-20} = CRD;
592 let Inst{21-30} = xo;
596 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
597 InstrItinClass itin, list<dag> pattern>
598 : I<opcode, OOL, IOL, asmstr, itin> {
603 let Pattern = pattern;
606 let Inst{11-15} = BI;
608 let Inst{19-20} = BH;
609 let Inst{21-30} = xo;
613 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
614 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
615 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
616 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
620 let BI{0-1} = BIBO{5-6};
621 let BI{2-4} = CR{0-2};
626 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
627 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
628 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
634 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
636 : I<opcode, OOL, IOL, asmstr, itin> {
642 let Inst{11-13} = BFA;
645 let Inst{21-30} = xo;
650 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
652 : I<opcode, OOL, IOL, asmstr, itin> {
657 let Inst{11} = SPR{4};
658 let Inst{12} = SPR{3};
659 let Inst{13} = SPR{2};
660 let Inst{14} = SPR{1};
661 let Inst{15} = SPR{0};
662 let Inst{16} = SPR{9};
663 let Inst{17} = SPR{8};
664 let Inst{18} = SPR{7};
665 let Inst{19} = SPR{6};
666 let Inst{20} = SPR{5};
667 let Inst{21-30} = xo;
671 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
672 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
673 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
677 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
679 : I<opcode, OOL, IOL, asmstr, itin> {
684 let Inst{21-30} = xo;
688 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
690 : I<opcode, OOL, IOL, asmstr, itin> {
696 let Inst{12-19} = FXM;
698 let Inst{21-30} = xo;
702 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
704 : I<opcode, OOL, IOL, asmstr, itin> {
710 let Inst{12-19} = FXM;
712 let Inst{21-30} = xo;
716 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
718 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
720 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
721 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
722 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
727 // This is probably 1.7.9, but I don't have the reference that uses this
728 // numbering scheme...
729 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
730 InstrItinClass itin, list<dag>pattern>
731 : I<opcode, OOL, IOL, asmstr, itin> {
735 bit RC = 0; // set by isDOT
736 let Pattern = pattern;
741 let Inst{16-20} = rT;
742 let Inst{21-30} = xo;
746 // 1.7.10 XS-Form - SRADI.
747 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
748 InstrItinClass itin, list<dag> pattern>
749 : I<opcode, OOL, IOL, asmstr, itin> {
754 bit RC = 0; // set by isDOT
755 let Pattern = pattern;
759 let Inst{16-20} = SH{4,3,2,1,0};
760 let Inst{21-29} = xo;
761 let Inst{30} = SH{5};
766 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
767 InstrItinClass itin, list<dag> pattern>
768 : I<opcode, OOL, IOL, asmstr, itin> {
773 let Pattern = pattern;
775 bit RC = 0; // set by isDOT
778 let Inst{11-15} = RA;
779 let Inst{16-20} = RB;
781 let Inst{22-30} = xo;
785 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
786 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
787 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
792 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
793 InstrItinClass itin, list<dag> pattern>
794 : I<opcode, OOL, IOL, asmstr, itin> {
800 let Pattern = pattern;
802 bit RC = 0; // set by isDOT
804 let Inst{6-10} = FRT;
805 let Inst{11-15} = FRA;
806 let Inst{16-20} = FRB;
807 let Inst{21-25} = FRC;
808 let Inst{26-30} = xo;
812 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
813 InstrItinClass itin, list<dag> pattern>
814 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
818 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
819 InstrItinClass itin, list<dag> pattern>
820 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
824 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
825 InstrItinClass itin, list<dag> pattern>
826 : I<opcode, OOL, IOL, asmstr, itin> {
832 let Pattern = pattern;
835 let Inst{11-15} = RA;
836 let Inst{16-20} = RB;
837 let Inst{21-25} = COND;
838 let Inst{26-30} = xo;
843 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
844 InstrItinClass itin, list<dag> pattern>
845 : I<opcode, OOL, IOL, asmstr, itin> {
852 let Pattern = pattern;
854 bit RC = 0; // set by isDOT
857 let Inst{11-15} = RA;
858 let Inst{16-20} = RB;
859 let Inst{21-25} = MB;
860 let Inst{26-30} = ME;
864 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
865 InstrItinClass itin, list<dag> pattern>
866 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
870 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
871 InstrItinClass itin, list<dag> pattern>
872 : I<opcode, OOL, IOL, asmstr, itin> {
878 let Pattern = pattern;
880 bit RC = 0; // set by isDOT
883 let Inst{11-15} = RA;
884 let Inst{16-20} = SH{4,3,2,1,0};
885 let Inst{21-26} = MBE{4,3,2,1,0,5};
886 let Inst{27-29} = xo;
887 let Inst{30} = SH{5};
891 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
892 InstrItinClass itin, list<dag> pattern>
893 : I<opcode, OOL, IOL, asmstr, itin> {
899 let Pattern = pattern;
901 bit RC = 0; // set by isDOT
904 let Inst{11-15} = RA;
905 let Inst{16-20} = RB;
906 let Inst{21-26} = MBE{4,3,2,1,0,5};
907 let Inst{27-30} = xo;
914 // VAForm_1 - DACB ordering.
915 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
916 InstrItinClass itin, list<dag> pattern>
917 : I<4, OOL, IOL, asmstr, itin> {
923 let Pattern = pattern;
926 let Inst{11-15} = VA;
927 let Inst{16-20} = VB;
928 let Inst{21-25} = VC;
929 let Inst{26-31} = xo;
932 // VAForm_1a - DABC ordering.
933 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
934 InstrItinClass itin, list<dag> pattern>
935 : I<4, OOL, IOL, asmstr, itin> {
941 let Pattern = pattern;
944 let Inst{11-15} = VA;
945 let Inst{16-20} = VB;
946 let Inst{21-25} = VC;
947 let Inst{26-31} = xo;
950 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
951 InstrItinClass itin, list<dag> pattern>
952 : I<4, OOL, IOL, asmstr, itin> {
958 let Pattern = pattern;
961 let Inst{11-15} = VA;
962 let Inst{16-20} = VB;
964 let Inst{22-25} = SH;
965 let Inst{26-31} = xo;
969 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
970 InstrItinClass itin, list<dag> pattern>
971 : I<4, OOL, IOL, asmstr, itin> {
976 let Pattern = pattern;
979 let Inst{11-15} = VA;
980 let Inst{16-20} = VB;
981 let Inst{21-31} = xo;
984 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
985 InstrItinClass itin, list<dag> pattern>
986 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
992 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
993 InstrItinClass itin, list<dag> pattern>
994 : I<4, OOL, IOL, asmstr, itin> {
998 let Pattern = pattern;
1000 let Inst{6-10} = VD;
1001 let Inst{11-15} = 0;
1002 let Inst{16-20} = VB;
1003 let Inst{21-31} = xo;
1006 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
1007 InstrItinClass itin, list<dag> pattern>
1008 : I<4, OOL, IOL, asmstr, itin> {
1012 let Pattern = pattern;
1014 let Inst{6-10} = VD;
1015 let Inst{11-15} = IMM;
1016 let Inst{16-20} = 0;
1017 let Inst{21-31} = xo;
1020 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1021 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1022 InstrItinClass itin, list<dag> pattern>
1023 : I<4, OOL, IOL, asmstr, itin> {
1026 let Pattern = pattern;
1028 let Inst{6-10} = VD;
1029 let Inst{11-15} = 0;
1030 let Inst{16-20} = 0;
1031 let Inst{21-31} = xo;
1034 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1035 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1036 InstrItinClass itin, list<dag> pattern>
1037 : I<4, OOL, IOL, asmstr, itin> {
1040 let Pattern = pattern;
1043 let Inst{11-15} = 0;
1044 let Inst{16-20} = VB;
1045 let Inst{21-31} = xo;
1049 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
1050 InstrItinClass itin, list<dag> pattern>
1051 : I<4, OOL, IOL, asmstr, itin> {
1057 let Pattern = pattern;
1059 let Inst{6-10} = VD;
1060 let Inst{11-15} = VA;
1061 let Inst{16-20} = VB;
1063 let Inst{22-31} = xo;
1066 //===----------------------------------------------------------------------===//
1067 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1068 : I<0, OOL, IOL, asmstr, NoItinerary> {
1069 let isCodeGenOnly = 1;
1071 let Pattern = pattern;