1 //===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Altivec extension to the PowerPC instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Altivec transformation functions and pattern fragments.
18 // Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be
20 def vnot_ppc : PatFrag<(ops node:$in),
21 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>;
23 def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
24 (vector_shuffle node:$lhs, node:$rhs), [{
25 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG);
27 def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
28 (vector_shuffle node:$lhs, node:$rhs), [{
29 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG);
31 def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
32 (vector_shuffle node:$lhs, node:$rhs), [{
33 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);
35 def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
36 (vector_shuffle node:$lhs, node:$rhs), [{
37 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);
40 // These fragments are provided for little-endian, where the inputs must be
41 // swapped for correct semantics.
42 def vpkuhum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
43 (vector_shuffle node:$lhs, node:$rhs), [{
44 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG);
46 def vpkuwum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
47 (vector_shuffle node:$lhs, node:$rhs), [{
48 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG);
51 def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
52 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
53 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG);
55 def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
56 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
57 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG);
59 def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
60 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
61 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG);
63 def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
64 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
65 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG);
67 def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
68 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
69 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG);
71 def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
72 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
73 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG);
77 def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
78 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
79 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG);
81 def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
82 (vector_shuffle node:$lhs, node:$rhs), [{
83 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG);
85 def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
86 (vector_shuffle node:$lhs, node:$rhs), [{
87 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG);
89 def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
90 (vector_shuffle node:$lhs, node:$rhs), [{
91 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG);
93 def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
94 (vector_shuffle node:$lhs, node:$rhs), [{
95 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG);
97 def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
98 (vector_shuffle node:$lhs, node:$rhs), [{
99 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG);
103 // These fragments are provided for little-endian, where the inputs must be
104 // swapped for correct semantics.
105 def vmrglb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
106 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
107 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG);
109 def vmrglh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
110 (vector_shuffle node:$lhs, node:$rhs), [{
111 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG);
113 def vmrglw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
114 (vector_shuffle node:$lhs, node:$rhs), [{
115 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG);
117 def vmrghb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
118 (vector_shuffle node:$lhs, node:$rhs), [{
119 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG);
121 def vmrghh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
122 (vector_shuffle node:$lhs, node:$rhs), [{
123 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG);
125 def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
126 (vector_shuffle node:$lhs, node:$rhs), [{
127 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG);
131 def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{
132 return getI32Imm(PPC::isVSLDOIShuffleMask(N, false, *CurDAG));
134 def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
135 (vector_shuffle node:$lhs, node:$rhs), [{
136 return PPC::isVSLDOIShuffleMask(N, false, *CurDAG) != -1;
140 /// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into
141 /// vector_shuffle(X,undef,mask) by the dag combiner.
142 def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{
143 return getI32Imm(PPC::isVSLDOIShuffleMask(N, true, *CurDAG));
145 def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
146 (vector_shuffle node:$lhs, node:$rhs), [{
147 return PPC::isVSLDOIShuffleMask(N, true, *CurDAG) != -1;
148 }], VSLDOI_unary_get_imm>;
151 // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
152 def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{
153 return getI32Imm(PPC::getVSPLTImmediate(N, 1, *CurDAG));
155 def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
156 (vector_shuffle node:$lhs, node:$rhs), [{
157 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1);
159 def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{
160 return getI32Imm(PPC::getVSPLTImmediate(N, 2, *CurDAG));
162 def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
163 (vector_shuffle node:$lhs, node:$rhs), [{
164 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2);
166 def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{
167 return getI32Imm(PPC::getVSPLTImmediate(N, 4, *CurDAG));
169 def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
170 (vector_shuffle node:$lhs, node:$rhs), [{
171 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4);
175 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
176 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
177 return PPC::get_VSPLTI_elt(N, 1, *CurDAG);
179 def vecspltisb : PatLeaf<(build_vector), [{
180 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0;
181 }], VSPLTISB_get_imm>;
183 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
184 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
185 return PPC::get_VSPLTI_elt(N, 2, *CurDAG);
187 def vecspltish : PatLeaf<(build_vector), [{
188 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0;
189 }], VSPLTISH_get_imm>;
191 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
192 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
193 return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
195 def vecspltisw : PatLeaf<(build_vector), [{
196 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0;
197 }], VSPLTISW_get_imm>;
199 //===----------------------------------------------------------------------===//
200 // Helpers for defining instructions that directly correspond to intrinsics.
202 // VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type.
203 class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty>
204 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
205 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
206 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>;
208 // VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the
209 // inputs doesn't match the type of the output.
210 class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
212 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
213 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
214 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>;
216 // VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two
217 // input types and an output type.
218 class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
219 ValueType In1Ty, ValueType In2Ty>
220 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
221 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
223 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>;
225 // VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type.
226 class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
227 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
228 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
229 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>;
231 // VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the
232 // inputs doesn't match the type of the output.
233 class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
235 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
236 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
237 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>;
239 // VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two
240 // input types and an output type.
241 class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
242 ValueType In1Ty, ValueType In2Ty>
243 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
244 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
245 [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>;
247 // VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type.
248 class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID>
249 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
250 !strconcat(opc, " $vD, $vB"), IIC_VecFP,
251 [(set v4f32:$vD, (IntID v4f32:$vB))]>;
253 // VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the
254 // inputs doesn't match the type of the output.
255 class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
257 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
258 !strconcat(opc, " $vD, $vB"), IIC_VecFP,
259 [(set OutTy:$vD, (IntID InTy:$vB))]>;
261 //===----------------------------------------------------------------------===//
262 // Instruction Definitions.
264 def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">;
265 let Predicates = [HasAltivec] in {
267 def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM),
268 "dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>,
269 Deprecated<DeprecatedDST> {
274 def DSSALL : DSS_Form<1, 822, (outs), (ins),
275 "dssall", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dssall)]>,
276 Deprecated<DeprecatedDST> {
282 def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
283 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
284 [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>,
285 Deprecated<DeprecatedDST>;
287 def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
288 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
289 [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>,
290 Deprecated<DeprecatedDST>;
292 def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
293 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
294 [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>,
295 Deprecated<DeprecatedDST>;
297 def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
298 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
299 [(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM)]>,
300 Deprecated<DeprecatedDST>;
302 let isCodeGenOnly = 1 in {
303 // The very same instructions as above, but formally matching 64bit registers.
304 def DST64 : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
305 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
306 [(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM)]>,
307 Deprecated<DeprecatedDST>;
309 def DSTT64 : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
310 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
311 [(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM)]>,
312 Deprecated<DeprecatedDST>;
314 def DSTST64 : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
315 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
316 [(int_ppc_altivec_dstst i64:$rA, i32:$rB,
318 Deprecated<DeprecatedDST>;
320 def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
321 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
322 [(int_ppc_altivec_dststt i64:$rA, i32:$rB,
324 Deprecated<DeprecatedDST>;
327 def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins),
328 "mfvscr $vD", IIC_LdStStore,
329 [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>;
330 def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB),
331 "mtvscr $vB", IIC_LdStLoad,
332 [(int_ppc_altivec_mtvscr v4i32:$vB)]>;
334 let canFoldAsLoad = 1, PPC970_Unit = 2 in { // Loads.
335 def LVEBX: XForm_1<31, 7, (outs vrrc:$vD), (ins memrr:$src),
336 "lvebx $vD, $src", IIC_LdStLoad,
337 [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
338 def LVEHX: XForm_1<31, 39, (outs vrrc:$vD), (ins memrr:$src),
339 "lvehx $vD, $src", IIC_LdStLoad,
340 [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
341 def LVEWX: XForm_1<31, 71, (outs vrrc:$vD), (ins memrr:$src),
342 "lvewx $vD, $src", IIC_LdStLoad,
343 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
344 def LVX : XForm_1<31, 103, (outs vrrc:$vD), (ins memrr:$src),
345 "lvx $vD, $src", IIC_LdStLoad,
346 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
347 def LVXL : XForm_1<31, 359, (outs vrrc:$vD), (ins memrr:$src),
348 "lvxl $vD, $src", IIC_LdStLoad,
349 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
352 def LVSL : XForm_1<31, 6, (outs vrrc:$vD), (ins memrr:$src),
353 "lvsl $vD, $src", IIC_LdStLoad,
354 [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
356 def LVSR : XForm_1<31, 38, (outs vrrc:$vD), (ins memrr:$src),
357 "lvsr $vD, $src", IIC_LdStLoad,
358 [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
361 let PPC970_Unit = 2 in { // Stores.
362 def STVEBX: XForm_8<31, 135, (outs), (ins vrrc:$rS, memrr:$dst),
363 "stvebx $rS, $dst", IIC_LdStStore,
364 [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>;
365 def STVEHX: XForm_8<31, 167, (outs), (ins vrrc:$rS, memrr:$dst),
366 "stvehx $rS, $dst", IIC_LdStStore,
367 [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>;
368 def STVEWX: XForm_8<31, 199, (outs), (ins vrrc:$rS, memrr:$dst),
369 "stvewx $rS, $dst", IIC_LdStStore,
370 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>;
371 def STVX : XForm_8<31, 231, (outs), (ins vrrc:$rS, memrr:$dst),
372 "stvx $rS, $dst", IIC_LdStStore,
373 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>;
374 def STVXL : XForm_8<31, 487, (outs), (ins vrrc:$rS, memrr:$dst),
375 "stvxl $rS, $dst", IIC_LdStStore,
376 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>;
379 let PPC970_Unit = 5 in { // VALU Operations.
380 // VA-Form instructions. 3-input AltiVec ops.
381 let isCommutable = 1 in {
382 def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
383 "vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP,
385 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>;
387 // FIXME: The fma+fneg pattern won't match because fneg is not legal.
388 def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
389 "vnmsubfp $vD, $vA, $vC, $vB", IIC_VecFP,
390 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC,
391 (fneg v4f32:$vB))))]>;
393 def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>;
394 def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs,
396 def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>;
399 def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm,
400 v4i32, v4i32, v16i8>;
401 def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>;
404 def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u5imm:$SH),
405 "vsldoi $vD, $vA, $vB, $SH", IIC_VecFP,
407 (vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB))]>;
409 // VX-Form instructions. AltiVec arithmetic ops.
410 let isCommutable = 1 in {
411 def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
412 "vaddfp $vD, $vA, $vB", IIC_VecFP,
413 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>;
415 def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
416 "vaddubm $vD, $vA, $vB", IIC_VecGeneral,
417 [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>;
418 def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
419 "vadduhm $vD, $vA, $vB", IIC_VecGeneral,
420 [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>;
421 def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
422 "vadduwm $vD, $vA, $vB", IIC_VecGeneral,
423 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>;
425 def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>;
426 def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>;
427 def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>;
428 def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>;
429 def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>;
430 def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>;
431 def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>;
434 let isCommutable = 1 in
435 def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
436 "vand $vD, $vA, $vB", IIC_VecFP,
437 [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>;
438 def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
439 "vandc $vD, $vA, $vB", IIC_VecFP,
440 [(set v4i32:$vD, (and v4i32:$vA,
441 (vnot_ppc v4i32:$vB)))]>;
443 def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
444 "vcfsx $vD, $vB, $UIMM", IIC_VecFP,
446 (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>;
447 def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
448 "vcfux $vD, $vB, $UIMM", IIC_VecFP,
450 (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>;
451 def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
452 "vctsxs $vD, $vB, $UIMM", IIC_VecFP,
454 (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>;
455 def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
456 "vctuxs $vD, $vB, $UIMM", IIC_VecFP,
458 (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>;
460 // Defines with the UIM field set to 0 for floating-point
461 // to integer (fp_to_sint/fp_to_uint) conversions and integer
462 // to floating-point (sint_to_fp/uint_to_fp) conversions.
463 let isCodeGenOnly = 1, VA = 0 in {
464 def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB),
465 "vcfsx $vD, $vB, 0", IIC_VecFP,
467 (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>;
468 def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB),
469 "vctuxs $vD, $vB, 0", IIC_VecFP,
471 (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>;
472 def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB),
473 "vcfux $vD, $vB, 0", IIC_VecFP,
475 (int_ppc_altivec_vcfux v4i32:$vB, 0))]>;
476 def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB),
477 "vctsxs $vD, $vB, 0", IIC_VecFP,
479 (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>;
481 def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>;
482 def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>;
484 let isCommutable = 1 in {
485 def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>;
486 def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>;
487 def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>;
488 def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>;
489 def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>;
490 def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>;
492 def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>;
493 def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>;
494 def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>;
495 def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>;
496 def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>;
497 def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>;
498 def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>;
499 def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>;
500 def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>;
501 def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>;
502 def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>;
503 def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>;
504 def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>;
505 def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>;
508 def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
509 "vmrghb $vD, $vA, $vB", IIC_VecFP,
510 [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>;
511 def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
512 "vmrghh $vD, $vA, $vB", IIC_VecFP,
513 [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>;
514 def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
515 "vmrghw $vD, $vA, $vB", IIC_VecFP,
516 [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>;
517 def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
518 "vmrglb $vD, $vA, $vB", IIC_VecFP,
519 [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>;
520 def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
521 "vmrglh $vD, $vA, $vB", IIC_VecFP,
522 [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>;
523 def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
524 "vmrglw $vD, $vA, $vB", IIC_VecFP,
525 [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>;
527 def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm,
528 v4i32, v16i8, v4i32>;
529 def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm,
530 v4i32, v8i16, v4i32>;
531 def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs,
532 v4i32, v8i16, v4i32>;
533 def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm,
534 v4i32, v16i8, v4i32>;
535 def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm,
536 v4i32, v8i16, v4i32>;
537 def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs,
538 v4i32, v8i16, v4i32>;
540 let isCommutable = 1 in {
541 def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb,
543 def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh,
545 def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub,
547 def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh,
549 def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb,
551 def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh,
553 def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub,
555 def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh,
559 def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>;
560 def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>;
561 def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>;
562 def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>;
563 def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>;
564 def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
566 def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>;
568 def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
569 "vsubfp $vD, $vA, $vB", IIC_VecGeneral,
570 [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>;
571 def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
572 "vsububm $vD, $vA, $vB", IIC_VecGeneral,
573 [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>;
574 def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
575 "vsubuhm $vD, $vA, $vB", IIC_VecGeneral,
576 [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>;
577 def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
578 "vsubuwm $vD, $vA, $vB", IIC_VecGeneral,
579 [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>;
581 def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>;
582 def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>;
583 def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>;
584 def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>;
585 def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>;
586 def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>;
588 def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>;
589 def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>;
591 def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs,
592 v4i32, v16i8, v4i32>;
593 def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs,
594 v4i32, v8i16, v4i32>;
595 def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs,
596 v4i32, v16i8, v4i32>;
598 def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
599 "vnor $vD, $vA, $vB", IIC_VecFP,
600 [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA,
602 let isCommutable = 1 in {
603 def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
604 "vor $vD, $vA, $vB", IIC_VecFP,
605 [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>;
606 def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
607 "vxor $vD, $vA, $vB", IIC_VecFP,
608 [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>;
611 def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>;
612 def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>;
613 def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>;
615 def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >;
616 def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>;
618 def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>;
619 def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>;
620 def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>;
622 def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
623 "vspltb $vD, $vB, $UIMM", IIC_VecPerm,
625 (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>;
626 def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
627 "vsplth $vD, $vB, $UIMM", IIC_VecPerm,
629 (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>;
630 def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
631 "vspltw $vD, $vB, $UIMM", IIC_VecPerm,
633 (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>;
635 def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>;
636 def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>;
638 def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>;
639 def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>;
640 def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>;
641 def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>;
642 def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>;
643 def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>;
646 def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM),
647 "vspltisb $vD, $SIMM", IIC_VecPerm,
648 [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>;
649 def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM),
650 "vspltish $vD, $SIMM", IIC_VecPerm,
651 [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>;
652 def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM),
653 "vspltisw $vD, $SIMM", IIC_VecPerm,
654 [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>;
657 def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx,
659 def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss,
661 def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus,
663 def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss,
665 def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus,
667 def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
668 "vpkuhum $vD, $vA, $vB", IIC_VecFP,
670 (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>;
671 def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus,
673 def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
674 "vpkuwum $vD, $vA, $vB", IIC_VecFP,
676 (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>;
677 def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus,
681 def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx,
683 def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb,
685 def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh,
687 def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx,
689 def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb,
691 def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh,
695 // Altivec Comparisons.
697 class VCMP<bits<10> xo, string asmstr, ValueType Ty>
698 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
700 [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>;
701 class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
702 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
704 [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> {
709 // f32 element comparisons.0
710 def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>;
711 def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
712 def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
713 def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
714 def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
715 def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
716 def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
717 def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
719 // i8 element comparisons.
720 def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>;
721 def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>;
722 def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
723 def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
724 def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
725 def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
727 // i16 element comparisons.
728 def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
729 def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
730 def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
731 def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
732 def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
733 def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
735 // i32 element comparisons.
736 def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
737 def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
738 def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
739 def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
740 def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
741 def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
743 let isCodeGenOnly = 1 in {
744 def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
745 "vxor $vD, $vD, $vD", IIC_VecFP,
746 [(set v16i8:$vD, (v16i8 immAllZerosV))]>;
747 def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
748 "vxor $vD, $vD, $vD", IIC_VecFP,
749 [(set v8i16:$vD, (v8i16 immAllZerosV))]>;
750 def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
751 "vxor $vD, $vD, $vD", IIC_VecFP,
752 [(set v4i32:$vD, (v4i32 immAllZerosV))]>;
755 def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins),
756 "vspltisw $vD, -1", IIC_VecFP,
757 [(set v16i8:$vD, (v16i8 immAllOnesV))]>;
758 def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins),
759 "vspltisw $vD, -1", IIC_VecFP,
760 [(set v8i16:$vD, (v8i16 immAllOnesV))]>;
761 def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins),
762 "vspltisw $vD, -1", IIC_VecFP,
763 [(set v4i32:$vD, (v4i32 immAllOnesV))]>;
766 } // VALU Operations.
768 //===----------------------------------------------------------------------===//
769 // Additional Altivec Patterns
773 def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;
776 def : Pat<(store v4i32:$rS, xoaddr:$dst),
777 (STVX $rS, xoaddr:$dst)>;
780 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
781 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
782 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
784 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
785 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
786 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
788 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
789 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
790 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
792 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
793 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
794 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
798 // Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x)
799 def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef),
800 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>;
801 def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef),
803 def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef),
806 // Match vpkuwum(y,x), vpkuhum(y,x), i.e., swapped operands.
807 // These fragments are matched for little-endian, where the
808 // inputs must be swapped for correct semantics.
809 def:Pat<(vpkuwum_swapped_shuffle v16i8:$vA, v16i8:$vB),
811 def:Pat<(vpkuhum_swapped_shuffle v16i8:$vA, v16i8:$vB),
815 def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef),
817 def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef),
819 def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef),
821 def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef),
823 def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef),
825 def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef),
828 // Match vmrg*(y,x), i.e., swapped operands. These fragments
829 // are matched for little-endian, where the inputs must be
830 // swapped for correct semantics.
831 def:Pat<(vmrglb_swapped_shuffle v16i8:$vA, v16i8:$vB),
833 def:Pat<(vmrglh_swapped_shuffle v16i8:$vA, v16i8:$vB),
835 def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB),
837 def:Pat<(vmrghb_swapped_shuffle v16i8:$vA, v16i8:$vB),
839 def:Pat<(vmrghh_swapped_shuffle v16i8:$vA, v16i8:$vB),
841 def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB),
844 // Logical Operations
845 def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>;
847 def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)),
849 def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)),
852 def : Pat<(fmul v4f32:$vA, v4f32:$vB),
854 (v4i32 (VSLW (V_SETALLONES), (V_SETALLONES))))>;
856 // Fused multiply add and multiply sub for packed float. These are represented
857 // separately from the real instructions above, for operations that must have
858 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
859 def : Pat<(PPCvmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
860 (VMADDFP $A, $B, $C)>;
861 def : Pat<(PPCvnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
862 (VNMSUBFP $A, $B, $C)>;
864 def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
865 (VMADDFP $A, $B, $C)>;
866 def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
867 (VNMSUBFP $A, $B, $C)>;
869 def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC),
870 (VPERM $vA, $vB, $vC)>;
872 def : Pat<(PPCfre v4f32:$A), (VREFP $A)>;
873 def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>;
876 def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)),
877 (v16i8 (VSLB $vA, $vB))>;
878 def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)),
879 (v8i16 (VSLH $vA, $vB))>;
880 def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)),
881 (v4i32 (VSLW $vA, $vB))>;
883 def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)),
884 (v16i8 (VSRB $vA, $vB))>;
885 def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)),
886 (v8i16 (VSRH $vA, $vB))>;
887 def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)),
888 (v4i32 (VSRW $vA, $vB))>;
890 def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)),
891 (v16i8 (VSRAB $vA, $vB))>;
892 def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)),
893 (v8i16 (VSRAH $vA, $vB))>;
894 def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)),
895 (v4i32 (VSRAW $vA, $vB))>;
897 // Float to integer and integer to float conversions
898 def : Pat<(v4i32 (fp_to_sint v4f32:$vA)),
900 def : Pat<(v4i32 (fp_to_uint v4f32:$vA)),
902 def : Pat<(v4f32 (sint_to_fp v4i32:$vA)),
904 def : Pat<(v4f32 (uint_to_fp v4i32:$vA)),
907 // Floating-point rounding
908 def : Pat<(v4f32 (ffloor v4f32:$vA)),
910 def : Pat<(v4f32 (fceil v4f32:$vA)),
912 def : Pat<(v4f32 (ftrunc v4f32:$vA)),
914 def : Pat<(v4f32 (fnearbyint v4f32:$vA)),