1 //===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Altivec extension to the PowerPC instruction set.
12 //===----------------------------------------------------------------------===//
14 // *********************************** NOTE ***********************************
15 // ** For POWER8 Little Endian, the VSX swap optimization relies on knowing **
16 // ** which VMX and VSX instructions are lane-sensitive and which are not. **
17 // ** A lane-sensitive instruction relies, implicitly or explicitly, on **
18 // ** whether lanes are numbered from left to right. An instruction like **
19 // ** VADDFP is not lane-sensitive, because each lane of the result vector **
20 // ** relies only on the corresponding lane of the source vectors. However, **
21 // ** an instruction like VMULESB is lane-sensitive, because "even" and **
22 // ** "odd" lanes are different for big-endian and little-endian numbering. **
24 // ** When adding new VMX and VSX instructions, please consider whether they **
25 // ** are lane-sensitive. If so, they must be added to a switch statement **
26 // ** in PPCVSXSwapRemoval::gatherVectorInstructions(). **
27 // ****************************************************************************
29 //===----------------------------------------------------------------------===//
30 // Altivec transformation functions and pattern fragments.
33 // Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be
35 def vnot_ppc : PatFrag<(ops node:$in),
36 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>;
38 def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
39 (vector_shuffle node:$lhs, node:$rhs), [{
40 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG);
42 def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
43 (vector_shuffle node:$lhs, node:$rhs), [{
44 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG);
46 def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
47 (vector_shuffle node:$lhs, node:$rhs), [{
48 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);
50 def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
51 (vector_shuffle node:$lhs, node:$rhs), [{
52 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG);
55 // These fragments are provided for little-endian, where the inputs must be
56 // swapped for correct semantics.
57 def vpkuhum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
58 (vector_shuffle node:$lhs, node:$rhs), [{
59 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG);
61 def vpkuwum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
62 (vector_shuffle node:$lhs, node:$rhs), [{
63 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG);
66 def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
67 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
68 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG);
70 def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
71 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
72 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG);
74 def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
75 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
76 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG);
78 def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
79 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
80 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG);
82 def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
83 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
84 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG);
86 def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
87 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
88 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG);
92 def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
93 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
94 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG);
96 def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
97 (vector_shuffle node:$lhs, node:$rhs), [{
98 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG);
100 def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
101 (vector_shuffle node:$lhs, node:$rhs), [{
102 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG);
104 def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
105 (vector_shuffle node:$lhs, node:$rhs), [{
106 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG);
108 def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
109 (vector_shuffle node:$lhs, node:$rhs), [{
110 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG);
112 def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
113 (vector_shuffle node:$lhs, node:$rhs), [{
114 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG);
118 // These fragments are provided for little-endian, where the inputs must be
119 // swapped for correct semantics.
120 def vmrglb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
121 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
122 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG);
124 def vmrglh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
125 (vector_shuffle node:$lhs, node:$rhs), [{
126 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG);
128 def vmrglw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
129 (vector_shuffle node:$lhs, node:$rhs), [{
130 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG);
132 def vmrghb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
133 (vector_shuffle node:$lhs, node:$rhs), [{
134 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG);
136 def vmrghh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
137 (vector_shuffle node:$lhs, node:$rhs), [{
138 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG);
140 def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
141 (vector_shuffle node:$lhs, node:$rhs), [{
142 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG);
146 def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{
147 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 0, *CurDAG), SDLoc(N));
149 def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
150 (vector_shuffle node:$lhs, node:$rhs), [{
151 return PPC::isVSLDOIShuffleMask(N, 0, *CurDAG) != -1;
155 /// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into
156 /// vector_shuffle(X,undef,mask) by the dag combiner.
157 def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{
158 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 1, *CurDAG), SDLoc(N));
160 def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
161 (vector_shuffle node:$lhs, node:$rhs), [{
162 return PPC::isVSLDOIShuffleMask(N, 1, *CurDAG) != -1;
163 }], VSLDOI_unary_get_imm>;
166 /// VSLDOI_swapped* - These fragments are provided for little-endian, where
167 /// the inputs must be swapped for correct semantics.
168 def VSLDOI_swapped_get_imm : SDNodeXForm<vector_shuffle, [{
169 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 2, *CurDAG), SDLoc(N));
171 def vsldoi_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
172 (vector_shuffle node:$lhs, node:$rhs), [{
173 return PPC::isVSLDOIShuffleMask(N, 2, *CurDAG) != -1;
177 // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
178 def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{
179 return getI32Imm(PPC::getVSPLTImmediate(N, 1, *CurDAG), SDLoc(N));
181 def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
182 (vector_shuffle node:$lhs, node:$rhs), [{
183 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1);
185 def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{
186 return getI32Imm(PPC::getVSPLTImmediate(N, 2, *CurDAG), SDLoc(N));
188 def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
189 (vector_shuffle node:$lhs, node:$rhs), [{
190 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2);
192 def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{
193 return getI32Imm(PPC::getVSPLTImmediate(N, 4, *CurDAG), SDLoc(N));
195 def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
196 (vector_shuffle node:$lhs, node:$rhs), [{
197 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4);
201 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
202 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
203 return PPC::get_VSPLTI_elt(N, 1, *CurDAG);
205 def vecspltisb : PatLeaf<(build_vector), [{
206 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0;
207 }], VSPLTISB_get_imm>;
209 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
210 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
211 return PPC::get_VSPLTI_elt(N, 2, *CurDAG);
213 def vecspltish : PatLeaf<(build_vector), [{
214 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0;
215 }], VSPLTISH_get_imm>;
217 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
218 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
219 return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
221 def vecspltisw : PatLeaf<(build_vector), [{
222 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0;
223 }], VSPLTISW_get_imm>;
225 //===----------------------------------------------------------------------===//
226 // Helpers for defining instructions that directly correspond to intrinsics.
228 // VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type.
229 class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty>
230 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
231 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
232 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>;
234 // VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the
235 // inputs doesn't match the type of the output.
236 class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
238 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
239 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
240 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>;
242 // VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two
243 // input types and an output type.
244 class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
245 ValueType In1Ty, ValueType In2Ty>
246 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
247 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
249 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>;
251 // VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type.
252 class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
253 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
254 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
255 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>;
257 // VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the
258 // inputs doesn't match the type of the output.
259 class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
261 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
262 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
263 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>;
265 // VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two
266 // input types and an output type.
267 class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
268 ValueType In1Ty, ValueType In2Ty>
269 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
270 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
271 [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>;
273 // VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type.
274 class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID>
275 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
276 !strconcat(opc, " $vD, $vB"), IIC_VecFP,
277 [(set v4f32:$vD, (IntID v4f32:$vB))]>;
279 // VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the
280 // inputs doesn't match the type of the output.
281 class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
283 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
284 !strconcat(opc, " $vD, $vB"), IIC_VecFP,
285 [(set OutTy:$vD, (IntID InTy:$vB))]>;
287 class VXBX_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
288 : VXForm_BX<xo, (outs vrrc:$vD), (ins vrrc:$vA),
289 !strconcat(opc, " $vD, $vA"), IIC_VecFP,
290 [(set Ty:$vD, (IntID Ty:$vA))]>;
292 class VXCR_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
293 : VXForm_CR<xo, (outs vrrc:$vD), (ins vrrc:$vA, u1imm:$ST, u4imm:$SIX),
294 !strconcat(opc, " $vD, $vA, $ST, $SIX"), IIC_VecFP,
295 [(set Ty:$vD, (IntID Ty:$vA, imm:$ST, imm:$SIX))]>;
297 //===----------------------------------------------------------------------===//
298 // Instruction Definitions.
300 def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">;
301 let Predicates = [HasAltivec] in {
303 def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM),
304 "dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>,
305 Deprecated<DeprecatedDST> {
310 def DSSALL : DSS_Form<1, 822, (outs), (ins),
311 "dssall", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dssall)]>,
312 Deprecated<DeprecatedDST> {
318 def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
319 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
320 [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>,
321 Deprecated<DeprecatedDST>;
323 def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
324 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
325 [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>,
326 Deprecated<DeprecatedDST>;
328 def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
329 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
330 [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>,
331 Deprecated<DeprecatedDST>;
333 def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
334 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
335 [(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM)]>,
336 Deprecated<DeprecatedDST>;
338 let isCodeGenOnly = 1 in {
339 // The very same instructions as above, but formally matching 64bit registers.
340 def DST64 : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
341 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
342 [(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM)]>,
343 Deprecated<DeprecatedDST>;
345 def DSTT64 : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
346 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
347 [(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM)]>,
348 Deprecated<DeprecatedDST>;
350 def DSTST64 : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
351 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
352 [(int_ppc_altivec_dstst i64:$rA, i32:$rB,
354 Deprecated<DeprecatedDST>;
356 def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
357 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
358 [(int_ppc_altivec_dststt i64:$rA, i32:$rB,
360 Deprecated<DeprecatedDST>;
363 def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins),
364 "mfvscr $vD", IIC_LdStStore,
365 [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>;
366 def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB),
367 "mtvscr $vB", IIC_LdStLoad,
368 [(int_ppc_altivec_mtvscr v4i32:$vB)]>;
370 let PPC970_Unit = 2 in { // Loads.
371 def LVEBX: XForm_1<31, 7, (outs vrrc:$vD), (ins memrr:$src),
372 "lvebx $vD, $src", IIC_LdStLoad,
373 [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
374 def LVEHX: XForm_1<31, 39, (outs vrrc:$vD), (ins memrr:$src),
375 "lvehx $vD, $src", IIC_LdStLoad,
376 [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
377 def LVEWX: XForm_1<31, 71, (outs vrrc:$vD), (ins memrr:$src),
378 "lvewx $vD, $src", IIC_LdStLoad,
379 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
380 def LVX : XForm_1<31, 103, (outs vrrc:$vD), (ins memrr:$src),
381 "lvx $vD, $src", IIC_LdStLoad,
382 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
383 def LVXL : XForm_1<31, 359, (outs vrrc:$vD), (ins memrr:$src),
384 "lvxl $vD, $src", IIC_LdStLoad,
385 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
388 def LVSL : XForm_1<31, 6, (outs vrrc:$vD), (ins memrr:$src),
389 "lvsl $vD, $src", IIC_LdStLoad,
390 [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
392 def LVSR : XForm_1<31, 38, (outs vrrc:$vD), (ins memrr:$src),
393 "lvsr $vD, $src", IIC_LdStLoad,
394 [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
397 let PPC970_Unit = 2 in { // Stores.
398 def STVEBX: XForm_8<31, 135, (outs), (ins vrrc:$rS, memrr:$dst),
399 "stvebx $rS, $dst", IIC_LdStStore,
400 [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>;
401 def STVEHX: XForm_8<31, 167, (outs), (ins vrrc:$rS, memrr:$dst),
402 "stvehx $rS, $dst", IIC_LdStStore,
403 [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>;
404 def STVEWX: XForm_8<31, 199, (outs), (ins vrrc:$rS, memrr:$dst),
405 "stvewx $rS, $dst", IIC_LdStStore,
406 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>;
407 def STVX : XForm_8<31, 231, (outs), (ins vrrc:$rS, memrr:$dst),
408 "stvx $rS, $dst", IIC_LdStStore,
409 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>;
410 def STVXL : XForm_8<31, 487, (outs), (ins vrrc:$rS, memrr:$dst),
411 "stvxl $rS, $dst", IIC_LdStStore,
412 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>;
415 let PPC970_Unit = 5 in { // VALU Operations.
416 // VA-Form instructions. 3-input AltiVec ops.
417 let isCommutable = 1 in {
418 def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
419 "vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP,
421 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>;
423 // FIXME: The fma+fneg pattern won't match because fneg is not legal.
424 def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
425 "vnmsubfp $vD, $vA, $vC, $vB", IIC_VecFP,
426 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC,
427 (fneg v4f32:$vB))))]>;
429 def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>;
430 def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs,
432 def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>;
435 def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm,
436 v4i32, v4i32, v16i8>;
437 def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>;
440 def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u5imm:$SH),
441 "vsldoi $vD, $vA, $vB, $SH", IIC_VecFP,
443 (vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB))]>;
445 // VX-Form instructions. AltiVec arithmetic ops.
446 let isCommutable = 1 in {
447 def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
448 "vaddfp $vD, $vA, $vB", IIC_VecFP,
449 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>;
451 def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
452 "vaddubm $vD, $vA, $vB", IIC_VecGeneral,
453 [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>;
454 def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
455 "vadduhm $vD, $vA, $vB", IIC_VecGeneral,
456 [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>;
457 def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
458 "vadduwm $vD, $vA, $vB", IIC_VecGeneral,
459 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>;
461 def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>;
462 def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>;
463 def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>;
464 def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>;
465 def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>;
466 def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>;
467 def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>;
470 let isCommutable = 1 in
471 def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
472 "vand $vD, $vA, $vB", IIC_VecFP,
473 [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>;
474 def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
475 "vandc $vD, $vA, $vB", IIC_VecFP,
476 [(set v4i32:$vD, (and v4i32:$vA,
477 (vnot_ppc v4i32:$vB)))]>;
479 def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
480 "vcfsx $vD, $vB, $UIMM", IIC_VecFP,
482 (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>;
483 def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
484 "vcfux $vD, $vB, $UIMM", IIC_VecFP,
486 (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>;
487 def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
488 "vctsxs $vD, $vB, $UIMM", IIC_VecFP,
490 (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>;
491 def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
492 "vctuxs $vD, $vB, $UIMM", IIC_VecFP,
494 (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>;
496 // Defines with the UIM field set to 0 for floating-point
497 // to integer (fp_to_sint/fp_to_uint) conversions and integer
498 // to floating-point (sint_to_fp/uint_to_fp) conversions.
499 let isCodeGenOnly = 1, VA = 0 in {
500 def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB),
501 "vcfsx $vD, $vB, 0", IIC_VecFP,
503 (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>;
504 def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB),
505 "vctuxs $vD, $vB, 0", IIC_VecFP,
507 (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>;
508 def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB),
509 "vcfux $vD, $vB, 0", IIC_VecFP,
511 (int_ppc_altivec_vcfux v4i32:$vB, 0))]>;
512 def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB),
513 "vctsxs $vD, $vB, 0", IIC_VecFP,
515 (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>;
517 def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>;
518 def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>;
520 let isCommutable = 1 in {
521 def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>;
522 def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>;
523 def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>;
524 def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>;
525 def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>;
526 def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>;
528 def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>;
529 def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>;
530 def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>;
531 def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>;
532 def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>;
533 def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>;
534 def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>;
535 def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>;
536 def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>;
537 def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>;
538 def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>;
539 def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>;
540 def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>;
541 def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>;
544 def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
545 "vmrghb $vD, $vA, $vB", IIC_VecFP,
546 [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>;
547 def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
548 "vmrghh $vD, $vA, $vB", IIC_VecFP,
549 [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>;
550 def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
551 "vmrghw $vD, $vA, $vB", IIC_VecFP,
552 [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>;
553 def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
554 "vmrglb $vD, $vA, $vB", IIC_VecFP,
555 [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>;
556 def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
557 "vmrglh $vD, $vA, $vB", IIC_VecFP,
558 [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>;
559 def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
560 "vmrglw $vD, $vA, $vB", IIC_VecFP,
561 [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>;
563 def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm,
564 v4i32, v16i8, v4i32>;
565 def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm,
566 v4i32, v8i16, v4i32>;
567 def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs,
568 v4i32, v8i16, v4i32>;
569 def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm,
570 v4i32, v16i8, v4i32>;
571 def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm,
572 v4i32, v8i16, v4i32>;
573 def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs,
574 v4i32, v8i16, v4i32>;
576 let isCommutable = 1 in {
577 def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb,
579 def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh,
581 def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub,
583 def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh,
585 def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb,
587 def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh,
589 def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub,
591 def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh,
595 def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>;
596 def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>;
597 def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>;
598 def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>;
599 def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>;
600 def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
602 def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>;
604 def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
605 "vsubfp $vD, $vA, $vB", IIC_VecGeneral,
606 [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>;
607 def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
608 "vsububm $vD, $vA, $vB", IIC_VecGeneral,
609 [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>;
610 def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
611 "vsubuhm $vD, $vA, $vB", IIC_VecGeneral,
612 [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>;
613 def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
614 "vsubuwm $vD, $vA, $vB", IIC_VecGeneral,
615 [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>;
617 def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>;
618 def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>;
619 def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>;
620 def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>;
621 def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>;
622 def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>;
624 def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>;
625 def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>;
627 def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs,
628 v4i32, v16i8, v4i32>;
629 def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs,
630 v4i32, v8i16, v4i32>;
631 def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs,
632 v4i32, v16i8, v4i32>;
634 def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
635 "vnor $vD, $vA, $vB", IIC_VecFP,
636 [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA,
638 let isCommutable = 1 in {
639 def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
640 "vor $vD, $vA, $vB", IIC_VecFP,
641 [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>;
642 def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
643 "vxor $vD, $vA, $vB", IIC_VecFP,
644 [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>;
647 def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>;
648 def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>;
649 def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>;
651 def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >;
652 def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>;
654 def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>;
655 def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>;
656 def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>;
658 def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
659 "vspltb $vD, $vB, $UIMM", IIC_VecPerm,
661 (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>;
662 def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
663 "vsplth $vD, $vB, $UIMM", IIC_VecPerm,
665 (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>;
666 def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
667 "vspltw $vD, $vB, $UIMM", IIC_VecPerm,
669 (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>;
671 def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>;
672 def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>;
674 def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>;
675 def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>;
676 def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>;
677 def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>;
678 def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>;
679 def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>;
682 def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM),
683 "vspltisb $vD, $SIMM", IIC_VecPerm,
684 [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>;
685 def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM),
686 "vspltish $vD, $SIMM", IIC_VecPerm,
687 [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>;
688 def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM),
689 "vspltisw $vD, $SIMM", IIC_VecPerm,
690 [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>;
693 def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx,
695 def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss,
697 def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus,
699 def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss,
701 def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus,
703 def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
704 "vpkuhum $vD, $vA, $vB", IIC_VecFP,
706 (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>;
707 def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus,
709 def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
710 "vpkuwum $vD, $vA, $vB", IIC_VecFP,
712 (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>;
713 def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus,
717 def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx,
719 def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb,
721 def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh,
723 def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx,
725 def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb,
727 def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh,
731 // Altivec Comparisons.
733 class VCMP<bits<10> xo, string asmstr, ValueType Ty>
734 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
736 [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>;
737 class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
738 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
740 [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> {
745 // f32 element comparisons.0
746 def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>;
747 def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
748 def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
749 def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
750 def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
751 def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
752 def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
753 def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
755 // i8 element comparisons.
756 def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>;
757 def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>;
758 def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
759 def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
760 def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
761 def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
763 // i16 element comparisons.
764 def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
765 def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
766 def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
767 def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
768 def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
769 def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
771 // i32 element comparisons.
772 def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
773 def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
774 def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
775 def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
776 def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
777 def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
779 let isCodeGenOnly = 1 in {
780 def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
781 "vxor $vD, $vD, $vD", IIC_VecFP,
782 [(set v16i8:$vD, (v16i8 immAllZerosV))]>;
783 def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
784 "vxor $vD, $vD, $vD", IIC_VecFP,
785 [(set v8i16:$vD, (v8i16 immAllZerosV))]>;
786 def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
787 "vxor $vD, $vD, $vD", IIC_VecFP,
788 [(set v4i32:$vD, (v4i32 immAllZerosV))]>;
791 def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins),
792 "vspltisw $vD, -1", IIC_VecFP,
793 [(set v16i8:$vD, (v16i8 immAllOnesV))]>;
794 def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins),
795 "vspltisw $vD, -1", IIC_VecFP,
796 [(set v8i16:$vD, (v8i16 immAllOnesV))]>;
797 def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins),
798 "vspltisw $vD, -1", IIC_VecFP,
799 [(set v4i32:$vD, (v4i32 immAllOnesV))]>;
802 } // VALU Operations.
804 //===----------------------------------------------------------------------===//
805 // Additional Altivec Patterns
809 def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;
812 def : Pat<(store v4i32:$rS, xoaddr:$dst),
813 (STVX $rS, xoaddr:$dst)>;
816 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
817 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
818 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
819 def : Pat<(v16i8 (bitconvert (v2i64 VRRC:$src))), (v16i8 VRRC:$src)>;
821 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
822 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
823 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
824 def : Pat<(v8i16 (bitconvert (v2i64 VRRC:$src))), (v8i16 VRRC:$src)>;
826 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
827 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
828 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
829 def : Pat<(v4i32 (bitconvert (v2i64 VRRC:$src))), (v4i32 VRRC:$src)>;
831 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
832 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
833 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
834 def : Pat<(v4f32 (bitconvert (v2i64 VRRC:$src))), (v4f32 VRRC:$src)>;
836 def : Pat<(v2i64 (bitconvert (v16i8 VRRC:$src))), (v2i64 VRRC:$src)>;
837 def : Pat<(v2i64 (bitconvert (v8i16 VRRC:$src))), (v2i64 VRRC:$src)>;
838 def : Pat<(v2i64 (bitconvert (v4i32 VRRC:$src))), (v2i64 VRRC:$src)>;
839 def : Pat<(v2i64 (bitconvert (v4f32 VRRC:$src))), (v2i64 VRRC:$src)>;
843 // Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x)
844 def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef),
845 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>;
846 def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef),
848 def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef),
851 // Match vsldoi(y,x), vpkuwum(y,x), vpkuhum(y,x), i.e., swapped operands.
852 // These fragments are matched for little-endian, where the inputs must
853 // be swapped for correct semantics.
854 def:Pat<(vsldoi_swapped_shuffle:$in v16i8:$vA, v16i8:$vB),
855 (VSLDOI $vB, $vA, (VSLDOI_swapped_get_imm $in))>;
856 def:Pat<(vpkuwum_swapped_shuffle v16i8:$vA, v16i8:$vB),
858 def:Pat<(vpkuhum_swapped_shuffle v16i8:$vA, v16i8:$vB),
862 def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef),
864 def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef),
866 def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef),
868 def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef),
870 def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef),
872 def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef),
875 // Match vmrg*(y,x), i.e., swapped operands. These fragments
876 // are matched for little-endian, where the inputs must be
877 // swapped for correct semantics.
878 def:Pat<(vmrglb_swapped_shuffle v16i8:$vA, v16i8:$vB),
880 def:Pat<(vmrglh_swapped_shuffle v16i8:$vA, v16i8:$vB),
882 def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB),
884 def:Pat<(vmrghb_swapped_shuffle v16i8:$vA, v16i8:$vB),
886 def:Pat<(vmrghh_swapped_shuffle v16i8:$vA, v16i8:$vB),
888 def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB),
891 // Logical Operations
892 def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>;
894 def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)),
896 def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)),
899 def : Pat<(fmul v4f32:$vA, v4f32:$vB),
901 (v4i32 (VSLW (V_SETALLONES), (V_SETALLONES))))>;
903 // Fused multiply add and multiply sub for packed float. These are represented
904 // separately from the real instructions above, for operations that must have
905 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
906 def : Pat<(PPCvmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
907 (VMADDFP $A, $B, $C)>;
908 def : Pat<(PPCvnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
909 (VNMSUBFP $A, $B, $C)>;
911 def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
912 (VMADDFP $A, $B, $C)>;
913 def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
914 (VNMSUBFP $A, $B, $C)>;
916 def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC),
917 (VPERM $vA, $vB, $vC)>;
919 def : Pat<(PPCfre v4f32:$A), (VREFP $A)>;
920 def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>;
923 def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)),
924 (v16i8 (VSLB $vA, $vB))>;
925 def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)),
926 (v8i16 (VSLH $vA, $vB))>;
927 def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)),
928 (v4i32 (VSLW $vA, $vB))>;
930 def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)),
931 (v16i8 (VSRB $vA, $vB))>;
932 def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)),
933 (v8i16 (VSRH $vA, $vB))>;
934 def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)),
935 (v4i32 (VSRW $vA, $vB))>;
937 def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)),
938 (v16i8 (VSRAB $vA, $vB))>;
939 def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)),
940 (v8i16 (VSRAH $vA, $vB))>;
941 def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)),
942 (v4i32 (VSRAW $vA, $vB))>;
944 // Float to integer and integer to float conversions
945 def : Pat<(v4i32 (fp_to_sint v4f32:$vA)),
947 def : Pat<(v4i32 (fp_to_uint v4f32:$vA)),
949 def : Pat<(v4f32 (sint_to_fp v4i32:$vA)),
951 def : Pat<(v4f32 (uint_to_fp v4i32:$vA)),
954 // Floating-point rounding
955 def : Pat<(v4f32 (ffloor v4f32:$vA)),
957 def : Pat<(v4f32 (fceil v4f32:$vA)),
959 def : Pat<(v4f32 (ftrunc v4f32:$vA)),
961 def : Pat<(v4f32 (fnearbyint v4f32:$vA)),
966 def HasP8Altivec : Predicate<"PPCSubTarget->hasP8Altivec()">;
967 def HasP8Crypto : Predicate<"PPCSubTarget->hasP8Crypto()">;
968 let Predicates = [HasP8Altivec] in {
970 let isCommutable = 1 in {
971 def VMULESW : VX1_Int_Ty2<904, "vmulesw", int_ppc_altivec_vmulesw,
973 def VMULEUW : VX1_Int_Ty2<648, "vmuleuw", int_ppc_altivec_vmuleuw,
975 def VMULOSW : VX1_Int_Ty2<392, "vmulosw", int_ppc_altivec_vmulosw,
977 def VMULOUW : VX1_Int_Ty2<136, "vmulouw", int_ppc_altivec_vmulouw,
979 def VMULUWM : VXForm_1<137, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
980 "vmuluwm $vD, $vA, $vB", IIC_VecGeneral,
981 [(set v4i32:$vD, (mul v4i32:$vA, v4i32:$vB))]>;
982 def VMAXSD : VX1_Int_Ty<450, "vmaxsd", int_ppc_altivec_vmaxsd, v2i64>;
983 def VMAXUD : VX1_Int_Ty<194, "vmaxud", int_ppc_altivec_vmaxud, v2i64>;
984 def VMINSD : VX1_Int_Ty<962, "vminsd", int_ppc_altivec_vminsd, v2i64>;
985 def VMINUD : VX1_Int_Ty<706, "vminud", int_ppc_altivec_vminud, v2i64>;
989 def VRLD : VX1_Int_Ty<196, "vrld", int_ppc_altivec_vrld, v2i64>;
990 def VSLD : VXForm_1<1476, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
991 "vsld $vD, $vA, $vB", IIC_VecGeneral,
992 [(set v2i64:$vD, (shl v2i64:$vA, v2i64:$vB))]>;
993 def VSRD : VXForm_1<1732, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
994 "vsrd $vD, $vA, $vB", IIC_VecGeneral,
995 [(set v2i64:$vD, (srl v2i64:$vA, v2i64:$vB))]>;
996 def VSRAD : VXForm_1<964, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
997 "vsrad $vD, $vA, $vB", IIC_VecGeneral,
998 [(set v2i64:$vD, (sra v2i64:$vA, v2i64:$vB))]>;
1000 // Vector Integer Arithmetic Instructions
1001 let isCommutable = 1 in {
1002 def VADDUDM : VXForm_1<192, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1003 "vaddudm $vD, $vA, $vB", IIC_VecGeneral,
1004 [(set v2i64:$vD, (add v2i64:$vA, v2i64:$vB))]>;
1007 def VSUBUDM : VXForm_1<1216, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1008 "vsubudm $vD, $vA, $vB", IIC_VecGeneral,
1009 [(set v2i64:$vD, (sub v2i64:$vA, v2i64:$vB))]>;
1011 // Count Leading Zeros
1012 def VCLZB : VXForm_2<1794, (outs vrrc:$vD), (ins vrrc:$vB),
1013 "vclzb $vD, $vB", IIC_VecGeneral,
1014 [(set v16i8:$vD, (ctlz v16i8:$vB))]>;
1015 def VCLZH : VXForm_2<1858, (outs vrrc:$vD), (ins vrrc:$vB),
1016 "vclzh $vD, $vB", IIC_VecGeneral,
1017 [(set v8i16:$vD, (ctlz v8i16:$vB))]>;
1018 def VCLZW : VXForm_2<1922, (outs vrrc:$vD), (ins vrrc:$vB),
1019 "vclzw $vD, $vB", IIC_VecGeneral,
1020 [(set v4i32:$vD, (ctlz v4i32:$vB))]>;
1021 def VCLZD : VXForm_2<1986, (outs vrrc:$vD), (ins vrrc:$vB),
1022 "vclzd $vD, $vB", IIC_VecGeneral,
1023 [(set v2i64:$vD, (ctlz v2i64:$vB))]>;
1026 def VPOPCNTB : VXForm_2<1795, (outs vrrc:$vD), (ins vrrc:$vB),
1027 "vpopcntb $vD, $vB", IIC_VecGeneral,
1028 [(set v16i8:$vD, (ctpop v16i8:$vB))]>;
1029 def VPOPCNTH : VXForm_2<1859, (outs vrrc:$vD), (ins vrrc:$vB),
1030 "vpopcnth $vD, $vB", IIC_VecGeneral,
1031 [(set v8i16:$vD, (ctpop v8i16:$vB))]>;
1032 def VPOPCNTW : VXForm_2<1923, (outs vrrc:$vD), (ins vrrc:$vB),
1033 "vpopcntw $vD, $vB", IIC_VecGeneral,
1034 [(set v4i32:$vD, (ctpop v4i32:$vB))]>;
1035 def VPOPCNTD : VXForm_2<1987, (outs vrrc:$vD), (ins vrrc:$vB),
1036 "vpopcntd $vD, $vB", IIC_VecGeneral,
1037 [(set v2i64:$vD, (ctpop v2i64:$vB))]>;
1039 let isCommutable = 1 in {
1040 // FIXME: Use AddedComplexity > 400 to ensure these patterns match before the
1041 // VSX equivalents. We need to fix this up at some point. Two possible
1042 // solutions for this problem:
1043 // 1. Disable Altivec patterns that compete with VSX patterns using the
1044 // !HasVSX predicate. This essentially favours VSX over Altivec, in
1045 // hopes of reducing register pressure (larger register set using VSX
1046 // instructions than VMX instructions)
1047 // 2. Employ a more disciplined use of AddedComplexity, which would provide
1048 // more fine-grained control than option 1. This would be beneficial
1049 // if we find situations where Altivec is really preferred over VSX.
1050 def VEQV : VXForm_1<1668, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1051 "veqv $vD, $vA, $vB", IIC_VecGeneral,
1052 [(set v4i32:$vD, (vnot_ppc (xor v4i32:$vA, v4i32:$vB)))]>;
1053 def VNAND : VXForm_1<1412, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1054 "vnand $vD, $vA, $vB", IIC_VecGeneral,
1055 [(set v4i32:$vD, (vnot_ppc (and v4i32:$vA, v4i32:$vB)))]>;
1058 def VORC : VXForm_1<1348, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
1059 "vorc $vD, $vA, $vB", IIC_VecGeneral,
1060 [(set v4i32:$vD, (or v4i32:$vA,
1061 (vnot_ppc v4i32:$vB)))]>;
1063 // i64 element comparisons.
1064 def VCMPEQUD : VCMP <199, "vcmpequd $vD, $vA, $vB" , v2i64>;
1065 def VCMPEQUDo : VCMPo<199, "vcmpequd. $vD, $vA, $vB", v2i64>;
1066 def VCMPGTSD : VCMP <967, "vcmpgtsd $vD, $vA, $vB" , v2i64>;
1067 def VCMPGTSDo : VCMPo<967, "vcmpgtsd. $vD, $vA, $vB", v2i64>;
1068 def VCMPGTUD : VCMP <711, "vcmpgtud $vD, $vA, $vB" , v2i64>;
1069 def VCMPGTUDo : VCMPo<711, "vcmpgtud. $vD, $vA, $vB", v2i64>;
1071 // The cryptography instructions that do not require Category:Vector.Crypto
1072 def VPMSUMB : VX1_Int_Ty<1032, "vpmsumb",
1073 int_ppc_altivec_crypto_vpmsumb, v16i8>;
1074 def VPMSUMH : VX1_Int_Ty<1096, "vpmsumh",
1075 int_ppc_altivec_crypto_vpmsumh, v8i16>;
1076 def VPMSUMW : VX1_Int_Ty<1160, "vpmsumw",
1077 int_ppc_altivec_crypto_vpmsumw, v4i32>;
1078 def VPMSUMD : VX1_Int_Ty<1224, "vpmsumd",
1079 int_ppc_altivec_crypto_vpmsumd, v2i64>;
1080 def VPERMXOR : VA1a_Int_Ty<45, "vpermxor",
1081 int_ppc_altivec_crypto_vpermxor, v16i8>;
1083 } // end HasP8Altivec
1085 // Crypto instructions (from builtins)
1086 let Predicates = [HasP8Crypto] in {
1087 def VSHASIGMAW : VXCR_Int_Ty<1666, "vshasigmaw",
1088 int_ppc_altivec_crypto_vshasigmaw, v4i32>;
1089 def VSHASIGMAD : VXCR_Int_Ty<1730, "vshasigmad",
1090 int_ppc_altivec_crypto_vshasigmad, v2i64>;
1091 def VCIPHER : VX1_Int_Ty<1288, "vcipher", int_ppc_altivec_crypto_vcipher,
1093 def VCIPHERLAST : VX1_Int_Ty<1289, "vcipherlast",
1094 int_ppc_altivec_crypto_vcipherlast, v2i64>;
1095 def VNCIPHER : VX1_Int_Ty<1352, "vncipher",
1096 int_ppc_altivec_crypto_vncipher, v2i64>;
1097 def VNCIPHERLAST : VX1_Int_Ty<1353, "vncipherlast",
1098 int_ppc_altivec_crypto_vncipherlast, v2i64>;
1099 def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>;