1 //===- PPCInstrAltivec.td - The PowerPC Altivec Extension --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Altivec extension to the PowerPC instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Altivec transformation functions and pattern fragments.
18 /// VPKUHUM_shuffle_mask/VPKUWUM_shuffle_mask - Return true if this is a valid
19 /// shuffle mask for the VPKUHUM or VPKUWUM instructions.
20 def VPKUHUM_shuffle_mask : PatLeaf<(build_vector), [{
21 return PPC::isVPKUHUMShuffleMask(N);
23 def VPKUWUM_shuffle_mask : PatLeaf<(build_vector), [{
24 return PPC::isVPKUWUMShuffleMask(N);
27 def VSLDOI_get_imm : SDNodeXForm<build_vector, [{
28 return getI32Imm(PPC::isVSLDOIShuffleMask(N));
30 def VSLDOI_shuffle_mask : PatLeaf<(build_vector), [{
31 return PPC::isVSLDOIShuffleMask(N) != -1;
34 /// VSLDOI_rotate* - These are used to match vsldoi(X,X), which is turned into
35 /// vector_shuffle(X,undef,mask) by the dag combiner.
36 def VSLDOI_rotate_get_imm : SDNodeXForm<build_vector, [{
37 return getI32Imm(PPC::isVSLDOIRotateShuffleMask(N));
39 def VSLDOI_rotate_shuffle_mask : PatLeaf<(build_vector), [{
40 return PPC::isVSLDOIRotateShuffleMask(N) != -1;
41 }], VSLDOI_rotate_get_imm>;
44 // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
45 def VSPLTB_get_imm : SDNodeXForm<build_vector, [{
46 return getI32Imm(PPC::getVSPLTImmediate(N, 1));
48 def VSPLTB_shuffle_mask : PatLeaf<(build_vector), [{
49 return PPC::isSplatShuffleMask(N, 1);
51 def VSPLTH_get_imm : SDNodeXForm<build_vector, [{
52 return getI32Imm(PPC::getVSPLTImmediate(N, 2));
54 def VSPLTH_shuffle_mask : PatLeaf<(build_vector), [{
55 return PPC::isSplatShuffleMask(N, 2);
57 def VSPLTW_get_imm : SDNodeXForm<build_vector, [{
58 return getI32Imm(PPC::getVSPLTImmediate(N, 4));
60 def VSPLTW_shuffle_mask : PatLeaf<(build_vector), [{
61 return PPC::isSplatShuffleMask(N, 4);
65 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
66 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
68 PPC::isVecSplatImm(N, 1, &Val);
69 return getI32Imm(Val);
71 def vecspltisb : PatLeaf<(build_vector), [{
72 return PPC::isVecSplatImm(N, 1);
73 }], VSPLTISB_get_imm>;
75 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
76 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
78 PPC::isVecSplatImm(N, 2, &Val);
79 return getI32Imm(Val);
81 def vecspltish : PatLeaf<(build_vector), [{
82 return PPC::isVecSplatImm(N, 2);
83 }], VSPLTISH_get_imm>;
85 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
86 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
88 PPC::isVecSplatImm(N, 4, &Val);
89 return getI32Imm(Val);
91 def vecspltisw : PatLeaf<(build_vector), [{
92 return PPC::isVecSplatImm(N, 4);
93 }], VSPLTISW_get_imm>;
95 //===----------------------------------------------------------------------===//
96 // Helpers for defining instructions that directly correspond to intrinsics.
98 // VA1a_Int - A VAForm_1a intrinsic definition.
99 class VA1a_Int<bits<6> xo, string opc, Intrinsic IntID>
100 : VAForm_1a<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
101 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP,
102 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
104 // VX1_Int - A VXForm_1 intrinsic definition.
105 class VX1_Int<bits<11> xo, string opc, Intrinsic IntID>
106 : VXForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
107 !strconcat(opc, " $vD, $vA, $vB"), VecFP,
108 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>;
110 // VX2_Int - A VXForm_2 intrinsic definition.
111 class VX2_Int<bits<11> xo, string opc, Intrinsic IntID>
112 : VXForm_2<xo, (ops VRRC:$vD, VRRC:$vB),
113 !strconcat(opc, " $vD, $vB"), VecFP,
114 [(set VRRC:$vD, (IntID VRRC:$vB))]>;
116 //===----------------------------------------------------------------------===//
117 // Instruction Definitions.
119 def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
120 [(set VRRC:$rD, (v4f32 (undef)))]>;
122 let noResults = 1 in {
123 def DSS : DSS_Form<822, (ops u5imm:$A, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
124 "dss $STRM, $A", LdStGeneral /*FIXME*/, []>;
125 def DST : DSS_Form<342, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
126 "dst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>;
127 def DSTST : DSS_Form<374, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
128 "dstst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>;
131 def MFVSCR : VXForm_4<1540, (ops VRRC:$vD),
132 "mfvcr $vD", LdStGeneral,
133 [(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>;
134 def MTVSCR : VXForm_5<1604, (ops VRRC:$vB),
135 "mtvcr $vB", LdStGeneral,
136 [(int_ppc_altivec_mtvscr VRRC:$vB)]>;
138 let isLoad = 1, PPC970_Unit = 2 in { // Loads.
139 def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
140 "lvebx $vD, $src", LdStGeneral,
141 [(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
142 def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src),
143 "lvehx $vD, $src", LdStGeneral,
144 [(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
145 def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src),
146 "lvewx $vD, $src", LdStGeneral,
147 [(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
148 def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
149 "lvx $vD, $src", LdStGeneral,
150 [(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
151 def LVXL : XForm_1<31, 359, (ops VRRC:$vD, memrr:$src),
152 "lvxl $vD, $src", LdStGeneral,
153 [(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
156 def LVSL : XForm_1<31, 6, (ops VRRC:$vD, memrr:$src),
157 "lvsl $vD, $src", LdStGeneral,
158 [(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
160 def LVSR : XForm_1<31, 38, (ops VRRC:$vD, memrr:$src),
161 "lvsr $vD, $src", LdStGeneral,
162 [(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
165 let isStore = 1, noResults = 1, PPC970_Unit = 2 in { // Stores.
166 def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, memrr:$dst),
167 "stvebx $rS, $dst", LdStGeneral,
168 [(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>;
169 def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, memrr:$dst),
170 "stvehx $rS, $dst", LdStGeneral,
171 [(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>;
172 def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, memrr:$dst),
173 "stvewx $rS, $dst", LdStGeneral,
174 [(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>;
175 def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
176 "stvx $rS, $dst", LdStGeneral,
177 [(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>;
178 def STVXL : XForm_8<31, 487, (ops VRRC:$rS, memrr:$dst),
179 "stvxl $rS, $dst", LdStGeneral,
180 [(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>;
183 let PPC970_Unit = 5 in { // VALU Operations.
184 // VA-Form instructions. 3-input AltiVec ops.
185 def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
186 "vmaddfp $vD, $vA, $vC, $vB", VecFP,
187 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
189 Requires<[FPContractions]>;
190 def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
191 "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
192 [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
194 Requires<[FPContractions]>;
196 def VMHADDSHS : VA1a_Int<32, "vmhaddshs", int_ppc_altivec_vmhaddshs>;
197 def VMHRADDSHS : VA1a_Int<33, "vmhraddshs", int_ppc_altivec_vmhraddshs>;
198 def VMLADDUHM : VA1a_Int<34, "vmladduhm", int_ppc_altivec_vmladduhm>;
199 def VPERM : VA1a_Int<43, "vperm", int_ppc_altivec_vperm>;
200 def VSEL : VA1a_Int<42, "vsel", int_ppc_altivec_vsel>;
203 def VSLDOI : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH),
204 "vsldoi $vD, $vA, $vB, $SH", VecFP,
206 (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB,
207 VSLDOI_shuffle_mask:$SH))]>;
209 // VX-Form instructions. AltiVec arithmetic ops.
210 def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
211 "vaddfp $vD, $vA, $vB", VecFP,
212 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
214 def VADDUBM : VXForm_1<0, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
215 "vaddubm $vD, $vA, $vB", VecGeneral,
216 [(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>;
217 def VADDUHM : VXForm_1<64, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
218 "vadduhm $vD, $vA, $vB", VecGeneral,
219 [(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>;
220 def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
221 "vadduwm $vD, $vA, $vB", VecGeneral,
222 [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>;
224 def VADDCUW : VX1_Int<384, "vaddcuw", int_ppc_altivec_vaddcuw>;
225 def VADDSBS : VX1_Int<768, "vaddsbs", int_ppc_altivec_vaddsbs>;
226 def VADDSHS : VX1_Int<832, "vaddshs", int_ppc_altivec_vaddshs>;
227 def VADDSWS : VX1_Int<896, "vaddsws", int_ppc_altivec_vaddsws>;
228 def VADDUBS : VX1_Int<512, "vaddubs", int_ppc_altivec_vaddubs>;
229 def VADDUHS : VX1_Int<576, "vadduhs", int_ppc_altivec_vadduhs>;
230 def VADDUWS : VX1_Int<640, "vadduws", int_ppc_altivec_vadduws>;
233 def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
234 "vand $vD, $vA, $vB", VecFP,
235 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>;
236 def VANDC : VXForm_1<1092, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
237 "vandc $vD, $vA, $vB", VecFP,
238 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), (vnot VRRC:$vB)))]>;
240 def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
241 "vcfsx $vD, $vB, $UIMM", VecFP,
243 (int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>;
244 def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
245 "vcfux $vD, $vB, $UIMM", VecFP,
247 (int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>;
248 def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
249 "vctsxs $vD, $vB, $UIMM", VecFP,
251 (int_ppc_altivec_vctsxs VRRC:$vB, imm:$UIMM))]>;
252 def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
253 "vctuxs $vD, $vB, $UIMM", VecFP,
255 (int_ppc_altivec_vctuxs VRRC:$vB, imm:$UIMM))]>;
256 def VEXPTEFP : VX2_Int<394, "vexptefp", int_ppc_altivec_vexptefp>;
257 def VLOGEFP : VX2_Int<458, "vlogefp", int_ppc_altivec_vlogefp>;
259 def VAVGSB : VX1_Int<1282, "vavgsb", int_ppc_altivec_vavgsb>;
260 def VAVGSH : VX1_Int<1346, "vavgsh", int_ppc_altivec_vavgsh>;
261 def VAVGSW : VX1_Int<1410, "vavgsw", int_ppc_altivec_vavgsw>;
262 def VAVGUB : VX1_Int<1026, "vavgub", int_ppc_altivec_vavgub>;
263 def VAVGUH : VX1_Int<1090, "vavguh", int_ppc_altivec_vavguh>;
264 def VAVGUW : VX1_Int<1154, "vavguw", int_ppc_altivec_vavguw>;
266 def VMAXFP : VX1_Int<1034, "vmaxfp", int_ppc_altivec_vmaxfp>;
267 def VMAXSB : VX1_Int< 258, "vmaxsb", int_ppc_altivec_vmaxsb>;
268 def VMAXSH : VX1_Int< 322, "vmaxsh", int_ppc_altivec_vmaxsh>;
269 def VMAXSW : VX1_Int< 386, "vmaxsw", int_ppc_altivec_vmaxsw>;
270 def VMAXUB : VX1_Int< 2, "vmaxub", int_ppc_altivec_vmaxub>;
271 def VMAXUH : VX1_Int< 66, "vmaxuh", int_ppc_altivec_vmaxuh>;
272 def VMAXUW : VX1_Int< 130, "vmaxuw", int_ppc_altivec_vmaxuw>;
273 def VMINFP : VX1_Int<1098, "vminfp", int_ppc_altivec_vminfp>;
274 def VMINSB : VX1_Int< 770, "vminsb", int_ppc_altivec_vminsb>;
275 def VMINSH : VX1_Int< 834, "vminsh", int_ppc_altivec_vminsh>;
276 def VMINSW : VX1_Int< 896, "vminsw", int_ppc_altivec_vminsw>;
277 def VMINUB : VX1_Int< 514, "vminub", int_ppc_altivec_vminub>;
278 def VMINUH : VX1_Int< 578, "vminuh", int_ppc_altivec_vminuh>;
279 def VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>;
281 def VMRGHB : VX1_Int<12 , "vmrghb", int_ppc_altivec_vmrghb>;
282 def VMRGHH : VX1_Int<76 , "vmrghh", int_ppc_altivec_vmrghh>;
283 def VMRGHW : VX1_Int<140, "vmrghw", int_ppc_altivec_vmrghw>;
284 def VMRGLB : VX1_Int<268, "vmrglb", int_ppc_altivec_vmrglb>;
285 def VMRGLH : VX1_Int<332, "vmrglh", int_ppc_altivec_vmrglh>;
286 def VMRGLW : VX1_Int<396, "vmrglw", int_ppc_altivec_vmrglw>;
288 def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>;
289 def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>;
290 def VMSUMSHS : VA1a_Int<41, "vmsumshs", int_ppc_altivec_vmsumshs>;
291 def VMSUMUBM : VA1a_Int<36, "vmsumubm", int_ppc_altivec_vmsumubm>;
292 def VMSUMUHM : VA1a_Int<38, "vmsumuhm", int_ppc_altivec_vmsumuhm>;
293 def VMSUMUHS : VA1a_Int<39, "vmsumuhs", int_ppc_altivec_vmsumuhs>;
295 def VMULESB : VX1_Int<776, "vmulesb", int_ppc_altivec_vmulesb>;
296 def VMULESH : VX1_Int<840, "vmulesh", int_ppc_altivec_vmulesh>;
297 def VMULEUB : VX1_Int<520, "vmuleub", int_ppc_altivec_vmuleub>;
298 def VMULEUH : VX1_Int<584, "vmuleuh", int_ppc_altivec_vmuleuh>;
299 def VMULOSB : VX1_Int<264, "vmulosb", int_ppc_altivec_vmulosb>;
300 def VMULOSH : VX1_Int<328, "vmulosh", int_ppc_altivec_vmulosh>;
301 def VMULOUB : VX1_Int< 8, "vmuloub", int_ppc_altivec_vmuloub>;
302 def VMULOUH : VX1_Int< 72, "vmulouh", int_ppc_altivec_vmulouh>;
304 def VREFP : VX2_Int<266, "vrefp", int_ppc_altivec_vrefp>;
305 def VRFIM : VX2_Int<714, "vrfim", int_ppc_altivec_vrfim>;
306 def VRFIN : VX2_Int<522, "vrfin", int_ppc_altivec_vrfin>;
307 def VRFIP : VX2_Int<650, "vrfip", int_ppc_altivec_vrfip>;
308 def VRFIZ : VX2_Int<586, "vrfiz", int_ppc_altivec_vrfiz>;
309 def VRSQRTEFP : VX2_Int<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
311 def VSUBCUW : VX1_Int<74, "vsubcuw", int_ppc_altivec_vsubcuw>;
313 def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
314 "vsubfp $vD, $vA, $vB", VecGeneral,
315 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
316 def VSUBUBM : VXForm_1<1024, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
317 "vsububm $vD, $vA, $vB", VecGeneral,
318 [(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>;
319 def VSUBUHM : VXForm_1<1088, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
320 "vsubuhm $vD, $vA, $vB", VecGeneral,
321 [(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>;
322 def VSUBUWM : VXForm_1<1152, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
323 "vsubuwm $vD, $vA, $vB", VecGeneral,
324 [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>;
326 def VSUBSBS : VX1_Int<1792, "vsubsbs" , int_ppc_altivec_vsubsbs>;
327 def VSUBSHS : VX1_Int<1856, "vsubshs" , int_ppc_altivec_vsubshs>;
328 def VSUBSWS : VX1_Int<1920, "vsubsws" , int_ppc_altivec_vsubsws>;
329 def VSUBUBS : VX1_Int<1536, "vsububs" , int_ppc_altivec_vsububs>;
330 def VSUBUHS : VX1_Int<1600, "vsubuhs" , int_ppc_altivec_vsubuhs>;
331 def VSUBUWS : VX1_Int<1664, "vsubuws" , int_ppc_altivec_vsubuws>;
332 def VSUMSWS : VX1_Int<1928, "vsumsws" , int_ppc_altivec_vsumsws>;
333 def VSUM2SWS: VX1_Int<1672, "vsum2sws", int_ppc_altivec_vsum2sws>;
334 def VSUM4SBS: VX1_Int<1672, "vsum4sbs", int_ppc_altivec_vsum4sbs>;
335 def VSUM4SHS: VX1_Int<1608, "vsum4shs", int_ppc_altivec_vsum4shs>;
336 def VSUM4UBS: VX1_Int<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs>;
338 def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
339 "vnor $vD, $vA, $vB", VecFP,
340 [(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>;
341 def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
342 "vor $vD, $vA, $vB", VecFP,
343 [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>;
344 def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
345 "vxor $vD, $vA, $vB", VecFP,
346 [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
348 def VRLB : VX1_Int< 4, "vrlb", int_ppc_altivec_vrlb>;
349 def VRLH : VX1_Int< 68, "vrlh", int_ppc_altivec_vrlh>;
350 def VRLW : VX1_Int< 132, "vrlw", int_ppc_altivec_vrlw>;
352 def VSL : VX1_Int< 452, "vsl" , int_ppc_altivec_vsl >;
353 def VSLO : VX1_Int<1036, "vslo", int_ppc_altivec_vslo>;
354 def VSLB : VX1_Int< 260, "vslb", int_ppc_altivec_vslb>;
355 def VSLH : VX1_Int< 324, "vslh", int_ppc_altivec_vslh>;
356 def VSLW : VX1_Int< 388, "vslw", int_ppc_altivec_vslw>;
358 def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
359 "vspltb $vD, $vB, $UIMM", VecPerm,
360 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
361 VSPLTB_shuffle_mask:$UIMM))]>;
362 def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
363 "vsplth $vD, $vB, $UIMM", VecPerm,
364 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
365 VSPLTH_shuffle_mask:$UIMM))]>;
366 def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
367 "vspltw $vD, $vB, $UIMM", VecPerm,
368 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
369 VSPLTW_shuffle_mask:$UIMM))]>;
371 def VSR : VX1_Int< 708, "vsr" , int_ppc_altivec_vsr>;
372 def VSRO : VX1_Int<1100, "vsro" , int_ppc_altivec_vsro>;
373 def VSRAB : VX1_Int< 772, "vsrab", int_ppc_altivec_vsrab>;
374 def VSRAH : VX1_Int< 836, "vsrah", int_ppc_altivec_vsrah>;
375 def VSRAW : VX1_Int< 900, "vsraw", int_ppc_altivec_vsraw>;
376 def VSRB : VX1_Int< 516, "vsrb" , int_ppc_altivec_vsrb>;
377 def VSRH : VX1_Int< 580, "vsrh" , int_ppc_altivec_vsrh>;
378 def VSRW : VX1_Int< 644, "vsrw" , int_ppc_altivec_vsrw>;
381 def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM),
382 "vspltisb $vD, $SIMM", VecPerm,
383 [(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
384 def VSPLTISH : VXForm_3<844, (ops VRRC:$vD, s5imm:$SIMM),
385 "vspltish $vD, $SIMM", VecPerm,
386 [(set VRRC:$vD, (v4f32 vecspltish:$SIMM))]>;
387 def VSPLTISW : VXForm_3<908, (ops VRRC:$vD, s5imm:$SIMM),
388 "vspltisw $vD, $SIMM", VecPerm,
389 [(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
392 def VPKPX : VX1_Int<782, "vpkpx", int_ppc_altivec_vpkpx>;
393 def VPKSHSS : VX1_Int<398, "vpkshss", int_ppc_altivec_vpkshss>;
394 def VPKSHUS : VX1_Int<270, "vpkshus", int_ppc_altivec_vpkshus>;
395 def VPKSWSS : VX1_Int<462, "vpkswss", int_ppc_altivec_vpkswss>;
396 def VPKSWUS : VX1_Int<334, "vpkswus", int_ppc_altivec_vpkswus>;
397 def VPKUHUM : VXForm_1<14, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
398 "vpkuhum $vD, $vA, $vB", VecFP,
399 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
400 VRRC:$vB, VPKUHUM_shuffle_mask))]>;
401 def VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>;
402 def VPKUWUM : VXForm_1<78, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
403 "vpkuwum $vD, $vA, $vB", VecFP,
404 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
405 VRRC:$vB, VPKUWUM_shuffle_mask))]>;
406 def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>;
409 def VUPKHPX : VX2_Int<846, "vupkhpx", int_ppc_altivec_vupkhpx>;
410 def VUPKHSB : VX2_Int<526, "vupkhsb", int_ppc_altivec_vupkhsb>;
411 def VUPKHSH : VX2_Int<590, "vupkhsh", int_ppc_altivec_vupkhsh>;
412 def VUPKLPX : VX2_Int<974, "vupklpx", int_ppc_altivec_vupklpx>;
413 def VUPKLSB : VX2_Int<654, "vupklsb", int_ppc_altivec_vupklsb>;
414 def VUPKLSH : VX2_Int<718, "vupklsh", int_ppc_altivec_vupklsh>;
417 // Altivec Comparisons.
419 class VCMP<bits<10> xo, string asmstr, ValueType Ty>
420 : VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare,
421 [(set VRRC:$vD, (Ty (PPCvcmp VRRC:$vA, VRRC:$vB, xo)))]>;
422 class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
423 : VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare,
424 [(set VRRC:$vD, (Ty (PPCvcmp_o VRRC:$vA, VRRC:$vB, xo)))]> {
429 // f32 element comparisons.0
430 def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>;
431 def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
432 def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
433 def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
434 def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
435 def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
436 def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
437 def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
439 // i8 element comparisons.
440 def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>;
441 def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>;
442 def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
443 def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
444 def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
445 def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
447 // i16 element comparisons.
448 def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
449 def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
450 def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
451 def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
452 def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
453 def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
455 // i32 element comparisons.
456 def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
457 def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
458 def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
459 def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
460 def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
461 def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
463 def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
464 "vxor $vD, $vD, $vD", VecFP,
465 [(set VRRC:$vD, (v4f32 immAllZerosV))]>;
468 //===----------------------------------------------------------------------===//
469 // Additional Altivec Patterns
473 def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>;
474 def : Pat<(int_ppc_altivec_dssall), (DSS 1, 0, 0, 0)>;
475 def : Pat<(int_ppc_altivec_dst GPRC:$rA, GPRC:$rB, imm:$STRM),
476 (DST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
477 def : Pat<(int_ppc_altivec_dstt GPRC:$rA, GPRC:$rB, imm:$STRM),
478 (DST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
479 def : Pat<(int_ppc_altivec_dstst GPRC:$rA, GPRC:$rB, imm:$STRM),
480 (DSTST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
481 def : Pat<(int_ppc_altivec_dststt GPRC:$rA, GPRC:$rB, imm:$STRM),
482 (DSTST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
485 def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>;
486 def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>;
487 def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
488 def : Pat<(v16i8 immAllZerosV), (v16i8 (V_SET0))>;
489 def : Pat<(v8i16 immAllZerosV), (v8i16 (V_SET0))>;
490 def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0))>;
493 def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>;
494 def : Pat<(v8i16 (load xoaddr:$src)), (v8i16 (LVX xoaddr:$src))>;
495 def : Pat<(v4i32 (load xoaddr:$src)), (v4i32 (LVX xoaddr:$src))>;
496 def : Pat<(v4f32 (load xoaddr:$src)), (v4f32 (LVX xoaddr:$src))>;
499 def : Pat<(store (v16i8 VRRC:$rS), xoaddr:$dst),
500 (STVX (v16i8 VRRC:$rS), xoaddr:$dst)>;
501 def : Pat<(store (v8i16 VRRC:$rS), xoaddr:$dst),
502 (STVX (v8i16 VRRC:$rS), xoaddr:$dst)>;
503 def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
504 (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
505 def : Pat<(store (v4f32 VRRC:$rS), xoaddr:$dst),
506 (STVX (v4f32 VRRC:$rS), xoaddr:$dst)>;
509 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
510 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
511 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
513 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
514 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
515 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
517 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
518 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
519 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
521 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
522 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
523 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
528 def:Pat<(vector_shuffle (v16i8 VRRC:$vA),undef, VSLDOI_rotate_shuffle_mask:$in),
529 (VSLDOI VRRC:$vA, VRRC:$vA, VSLDOI_rotate_shuffle_mask:$in)>;
531 // Immediate vector formation with vsplti*.
532 def : Pat<(v16i8 vecspltisb:$invec), (v16i8 (VSPLTISB vecspltisb:$invec))>;
533 def : Pat<(v16i8 vecspltish:$invec), (v16i8 (VSPLTISH vecspltish:$invec))>;
534 def : Pat<(v16i8 vecspltisw:$invec), (v16i8 (VSPLTISW vecspltisw:$invec))>;
536 def : Pat<(v8i16 vecspltisb:$invec), (v8i16 (VSPLTISB vecspltisb:$invec))>;
537 def : Pat<(v8i16 vecspltish:$invec), (v8i16 (VSPLTISH vecspltish:$invec))>;
538 def : Pat<(v8i16 vecspltisw:$invec), (v8i16 (VSPLTISW vecspltisw:$invec))>;
540 def : Pat<(v4i32 vecspltisb:$invec), (v4i32 (VSPLTISB vecspltisb:$invec))>;
541 def : Pat<(v4i32 vecspltish:$invec), (v4i32 (VSPLTISH vecspltish:$invec))>;
542 def : Pat<(v4i32 vecspltisw:$invec), (v4i32 (VSPLTISW vecspltisw:$invec))>;
544 // Logical Operations
545 def : Pat<(v16i8 (vnot VRRC:$vA)), (v16i8 (VNOR VRRC:$vA, VRRC:$vA))>;
546 def : Pat<(v8i16 (vnot VRRC:$vA)), (v8i16 (VNOR VRRC:$vA, VRRC:$vA))>;
547 def : Pat<(v4i32 (vnot VRRC:$vA)), (v4i32 (VNOR VRRC:$vA, VRRC:$vA))>;
549 def : Pat<(v16i8 (and VRRC:$A, VRRC:$B)), (v16i8 (VAND VRRC:$A, VRRC:$B))>;
550 def : Pat<(v8i16 (and VRRC:$A, VRRC:$B)), (v8i16 (VAND VRRC:$A, VRRC:$B))>;
551 def : Pat<(v16i8 (or VRRC:$A, VRRC:$B)), (v16i8 (VOR VRRC:$A, VRRC:$B))>;
552 def : Pat<(v8i16 (or VRRC:$A, VRRC:$B)), (v8i16 (VOR VRRC:$A, VRRC:$B))>;
553 def : Pat<(v16i8 (xor VRRC:$A, VRRC:$B)), (v16i8 (VXOR VRRC:$A, VRRC:$B))>;
554 def : Pat<(v8i16 (xor VRRC:$A, VRRC:$B)), (v8i16 (VXOR VRRC:$A, VRRC:$B))>;
555 def : Pat<(v16i8 (vnot (or VRRC:$A, VRRC:$B))),(v16i8 (VNOR VRRC:$A, VRRC:$B))>;
556 def : Pat<(v8i16 (vnot (or VRRC:$A, VRRC:$B))),(v8i16 (VNOR VRRC:$A, VRRC:$B))>;
557 def : Pat<(v16i8 (and VRRC:$A, (vnot VRRC:$B))),
558 (v16i8 (VANDC VRRC:$A, VRRC:$B))>;
559 def : Pat<(v8i16 (and VRRC:$A, (vnot VRRC:$B))),
560 (v8i16 (VANDC VRRC:$A, VRRC:$B))>;
562 def : Pat<(fmul VRRC:$vA, VRRC:$vB),
563 (VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>;
565 // Fused multiply add and multiply sub for packed float. These are represented
566 // separately from the real instructions above, for operations that must have
567 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
568 def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
569 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
570 def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
571 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
573 def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
574 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
575 def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
576 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
578 def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC),
579 (v16i8 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;