1 //===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
21 def u16imm64 : Operand<i64> {
22 let PrintMethod = "printU16ImmOperand";
24 def symbolHi64 : Operand<i64> {
25 let PrintMethod = "printSymbolHi";
27 def symbolLo64 : Operand<i64> {
28 let PrintMethod = "printSymbolLo";
31 //===----------------------------------------------------------------------===//
32 // 64-bit transformation functions.
35 def SHL64 : SDNodeXForm<imm, [{
36 // Transformation function: 63 - imm
37 return getI32Imm(63 - N->getValue());
40 def SRL64 : SDNodeXForm<imm, [{
41 // Transformation function: 64 - imm
42 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
45 def HI32_48 : SDNodeXForm<imm, [{
46 // Transformation function: shift the immediate value down into the low bits.
47 return getI32Imm((unsigned short)(N->getValue() >> 32));
50 def HI48_64 : SDNodeXForm<imm, [{
51 // Transformation function: shift the immediate value down into the low bits.
52 return getI32Imm((unsigned short)(N->getValue() >> 48));
56 //===----------------------------------------------------------------------===//
57 // Pseudo instructions.
60 def IMPLICIT_DEF_G8RC : Pseudo<(ops G8RC:$rD), "; $rD = IMPLICIT_DEF_G8RC",
61 [(set G8RC:$rD, (undef))]>;
63 let Pattern = [(PPCmtctr G8RC:$rS)] in {
64 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (ops G8RC:$rS), "mtctr $rS", SprMTSPR>,
65 PPC970_DGroup_First, PPC970_Unit_FXU;
68 //===----------------------------------------------------------------------===//
69 // Fixed point instructions.
72 let PPC970_Unit = 1 in { // FXU Operations.
74 // Copies, extends, truncates.
75 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
76 "or $rA, $rS, $rB", IntGeneral,
78 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
79 "or $rA, $rS, $rB", IntGeneral,
82 def LI8 : DForm_2_r0<14, (ops G8RC:$rD, symbolLo64:$imm),
83 "li $rD, $imm", IntGeneral,
84 [(set G8RC:$rD, immSExt16:$imm)]>;
85 def LIS8 : DForm_2_r0<15, (ops G8RC:$rD, symbolHi64:$imm),
86 "lis $rD, $imm", IntGeneral,
87 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
90 def NAND8: XForm_6<31, 476, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
91 "nand $rA, $rS, $rB", IntGeneral,
92 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>;
93 def AND8 : XForm_6<31, 28, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
94 "and $rA, $rS, $rB", IntGeneral,
95 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>;
96 def ANDC8: XForm_6<31, 60, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
97 "andc $rA, $rS, $rB", IntGeneral,
98 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>;
99 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
100 "or $rA, $rS, $rB", IntGeneral,
101 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
102 def NOR8 : XForm_6<31, 124, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
103 "nor $rA, $rS, $rB", IntGeneral,
104 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>;
105 def ORC8 : XForm_6<31, 412, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
106 "orc $rA, $rS, $rB", IntGeneral,
107 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>;
108 def EQV8 : XForm_6<31, 284, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
109 "eqv $rA, $rS, $rB", IntGeneral,
110 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>;
111 def XOR8 : XForm_6<31, 316, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
112 "xor $rA, $rS, $rB", IntGeneral,
113 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
115 // Logical ops with immediate.
116 def ANDIo8 : DForm_4<28, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
117 "andi. $dst, $src1, $src2", IntGeneral,
118 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>,
120 def ANDISo8 : DForm_4<29, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
121 "andis. $dst, $src1, $src2", IntGeneral,
122 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
124 def ORI8 : DForm_4<24, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
125 "ori $dst, $src1, $src2", IntGeneral,
126 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
127 def ORIS8 : DForm_4<25, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
128 "oris $dst, $src1, $src2", IntGeneral,
129 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
130 def XORI8 : DForm_4<26, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
131 "xori $dst, $src1, $src2", IntGeneral,
132 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
133 def XORIS8 : DForm_4<27, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
134 "xoris $dst, $src1, $src2", IntGeneral,
135 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
139 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
140 "add $rT, $rA, $rB", IntGeneral,
141 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
142 def ADDI8 : DForm_2<14, (ops G8RC:$rD, G8RC:$rA, s16imm64:$imm),
143 "addi $rD, $rA, $imm", IntGeneral,
144 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>;
145 def ADDIS8 : DForm_2<15, (ops G8RC:$rD, G8RC:$rA, symbolHi64:$imm),
146 "addis $rD, $rA, $imm", IntGeneral,
147 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
149 def SUBFIC8: DForm_2< 8, (ops G8RC:$rD, G8RC:$rA, s16imm64:$imm),
150 "subfic $rD, $rA, $imm", IntGeneral,
151 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
152 def SUBF8 : XOForm_1<31, 40, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
153 "subf $rT, $rA, $rB", IntGeneral,
154 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
157 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
158 "mulhd $rT, $rA, $rB", IntMulHW,
159 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
160 def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
161 "mulhdu $rT, $rA, $rB", IntMulHWU,
162 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
164 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, G8RC:$rA, G8RC:$rB),
165 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
166 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, G8RC:$rA, G8RC:$rB),
167 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
168 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, G8RC:$rA, s16imm:$imm),
169 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
170 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, G8RC:$src1, u16imm:$src2),
171 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
173 def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
174 "sld $rA, $rS, $rB", IntRotateD,
175 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
176 def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
177 "srd $rA, $rS, $rB", IntRotateD,
178 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
179 def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
180 "srad $rA, $rS, $rB", IntRotateD,
181 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
182 def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
183 "extsw $rA, $rS", IntGeneral,
184 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
185 /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
186 def EXTSW_32 : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
187 "extsw $rA, $rS", IntGeneral,
188 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
189 def EXTSW_32_64 : XForm_11<31, 986, (ops G8RC:$rA, GPRC:$rS),
190 "extsw $rA, $rS", IntGeneral,
191 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64;
193 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
194 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
195 def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
196 "divd $rT, $rA, $rB", IntDivD,
197 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
198 PPC970_DGroup_First, PPC970_DGroup_Cracked;
199 def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
200 "divdu $rT, $rA, $rB", IntDivD,
201 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
202 PPC970_DGroup_First, PPC970_DGroup_Cracked;
203 def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
204 "mulld $rT, $rA, $rB", IntMulHD,
205 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
208 let isTwoAddress = 1, isCommutable = 1 in {
209 def RLDIMI : MDForm_1<30, 3,
210 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
211 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
215 // Rotate instructions.
216 def RLDICL : MDForm_1<30, 0,
217 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
218 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
220 def RLDICR : MDForm_1<30, 1,
221 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
222 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
224 } // End FXU Operations.
227 //===----------------------------------------------------------------------===//
228 // Load/Store instructions.
232 let isLoad = 1, PPC970_Unit = 2 in {
233 def LWA : DSForm_1<58, 2, (ops G8RC:$rD, memrix:$src),
234 "lwa $rD, $src", LdStLWA,
235 [(set G8RC:$rD, (sextload ixaddr:$src, i32))]>, isPPC64,
236 PPC970_DGroup_Cracked;
237 def LD : DSForm_2<58, 0, (ops G8RC:$rD, memrix:$src),
238 "ld $rD, $src", LdStLD,
239 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
241 def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src),
242 "lwax $rD, $src", LdStLHA,
243 [(set G8RC:$rD, (sextload xaddr:$src, i32))]>, isPPC64,
244 PPC970_DGroup_Cracked;
245 def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src),
246 "ldx $rD, $src", LdStLD,
247 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
248 def LWZ8 : DForm_1<32, (ops G8RC:$rD, memri:$src),
249 "lwz $rD, $src", LdStGeneral,
250 [(set G8RC:$rD, (zextload iaddr:$src, i32))]>, isPPC64;
252 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
253 def STD : DSForm_2<62, 0, (ops G8RC:$rS, memrix:$dst),
254 "std $rS, $dst", LdStSTD,
255 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
256 def STDX : XForm_8<31, 149, (ops G8RC:$rS, memrr:$dst),
257 "stdx $rS, $dst", LdStSTD,
258 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64,
259 PPC970_DGroup_Cracked;
260 def STDUX : XForm_8<31, 181, (ops G8RC:$rS, memrr:$dst),
261 "stdux $rS, $dst", LdStSTD,
264 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
265 def STD_32 : DSForm_2<62, 0, (ops GPRC:$rT, memrix:$dst),
266 "std $rT, $dst", LdStSTD,
267 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64;
268 def STDX_32 : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst),
269 "stdx $rT, $dst", LdStSTD,
270 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64,
271 PPC970_DGroup_Cracked;
276 //===----------------------------------------------------------------------===//
277 // Floating point instructions.
281 let PPC970_Unit = 3 in { // FPU Operations.
282 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
283 "fcfid $frD, $frB", FPGeneral,
284 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
285 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
286 "fctidz $frD, $frB", FPGeneral,
287 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
291 //===----------------------------------------------------------------------===//
292 // Instruction Patterns
295 // Immediate support.
297 // sext(0x0000_0000_0000_FFFF, i8) -> li imm
298 // sext(0x0000_0000_FFFF_0000, i16) -> lis imm>>16
300 // sext(0x0000_0000_FFFF_FFFF, i16) -> lis + ori
301 def sext_0x0000_0000_FFFF_FFFF_i16 : PatLeaf<(imm), [{
302 return N->getValue() == (uint64_t)(int32_t)N->getValue();
304 def : Pat<(i64 sext_0x0000_0000_FFFF_FFFF_i16:$imm),
305 (ORI8 (LIS8 (HI16 imm:$imm)), (LO16 imm:$imm))>;
307 // zext(0x0000_0000_FFFF_7FFF, i16) -> oris (li lo16(imm)), imm>>16
308 def zext_0x0000_0000_FFFF_7FFF_i16 : PatLeaf<(imm), [{
309 return (N->getValue() & 0xFFFFFFFF00008000ULL) == 0;
311 def : Pat<(i64 zext_0x0000_0000_FFFF_7FFF_i16:$imm),
312 (ORIS8 (LI8 (LO16 imm:$imm)), (HI16 imm:$imm))>;
314 // zext(0x0000_0000_FFFF_FFFF, i16) -> oris (ori (li 0), lo16(imm)), imm>>16
315 def zext_0x0000_0000_FFFF_FFFF_i16 : PatLeaf<(imm), [{
316 return (N->getValue() & 0xFFFFFFFF00000000ULL) == 0;
318 def : Pat<(i64 zext_0x0000_0000_FFFF_FFFF_i16:$imm),
319 (ORIS8 (ORI8 (LI8 0), (LO16 imm:$imm)), (HI16 imm:$imm))>;
321 // FIXME: Handle smart forms where the top 32-bits are set. Right now, stuff
322 // like 0xABCD0123BCDE0000 hits the case below, which produces ORI R, R, 0's!
324 // Fully general (and most expensive: 6 instructions!) immediate pattern.
325 def : Pat<(i64 imm:$imm),
330 (LIS8 (HI48_64 imm:$imm)),
337 // Extensions and truncates to/from 32-bit regs.
338 def : Pat<(i64 (zext GPRC:$in)),
339 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
340 def : Pat<(i64 (anyext GPRC:$in)),
341 (OR4To8 GPRC:$in, GPRC:$in)>;
342 def : Pat<(i32 (trunc G8RC:$in)),
343 (OR8To4 G8RC:$in, G8RC:$in)>;
346 def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
347 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
348 def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
349 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
351 // Hi and Lo for Darwin Global Addresses.
352 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
353 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
354 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
355 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
356 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
357 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
358 def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
359 (ADDIS8 G8RC:$in, tglobaladdr:$g)>;
360 def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)),
361 (ADDIS8 G8RC:$in, tconstpool:$g)>;
362 def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
363 (ADDIS8 G8RC:$in, tjumptable:$g)>;