1 //===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
21 def u16imm64 : Operand<i64> {
22 let PrintMethod = "printU16ImmOperand";
24 def symbolHi64 : Operand<i64> {
25 let PrintMethod = "printSymbolHi";
27 def symbolLo64 : Operand<i64> {
28 let PrintMethod = "printSymbolLo";
31 //===----------------------------------------------------------------------===//
32 // 64-bit transformation functions.
35 def SHL64 : SDNodeXForm<imm, [{
36 // Transformation function: 63 - imm
37 return getI32Imm(63 - N->getValue());
40 def SRL64 : SDNodeXForm<imm, [{
41 // Transformation function: 64 - imm
42 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
45 def HI32_48 : SDNodeXForm<imm, [{
46 // Transformation function: shift the immediate value down into the low bits.
47 return getI32Imm((unsigned short)(N->getValue() >> 32));
50 def HI48_64 : SDNodeXForm<imm, [{
51 // Transformation function: shift the immediate value down into the low bits.
52 return getI32Imm((unsigned short)(N->getValue() >> 48));
56 //===----------------------------------------------------------------------===//
57 // Pseudo instructions.
60 def IMPLICIT_DEF_G8RC : Pseudo<(ops G8RC:$rD), "; IMPLICIT_DEF_G8RC $rD",
61 [(set G8RC:$rD, (undef))]>;
64 //===----------------------------------------------------------------------===//
69 def MovePCtoLR8 : Pseudo<(ops piclabel:$label), "bl $label", []>,
73 let isCall = 1, noResults = 1, PPC970_Unit = 7,
74 // All calls clobber the PPC64 non-callee saved registers.
75 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
76 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
77 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
79 CR0,CR1,CR5,CR6,CR7] in {
80 // Convenient aliases for call instructions
81 def BL8_Macho : IForm<18, 0, 1,
82 (ops calltarget:$func, variable_ops),
83 "bl $func", BrB, []>; // See Pat patterns below.
85 def BLA8_Macho : IForm<18, 1, 1,
86 (ops aaddr:$func, variable_ops),
87 "bla $func", BrB, [(PPCcall_Macho (i64 imm:$func))]>;
90 // ELF 64 ABI Calls = Macho ABI Calls
91 // Used to define BL8_ELF and BLA8_ELF
92 let isCall = 1, noResults = 1, PPC970_Unit = 7,
93 // All calls clobber the PPC64 non-callee saved registers.
94 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
95 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
96 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
98 CR0,CR1,CR5,CR6,CR7] in {
99 // Convenient aliases for call instructions
100 def BL8_ELF : IForm<18, 0, 1,
101 (ops calltarget:$func, variable_ops),
102 "bl $func", BrB, []>; // See Pat patterns below.
104 def BLA8_ELF : IForm<18, 1, 1,
105 (ops aaddr:$func, variable_ops),
106 "bla $func", BrB, [(PPCcall_ELF (i64 imm:$func))]>;
111 def : Pat<(PPCcall_Macho (i64 tglobaladdr:$dst)),
112 (BL8_Macho tglobaladdr:$dst)>;
113 def : Pat<(PPCcall_Macho (i64 texternalsym:$dst)),
114 (BL8_Macho texternalsym:$dst)>;
116 def : Pat<(PPCcall_ELF (i64 tglobaladdr:$dst)),
117 (BL8_ELF tglobaladdr:$dst)>;
118 def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)),
119 (BL8_ELF texternalsym:$dst)>;
121 //===----------------------------------------------------------------------===//
122 // 64-bit SPR manipulation instrs.
124 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (ops G8RC:$rT), "mfctr $rT", SprMFSPR>,
125 PPC970_DGroup_First, PPC970_Unit_FXU;
126 let Pattern = [(PPCmtctr G8RC:$rS)] in {
127 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (ops G8RC:$rS), "mtctr $rS", SprMTSPR>,
128 PPC970_DGroup_First, PPC970_Unit_FXU;
131 def DYNALLOC8 : Pseudo<(ops G8RC:$result, G8RC:$negsize, memri:$fpsi),
132 "${:comment} DYNALLOC8 $result, $negsize, $fpsi",
134 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>,
137 def MTLR8 : XFXForm_7_ext<31, 467, 8, (ops G8RC:$rS), "mtlr $rS", SprMTSPR>,
138 PPC970_DGroup_First, PPC970_Unit_FXU;
139 def MFLR8 : XFXForm_1_ext<31, 339, 8, (ops G8RC:$rT), "mflr $rT", SprMFSPR>,
140 PPC970_DGroup_First, PPC970_Unit_FXU;
143 //===----------------------------------------------------------------------===//
144 // Fixed point instructions.
147 let PPC970_Unit = 1 in { // FXU Operations.
149 // Copies, extends, truncates.
150 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
151 "or $rA, $rS, $rB", IntGeneral,
153 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
154 "or $rA, $rS, $rB", IntGeneral,
157 def LI8 : DForm_2_r0<14, (ops G8RC:$rD, symbolLo64:$imm),
158 "li $rD, $imm", IntGeneral,
159 [(set G8RC:$rD, immSExt16:$imm)]>;
160 def LIS8 : DForm_2_r0<15, (ops G8RC:$rD, symbolHi64:$imm),
161 "lis $rD, $imm", IntGeneral,
162 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
165 def NAND8: XForm_6<31, 476, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
166 "nand $rA, $rS, $rB", IntGeneral,
167 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>;
168 def AND8 : XForm_6<31, 28, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
169 "and $rA, $rS, $rB", IntGeneral,
170 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>;
171 def ANDC8: XForm_6<31, 60, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
172 "andc $rA, $rS, $rB", IntGeneral,
173 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>;
174 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
175 "or $rA, $rS, $rB", IntGeneral,
176 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
177 def NOR8 : XForm_6<31, 124, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
178 "nor $rA, $rS, $rB", IntGeneral,
179 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>;
180 def ORC8 : XForm_6<31, 412, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
181 "orc $rA, $rS, $rB", IntGeneral,
182 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>;
183 def EQV8 : XForm_6<31, 284, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
184 "eqv $rA, $rS, $rB", IntGeneral,
185 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>;
186 def XOR8 : XForm_6<31, 316, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
187 "xor $rA, $rS, $rB", IntGeneral,
188 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
190 // Logical ops with immediate.
191 def ANDIo8 : DForm_4<28, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
192 "andi. $dst, $src1, $src2", IntGeneral,
193 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>,
195 def ANDISo8 : DForm_4<29, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
196 "andis. $dst, $src1, $src2", IntGeneral,
197 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
199 def ORI8 : DForm_4<24, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
200 "ori $dst, $src1, $src2", IntGeneral,
201 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
202 def ORIS8 : DForm_4<25, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
203 "oris $dst, $src1, $src2", IntGeneral,
204 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
205 def XORI8 : DForm_4<26, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
206 "xori $dst, $src1, $src2", IntGeneral,
207 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
208 def XORIS8 : DForm_4<27, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
209 "xoris $dst, $src1, $src2", IntGeneral,
210 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
212 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
213 "add $rT, $rA, $rB", IntGeneral,
214 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
216 def ADDC8 : XOForm_1<31, 10, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
217 "addc $rT, $rA, $rB", IntGeneral,
218 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>,
219 PPC970_DGroup_Cracked;
220 def ADDE8 : XOForm_1<31, 138, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
221 "adde $rT, $rA, $rB", IntGeneral,
222 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>;
224 def ADDI8 : DForm_2<14, (ops G8RC:$rD, G8RC:$rA, s16imm64:$imm),
225 "addi $rD, $rA, $imm", IntGeneral,
226 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>;
227 def ADDIS8 : DForm_2<15, (ops G8RC:$rD, G8RC:$rA, symbolHi64:$imm),
228 "addis $rD, $rA, $imm", IntGeneral,
229 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
231 def SUBFIC8: DForm_2< 8, (ops G8RC:$rD, G8RC:$rA, s16imm64:$imm),
232 "subfic $rD, $rA, $imm", IntGeneral,
233 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
234 def SUBF8 : XOForm_1<31, 40, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
235 "subf $rT, $rA, $rB", IntGeneral,
236 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
238 def SUBFC8 : XOForm_1<31, 8, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
239 "subfc $rT, $rA, $rB", IntGeneral,
240 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>,
241 PPC970_DGroup_Cracked;
243 def SUBFE8 : XOForm_1<31, 136, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
244 "subfe $rT, $rA, $rB", IntGeneral,
245 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>;
246 def ADDME8 : XOForm_3<31, 234, 0, (ops G8RC:$rT, G8RC:$rA),
247 "addme $rT, $rA", IntGeneral,
248 [(set G8RC:$rT, (adde G8RC:$rA, immAllOnes))]>;
249 def ADDZE8 : XOForm_3<31, 202, 0, (ops G8RC:$rT, G8RC:$rA),
250 "addze $rT, $rA", IntGeneral,
251 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>;
252 def NEG8 : XOForm_3<31, 104, 0, (ops G8RC:$rT, G8RC:$rA),
253 "neg $rT, $rA", IntGeneral,
254 [(set G8RC:$rT, (ineg G8RC:$rA))]>;
255 def SUBFME8 : XOForm_3<31, 232, 0, (ops G8RC:$rT, G8RC:$rA),
256 "subfme $rT, $rA", IntGeneral,
257 [(set G8RC:$rT, (sube immAllOnes, G8RC:$rA))]>;
258 def SUBFZE8 : XOForm_3<31, 200, 0, (ops G8RC:$rT, G8RC:$rA),
259 "subfze $rT, $rA", IntGeneral,
260 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>;
264 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
265 "mulhd $rT, $rA, $rB", IntMulHW,
266 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
267 def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
268 "mulhdu $rT, $rA, $rB", IntMulHWU,
269 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
271 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, G8RC:$rA, G8RC:$rB),
272 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
273 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, G8RC:$rA, G8RC:$rB),
274 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
275 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, G8RC:$rA, s16imm:$imm),
276 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
277 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, G8RC:$src1, u16imm:$src2),
278 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
280 def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB),
281 "sld $rA, $rS, $rB", IntRotateD,
282 [(set G8RC:$rA, (shl G8RC:$rS, GPRC:$rB))]>, isPPC64;
283 def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB),
284 "srd $rA, $rS, $rB", IntRotateD,
285 [(set G8RC:$rA, (srl G8RC:$rS, GPRC:$rB))]>, isPPC64;
286 def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB),
287 "srad $rA, $rS, $rB", IntRotateD,
288 [(set G8RC:$rA, (sra G8RC:$rS, GPRC:$rB))]>, isPPC64;
290 def EXTSB8 : XForm_11<31, 954, (ops G8RC:$rA, G8RC:$rS),
291 "extsb $rA, $rS", IntGeneral,
292 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>;
293 def EXTSH8 : XForm_11<31, 922, (ops G8RC:$rA, G8RC:$rS),
294 "extsh $rA, $rS", IntGeneral,
295 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>;
297 def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
298 "extsw $rA, $rS", IntGeneral,
299 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
300 /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
301 def EXTSW_32 : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
302 "extsw $rA, $rS", IntGeneral,
303 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
304 def EXTSW_32_64 : XForm_11<31, 986, (ops G8RC:$rA, GPRC:$rS),
305 "extsw $rA, $rS", IntGeneral,
306 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64;
308 def SRADI : XSForm_1<31, 413, (ops G8RC:$rA, G8RC:$rS, u6imm:$SH),
309 "sradi $rA, $rS, $SH", IntRotateD,
310 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64;
311 def CNTLZD : XForm_11<31, 58, (ops G8RC:$rA, G8RC:$rS),
312 "cntlzd $rA, $rS", IntGeneral,
313 [(set G8RC:$rA, (ctlz G8RC:$rS))]>;
315 def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
316 "divd $rT, $rA, $rB", IntDivD,
317 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
318 PPC970_DGroup_First, PPC970_DGroup_Cracked;
319 def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
320 "divdu $rT, $rA, $rB", IntDivD,
321 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
322 PPC970_DGroup_First, PPC970_DGroup_Cracked;
323 def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
324 "mulld $rT, $rA, $rB", IntMulHD,
325 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
328 let isCommutable = 1 in {
329 def RLDIMI : MDForm_1<30, 3,
330 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
331 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
332 []>, isPPC64, RegConstraint<"$rSi = $rA">,
336 // Rotate instructions.
337 def RLDICL : MDForm_1<30, 0,
338 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
339 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
341 def RLDICR : MDForm_1<30, 1,
342 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
343 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
345 } // End FXU Operations.
348 //===----------------------------------------------------------------------===//
349 // Load/Store instructions.
353 // Sign extending loads.
354 let isLoad = 1, PPC970_Unit = 2 in {
355 def LHA8: DForm_1<42, (ops G8RC:$rD, memri:$src),
356 "lha $rD, $src", LdStLHA,
357 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>,
358 PPC970_DGroup_Cracked;
359 def LWA : DSForm_1<58, 2, (ops G8RC:$rD, memrix:$src),
360 "lwa $rD, $src", LdStLWA,
361 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64,
362 PPC970_DGroup_Cracked;
363 def LHAX8: XForm_1<31, 343, (ops G8RC:$rD, memrr:$src),
364 "lhax $rD, $src", LdStLHA,
365 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>,
366 PPC970_DGroup_Cracked;
367 def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src),
368 "lwax $rD, $src", LdStLHA,
369 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
370 PPC970_DGroup_Cracked;
373 def LHAU8 : DForm_1<43, (ops G8RC:$rD, ptr_rc:$ea_result, symbolLo:$disp,
375 "lhau $rD, $disp($rA)", LdStGeneral,
376 []>, RegConstraint<"$rA = $ea_result">,
377 NoEncode<"$ea_result">;
382 // Zero extending loads.
383 let isLoad = 1, PPC970_Unit = 2 in {
384 def LBZ8 : DForm_1<34, (ops G8RC:$rD, memri:$src),
385 "lbz $rD, $src", LdStGeneral,
386 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
387 def LHZ8 : DForm_1<40, (ops G8RC:$rD, memri:$src),
388 "lhz $rD, $src", LdStGeneral,
389 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>;
390 def LWZ8 : DForm_1<32, (ops G8RC:$rD, memri:$src),
391 "lwz $rD, $src", LdStGeneral,
392 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
394 def LBZX8 : XForm_1<31, 87, (ops G8RC:$rD, memrr:$src),
395 "lbzx $rD, $src", LdStGeneral,
396 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>;
397 def LHZX8 : XForm_1<31, 279, (ops G8RC:$rD, memrr:$src),
398 "lhzx $rD, $src", LdStGeneral,
399 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>;
400 def LWZX8 : XForm_1<31, 23, (ops G8RC:$rD, memrr:$src),
401 "lwzx $rD, $src", LdStGeneral,
402 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>;
406 def LBZU8 : DForm_1<35, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr),
407 "lbzu $rD, $addr", LdStGeneral,
408 []>, RegConstraint<"$addr.reg = $ea_result">,
409 NoEncode<"$ea_result">;
410 def LHZU8 : DForm_1<41, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr),
411 "lhzu $rD, $addr", LdStGeneral,
412 []>, RegConstraint<"$addr.reg = $ea_result">,
413 NoEncode<"$ea_result">;
414 def LWZU8 : DForm_1<33, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr),
415 "lwzu $rD, $addr", LdStGeneral,
416 []>, RegConstraint<"$addr.reg = $ea_result">,
417 NoEncode<"$ea_result">;
421 // Full 8-byte loads.
422 let isLoad = 1, PPC970_Unit = 2 in {
423 def LD : DSForm_1<58, 0, (ops G8RC:$rD, memrix:$src),
424 "ld $rD, $src", LdStLD,
425 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
426 def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src),
427 "ldx $rD, $src", LdStLD,
428 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
430 def LDU : DSForm_1<58, 1, (ops G8RC:$rD, ptr_rc:$ea_result, memrix:$addr),
431 "ldu $rD, $addr", LdStLD,
432 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
433 NoEncode<"$ea_result">;
437 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
438 // Truncating stores.
439 def STB8 : DForm_1<38, (ops G8RC:$rS, memri:$src),
440 "stb $rS, $src", LdStGeneral,
441 [(truncstorei8 G8RC:$rS, iaddr:$src)]>;
442 def STH8 : DForm_1<44, (ops G8RC:$rS, memri:$src),
443 "sth $rS, $src", LdStGeneral,
444 [(truncstorei16 G8RC:$rS, iaddr:$src)]>;
445 def STW8 : DForm_1<36, (ops G8RC:$rS, memri:$src),
446 "stw $rS, $src", LdStGeneral,
447 [(truncstorei32 G8RC:$rS, iaddr:$src)]>;
448 def STBX8 : XForm_8<31, 215, (ops G8RC:$rS, memrr:$dst),
449 "stbx $rS, $dst", LdStGeneral,
450 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>,
451 PPC970_DGroup_Cracked;
452 def STHX8 : XForm_8<31, 407, (ops G8RC:$rS, memrr:$dst),
453 "sthx $rS, $dst", LdStGeneral,
454 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>,
455 PPC970_DGroup_Cracked;
456 def STWX8 : XForm_8<31, 151, (ops G8RC:$rS, memrr:$dst),
457 "stwx $rS, $dst", LdStGeneral,
458 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>,
459 PPC970_DGroup_Cracked;
460 // Normal 8-byte stores.
461 def STD : DSForm_1<62, 0, (ops G8RC:$rS, memrix:$dst),
462 "std $rS, $dst", LdStSTD,
463 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
464 def STDX : XForm_8<31, 149, (ops G8RC:$rS, memrr:$dst),
465 "stdx $rS, $dst", LdStSTD,
466 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64,
467 PPC970_DGroup_Cracked;
470 let isStore = 1, PPC970_Unit = 2 in {
472 def STBU8 : DForm_1<38, (ops ptr_rc:$ea_res, G8RC:$rS,
473 symbolLo:$ptroff, ptr_rc:$ptrreg),
474 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
475 [(set ptr_rc:$ea_res,
476 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg,
477 iaddroff:$ptroff))]>,
478 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
479 def STHU8 : DForm_1<45, (ops ptr_rc:$ea_res, G8RC:$rS,
480 symbolLo:$ptroff, ptr_rc:$ptrreg),
481 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
482 [(set ptr_rc:$ea_res,
483 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg,
484 iaddroff:$ptroff))]>,
485 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
486 def STWU8 : DForm_1<37, (ops ptr_rc:$ea_res, G8RC:$rS,
487 symbolLo:$ptroff, ptr_rc:$ptrreg),
488 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
489 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
490 iaddroff:$ptroff))]>,
491 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
494 def STDU : DSForm_1<62, 1, (ops ptr_rc:$ea_res, G8RC:$rS,
495 s16immX4:$ptroff, ptr_rc:$ptrreg),
496 "stdu $rS, $ptroff($ptrreg)", LdStSTD,
497 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
498 iaddroff:$ptroff))]>,
499 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
504 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
506 def STDUX : XForm_8<31, 181, (ops G8RC:$rS, memrr:$dst),
507 "stdux $rS, $dst", LdStSTD,
511 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
512 def STD_32 : DSForm_1<62, 0, (ops GPRC:$rT, memrix:$dst),
513 "std $rT, $dst", LdStSTD,
514 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64;
515 def STDX_32 : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst),
516 "stdx $rT, $dst", LdStSTD,
517 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64,
518 PPC970_DGroup_Cracked;
523 //===----------------------------------------------------------------------===//
524 // Floating point instructions.
528 let PPC970_Unit = 3 in { // FPU Operations.
529 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
530 "fcfid $frD, $frB", FPGeneral,
531 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
532 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
533 "fctidz $frD, $frB", FPGeneral,
534 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
538 //===----------------------------------------------------------------------===//
539 // Instruction Patterns
542 // Extensions and truncates to/from 32-bit regs.
543 def : Pat<(i64 (zext GPRC:$in)),
544 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
545 def : Pat<(i64 (anyext GPRC:$in)),
546 (OR4To8 GPRC:$in, GPRC:$in)>;
547 def : Pat<(i32 (trunc G8RC:$in)),
548 (OR8To4 G8RC:$in, G8RC:$in)>;
550 // Extending loads with i64 targets.
551 def : Pat<(zextloadi1 iaddr:$src),
553 def : Pat<(zextloadi1 xaddr:$src),
555 def : Pat<(extloadi1 iaddr:$src),
557 def : Pat<(extloadi1 xaddr:$src),
559 def : Pat<(extloadi8 iaddr:$src),
561 def : Pat<(extloadi8 xaddr:$src),
563 def : Pat<(extloadi16 iaddr:$src),
565 def : Pat<(extloadi16 xaddr:$src),
567 def : Pat<(extloadi32 iaddr:$src),
569 def : Pat<(extloadi32 xaddr:$src),
573 def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
574 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
575 def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
576 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
578 // Hi and Lo for Darwin Global Addresses.
579 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
580 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
581 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
582 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
583 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
584 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
585 def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
586 (ADDIS8 G8RC:$in, tglobaladdr:$g)>;
587 def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)),
588 (ADDIS8 G8RC:$in, tconstpool:$g)>;
589 def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
590 (ADDIS8 G8RC:$in, tjumptable:$g)>;