1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
21 def u16imm64 : Operand<i64> {
22 let PrintMethod = "printU16ImmOperand";
24 def symbolHi64 : Operand<i64> {
25 let PrintMethod = "printSymbolHi";
26 let EncoderMethod = "getHA16Encoding";
28 def symbolLo64 : Operand<i64> {
29 let PrintMethod = "printSymbolLo";
30 let EncoderMethod = "getLO16Encoding";
33 //===----------------------------------------------------------------------===//
34 // 64-bit transformation functions.
37 def SHL64 : SDNodeXForm<imm, [{
38 // Transformation function: 63 - imm
39 return getI32Imm(63 - N->getZExtValue());
42 def SRL64 : SDNodeXForm<imm, [{
43 // Transformation function: 64 - imm
44 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
47 def HI32_48 : SDNodeXForm<imm, [{
48 // Transformation function: shift the immediate value down into the low bits.
49 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
52 def HI48_64 : SDNodeXForm<imm, [{
53 // Transformation function: shift the immediate value down into the low bits.
54 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
58 //===----------------------------------------------------------------------===//
63 def MovePCtoLR8 : Pseudo<(outs), (ins), "", []>,
67 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
68 // Convenient aliases for call instructions
70 def BL8_Darwin : IForm<18, 0, 1,
71 (outs), (ins calltarget:$func, variable_ops),
72 "bl $func", BrB, []>; // See Pat patterns below.
73 def BLA8_Darwin : IForm<18, 1, 1,
74 (outs), (ins aaddr:$func, variable_ops),
75 "bla $func", BrB, [(PPCcall_Darwin (i64 imm:$func))]>;
77 let Uses = [CTR8, RM] in {
78 def BCTRL8_Darwin : XLForm_2_ext<19, 528, 20, 0, 1,
79 (outs), (ins variable_ops),
81 [(PPCbctrl_Darwin)]>, Requires<[In64BitMode]>;
85 // ELF 64 ABI Calls = Darwin ABI Calls
86 // Used to define BL8_ELF and BLA8_ELF
87 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
88 // Convenient aliases for call instructions
90 def BL8_ELF : IForm<18, 0, 1,
91 (outs), (ins calltarget:$func, variable_ops),
92 "bl $func", BrB, []>; // See Pat patterns below.
93 def BLA8_ELF : IForm<18, 1, 1,
94 (outs), (ins aaddr:$func, variable_ops),
95 "bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>;
97 let Uses = [X11, CTR8, RM] in {
98 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
99 (outs), (ins variable_ops),
101 [(PPCbctrl_SVR4)]>, Requires<[In64BitMode]>;
107 def : Pat<(PPCcall_Darwin (i64 tglobaladdr:$dst)),
108 (BL8_Darwin tglobaladdr:$dst)>;
109 def : Pat<(PPCcall_Darwin (i64 texternalsym:$dst)),
110 (BL8_Darwin texternalsym:$dst)>;
112 def : Pat<(PPCcall_SVR4 (i64 tglobaladdr:$dst)),
113 (BL8_ELF tglobaladdr:$dst)>;
114 def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst)),
115 (BL8_ELF texternalsym:$dst)>;
120 let usesCustomInserter = 1 in {
121 let Defs = [CR0] in {
122 def ATOMIC_LOAD_ADD_I64 : Pseudo<
123 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
124 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>;
125 def ATOMIC_LOAD_SUB_I64 : Pseudo<
126 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
127 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>;
128 def ATOMIC_LOAD_OR_I64 : Pseudo<
129 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
130 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>;
131 def ATOMIC_LOAD_XOR_I64 : Pseudo<
132 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
133 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>;
134 def ATOMIC_LOAD_AND_I64 : Pseudo<
135 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
136 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>;
137 def ATOMIC_LOAD_NAND_I64 : Pseudo<
138 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
139 [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>;
141 def ATOMIC_CMP_SWAP_I64 : Pseudo<
142 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "",
144 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>;
146 def ATOMIC_SWAP_I64 : Pseudo<
147 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "",
148 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>;
152 // Instructions to support atomic operations
153 def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr),
154 "ldarx $rD, $ptr", LdStLDARX,
155 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>;
158 def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst),
159 "stdcx. $rS, $dst", LdStSTDCX,
160 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>,
163 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
164 def TCRETURNdi8 :Pseudo< (outs),
165 (ins calltarget:$dst, i32imm:$offset, variable_ops),
166 "#TC_RETURNd8 $dst $offset",
169 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
170 def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops),
171 "#TC_RETURNa8 $func $offset",
172 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
174 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
175 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset, variable_ops),
176 "#TC_RETURNr8 $dst $offset",
180 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
181 isIndirectBranch = 1, isCall = 1, Uses = [CTR8, RM] in {
182 let isReturn = 1 in {
183 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
184 Requires<[In64BitMode]>;
187 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
188 Requires<[In64BitMode]>;
192 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
193 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
194 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
199 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
200 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
201 def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
205 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
206 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
208 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
209 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
211 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
212 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
214 // 64-but CR instructions
215 def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS),
216 "mtcrf $FXM, $rS", BrMCRX>,
217 PPC970_MicroCode, PPC970_Unit_CRU;
219 def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM),
221 PPC970_MicroCode, PPC970_Unit_CRU;
223 def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins),
224 "mfcr $rT", SprMFCR>,
225 PPC970_MicroCode, PPC970_Unit_CRU;
227 //===----------------------------------------------------------------------===//
228 // 64-bit SPR manipulation instrs.
230 let Uses = [CTR8] in {
231 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins),
232 "mfctr $rT", SprMFSPR>,
233 PPC970_DGroup_First, PPC970_Unit_FXU;
235 let Pattern = [(PPCmtctr G8RC:$rS)], Defs = [CTR8] in {
236 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
237 "mtctr $rS", SprMTSPR>,
238 PPC970_DGroup_First, PPC970_Unit_FXU;
241 let Defs = [X1], Uses = [X1] in
242 def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"",
244 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>;
246 let Defs = [LR8] in {
247 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS),
248 "mtlr $rS", SprMTSPR>,
249 PPC970_DGroup_First, PPC970_Unit_FXU;
251 let Uses = [LR8] in {
252 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins),
253 "mflr $rT", SprMFSPR>,
254 PPC970_DGroup_First, PPC970_Unit_FXU;
257 //===----------------------------------------------------------------------===//
258 // Fixed point instructions.
261 let PPC970_Unit = 1 in { // FXU Operations.
263 // Copies, extends, truncates.
264 def OR4To8 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB),
265 "or $rA, $rS, $rB", IntGeneral,
267 def OR8To4 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB),
268 "or $rA, $rS, $rB", IntGeneral,
271 def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm),
272 "li $rD, $imm", IntGeneral,
273 [(set G8RC:$rD, immSExt16:$imm)]>;
274 def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm),
275 "lis $rD, $imm", IntGeneral,
276 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
279 def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
280 "nand $rA, $rS, $rB", IntGeneral,
281 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>;
282 def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
283 "and $rA, $rS, $rB", IntGeneral,
284 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>;
285 def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
286 "andc $rA, $rS, $rB", IntGeneral,
287 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>;
288 def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
289 "or $rA, $rS, $rB", IntGeneral,
290 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
291 def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
292 "nor $rA, $rS, $rB", IntGeneral,
293 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>;
294 def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
295 "orc $rA, $rS, $rB", IntGeneral,
296 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>;
297 def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
298 "eqv $rA, $rS, $rB", IntGeneral,
299 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>;
300 def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
301 "xor $rA, $rS, $rB", IntGeneral,
302 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
304 // Logical ops with immediate.
305 def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
306 "andi. $dst, $src1, $src2", IntGeneral,
307 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>,
309 def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
310 "andis. $dst, $src1, $src2", IntGeneral,
311 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
313 def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
314 "ori $dst, $src1, $src2", IntGeneral,
315 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
316 def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
317 "oris $dst, $src1, $src2", IntGeneral,
318 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
319 def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
320 "xori $dst, $src1, $src2", IntGeneral,
321 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
322 def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
323 "xoris $dst, $src1, $src2", IntGeneral,
324 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
326 def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
327 "add $rT, $rA, $rB", IntGeneral,
328 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
330 let Defs = [CARRY] in {
331 def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
332 "addc $rT, $rA, $rB", IntGeneral,
333 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>,
334 PPC970_DGroup_Cracked;
335 def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
336 "addic $rD, $rA, $imm", IntGeneral,
337 [(set G8RC:$rD, (addc G8RC:$rA, immSExt16:$imm))]>;
339 def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
340 "addi $rD, $rA, $imm", IntGeneral,
341 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>;
342 def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm),
343 "addis $rD, $rA, $imm", IntGeneral,
344 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
346 let Defs = [CARRY] in {
347 def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
348 "subfic $rD, $rA, $imm", IntGeneral,
349 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
350 def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
351 "subfc $rT, $rA, $rB", IntGeneral,
352 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>,
353 PPC970_DGroup_Cracked;
355 def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
356 "subf $rT, $rA, $rB", IntGeneral,
357 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
358 def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA),
359 "neg $rT, $rA", IntGeneral,
360 [(set G8RC:$rT, (ineg G8RC:$rA))]>;
361 let Uses = [CARRY], Defs = [CARRY] in {
362 def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
363 "adde $rT, $rA, $rB", IntGeneral,
364 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>;
365 def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA),
366 "addme $rT, $rA", IntGeneral,
367 [(set G8RC:$rT, (adde G8RC:$rA, -1))]>;
368 def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA),
369 "addze $rT, $rA", IntGeneral,
370 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>;
371 def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
372 "subfe $rT, $rA, $rB", IntGeneral,
373 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>;
374 def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA),
375 "subfme $rT, $rA", IntGeneral,
376 [(set G8RC:$rT, (sube -1, G8RC:$rA))]>;
377 def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA),
378 "subfze $rT, $rA", IntGeneral,
379 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>;
383 def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
384 "mulhd $rT, $rA, $rB", IntMulHW,
385 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
386 def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
387 "mulhdu $rT, $rA, $rB", IntMulHWU,
388 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
390 def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
391 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
392 def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
393 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
394 def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm),
395 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
396 def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2),
397 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
399 def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
400 "sld $rA, $rS, $rB", IntRotateD,
401 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64;
402 def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
403 "srd $rA, $rS, $rB", IntRotateD,
404 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64;
405 let Defs = [CARRY] in {
406 def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
407 "srad $rA, $rS, $rB", IntRotateD,
408 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64;
411 def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS),
412 "extsb $rA, $rS", IntGeneral,
413 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>;
414 def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS),
415 "extsh $rA, $rS", IntGeneral,
416 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>;
418 def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS),
419 "extsw $rA, $rS", IntGeneral,
420 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
421 /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
422 def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS),
423 "extsw $rA, $rS", IntGeneral,
424 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
425 def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS),
426 "extsw $rA, $rS", IntGeneral,
427 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64;
429 let Defs = [CARRY] in {
430 def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH),
431 "sradi $rA, $rS, $SH", IntRotateD,
432 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64;
434 def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS),
435 "cntlzd $rA, $rS", IntGeneral,
436 [(set G8RC:$rA, (ctlz G8RC:$rS))]>;
438 def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
439 "divd $rT, $rA, $rB", IntDivD,
440 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
441 PPC970_DGroup_First, PPC970_DGroup_Cracked;
442 def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
443 "divdu $rT, $rA, $rB", IntDivD,
444 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
445 PPC970_DGroup_First, PPC970_DGroup_Cracked;
446 def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
447 "mulld $rT, $rA, $rB", IntMulHD,
448 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
451 let isCommutable = 1 in {
452 def RLDIMI : MDForm_1<30, 3,
453 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
454 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
455 []>, isPPC64, RegConstraint<"$rSi = $rA">,
459 // Rotate instructions.
460 def RLDCL : MDForm_1<30, 0,
461 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MB),
462 "rldcl $rA, $rS, $rB, $MB", IntRotateD,
464 def RLDICL : MDForm_1<30, 0,
465 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB),
466 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
468 def RLDICR : MDForm_1<30, 1,
469 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME),
470 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
473 def RLWINM8 : MForm_2<21,
474 (outs G8RC:$rA), (ins G8RC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
475 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
478 } // End FXU Operations.
481 //===----------------------------------------------------------------------===//
482 // Load/Store instructions.
486 // Sign extending loads.
487 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
488 def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src),
489 "lha $rD, $src", LdStLHA,
490 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>,
491 PPC970_DGroup_Cracked;
492 def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src),
493 "lwa $rD, $src", LdStLWA,
494 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64,
495 PPC970_DGroup_Cracked;
496 def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src),
497 "lhax $rD, $src", LdStLHA,
498 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>,
499 PPC970_DGroup_Cracked;
500 def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src),
501 "lwax $rD, $src", LdStLHA,
502 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
503 PPC970_DGroup_Cracked;
507 def LHAU8 : DForm_1a<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp,
509 "lhau $rD, $disp($rA)", LdStGeneral,
510 []>, RegConstraint<"$rA = $ea_result">,
511 NoEncode<"$ea_result">;
516 // Zero extending loads.
517 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
518 def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src),
519 "lbz $rD, $src", LdStGeneral,
520 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
521 def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src),
522 "lhz $rD, $src", LdStGeneral,
523 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>;
524 def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src),
525 "lwz $rD, $src", LdStGeneral,
526 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
528 def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src),
529 "lbzx $rD, $src", LdStGeneral,
530 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>;
531 def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src),
532 "lhzx $rD, $src", LdStGeneral,
533 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>;
534 def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src),
535 "lwzx $rD, $src", LdStGeneral,
536 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>;
541 def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
542 "lbzu $rD, $addr", LdStGeneral,
543 []>, RegConstraint<"$addr.reg = $ea_result">,
544 NoEncode<"$ea_result">;
545 def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
546 "lhzu $rD, $addr", LdStGeneral,
547 []>, RegConstraint<"$addr.reg = $ea_result">,
548 NoEncode<"$ea_result">;
549 def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
550 "lwzu $rD, $addr", LdStGeneral,
551 []>, RegConstraint<"$addr.reg = $ea_result">,
552 NoEncode<"$ea_result">;
557 // Full 8-byte loads.
558 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
559 def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
560 "ld $rD, $src", LdStLD,
561 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
562 def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
565 (PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64;
567 let hasSideEffects = 1 in {
568 let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo.
569 def LDinto_toc: DSForm_1<58, 0, (outs), (ins G8RC:$reg),
570 "ld 2, 8($reg)", LdStLD,
571 [(PPCload_toc G8RC:$reg)]>, isPPC64;
573 let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo.
574 def LDtoc_restore : DSForm_1<58, 0, (outs), (ins),
575 "ld 2, 40(1)", LdStLD,
576 [(PPCtoc_restore)]>, isPPC64;
578 def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
579 "ldx $rD, $src", LdStLD,
580 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
583 def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr),
584 "ldu $rD, $addr", LdStLD,
585 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
586 NoEncode<"$ea_result">;
590 def : Pat<(PPCload ixaddr:$src),
592 def : Pat<(PPCload xaddr:$src),
595 let PPC970_Unit = 2 in {
596 // Truncating stores.
597 def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src),
598 "stb $rS, $src", LdStGeneral,
599 [(truncstorei8 G8RC:$rS, iaddr:$src)]>;
600 def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src),
601 "sth $rS, $src", LdStGeneral,
602 [(truncstorei16 G8RC:$rS, iaddr:$src)]>;
603 def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src),
604 "stw $rS, $src", LdStGeneral,
605 [(truncstorei32 G8RC:$rS, iaddr:$src)]>;
606 def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst),
607 "stbx $rS, $dst", LdStGeneral,
608 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>,
609 PPC970_DGroup_Cracked;
610 def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst),
611 "sthx $rS, $dst", LdStGeneral,
612 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>,
613 PPC970_DGroup_Cracked;
614 def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst),
615 "stwx $rS, $dst", LdStGeneral,
616 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>,
617 PPC970_DGroup_Cracked;
618 // Normal 8-byte stores.
619 def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst),
620 "std $rS, $dst", LdStSTD,
621 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
622 def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst),
623 "stdx $rS, $dst", LdStSTD,
624 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64,
625 PPC970_DGroup_Cracked;
628 let PPC970_Unit = 2 in {
630 def STBU8 : DForm_1a<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
631 symbolLo:$ptroff, ptr_rc:$ptrreg),
632 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
633 [(set ptr_rc:$ea_res,
634 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg,
635 iaddroff:$ptroff))]>,
636 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
637 def STHU8 : DForm_1a<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
638 symbolLo:$ptroff, ptr_rc:$ptrreg),
639 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
640 [(set ptr_rc:$ea_res,
641 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg,
642 iaddroff:$ptroff))]>,
643 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
645 def STDU : DSForm_1a<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
646 s16immX4:$ptroff, ptr_rc:$ptrreg),
647 "stdu $rS, $ptroff($ptrreg)", LdStSTD,
648 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
649 iaddroff:$ptroff))]>,
650 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
654 def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst),
655 "stdux $rS, $dst", LdStSTD,
658 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
659 def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst),
660 "std $rT, $dst", LdStSTD,
661 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64;
662 def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst),
663 "stdx $rT, $dst", LdStSTD,
664 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64,
665 PPC970_DGroup_Cracked;
670 //===----------------------------------------------------------------------===//
671 // Floating point instructions.
675 let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations.
676 def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB),
677 "fcfid $frD, $frB", FPGeneral,
678 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
679 def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB),
680 "fctidz $frD, $frB", FPGeneral,
681 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
685 //===----------------------------------------------------------------------===//
686 // Instruction Patterns
689 // Extensions and truncates to/from 32-bit regs.
690 def : Pat<(i64 (zext GPRC:$in)),
691 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
692 def : Pat<(i64 (anyext GPRC:$in)),
693 (OR4To8 GPRC:$in, GPRC:$in)>;
694 def : Pat<(i32 (trunc G8RC:$in)),
695 (OR8To4 G8RC:$in, G8RC:$in)>;
697 // Extending loads with i64 targets.
698 def : Pat<(zextloadi1 iaddr:$src),
700 def : Pat<(zextloadi1 xaddr:$src),
702 def : Pat<(extloadi1 iaddr:$src),
704 def : Pat<(extloadi1 xaddr:$src),
706 def : Pat<(extloadi8 iaddr:$src),
708 def : Pat<(extloadi8 xaddr:$src),
710 def : Pat<(extloadi16 iaddr:$src),
712 def : Pat<(extloadi16 xaddr:$src),
714 def : Pat<(extloadi32 iaddr:$src),
716 def : Pat<(extloadi32 xaddr:$src),
719 // Standard shifts. These are represented separately from the real shifts above
720 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
722 def : Pat<(sra G8RC:$rS, GPRC:$rB),
723 (SRAD G8RC:$rS, GPRC:$rB)>;
724 def : Pat<(srl G8RC:$rS, GPRC:$rB),
725 (SRD G8RC:$rS, GPRC:$rB)>;
726 def : Pat<(shl G8RC:$rS, GPRC:$rB),
727 (SLD G8RC:$rS, GPRC:$rB)>;
730 def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
731 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
732 def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
733 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
736 def : Pat<(rotl G8RC:$in, GPRC:$sh),
737 (RLDCL G8RC:$in, GPRC:$sh, 0)>;
738 def : Pat<(rotl G8RC:$in, (i32 imm:$imm)),
739 (RLDICL G8RC:$in, imm:$imm, 0)>;
741 // Hi and Lo for Darwin Global Addresses.
742 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
743 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
744 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
745 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
746 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
747 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
748 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
749 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
750 def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
751 (ADDIS8 G8RC:$in, tglobaladdr:$g)>;
752 def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)),
753 (ADDIS8 G8RC:$in, tconstpool:$g)>;
754 def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
755 (ADDIS8 G8RC:$in, tjumptable:$g)>;
756 def : Pat<(add G8RC:$in, (PPChi tblockaddress:$g, 0)),
757 (ADDIS8 G8RC:$in, tblockaddress:$g)>;